2 * Copyright © 2014 Broadcom
3 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "pipe/p_context.h"
31 #include "pipe/p_state.h"
32 #include "util/slab.h"
37 #include "vc4_bufmgr.h"
38 #include "vc4_resource.h"
42 #ifndef DRM_VC4_PARAM_SUPPORTS_ETC1
43 #define DRM_VC4_PARAM_SUPPORTS_ETC1 4
45 #ifndef DRM_VC4_PARAM_SUPPORTS_THREADED_FS
46 #define DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5
49 #ifdef USE_VC4_SIMULATOR
50 #define using_vc4_simulator true
52 #define using_vc4_simulator false
55 #define VC4_DIRTY_BLEND (1 << 0)
56 #define VC4_DIRTY_RASTERIZER (1 << 1)
57 #define VC4_DIRTY_ZSA (1 << 2)
58 #define VC4_DIRTY_FRAGTEX (1 << 3)
59 #define VC4_DIRTY_VERTTEX (1 << 4)
61 #define VC4_DIRTY_BLEND_COLOR (1 << 7)
62 #define VC4_DIRTY_STENCIL_REF (1 << 8)
63 #define VC4_DIRTY_SAMPLE_MASK (1 << 9)
64 #define VC4_DIRTY_FRAMEBUFFER (1 << 10)
65 #define VC4_DIRTY_STIPPLE (1 << 11)
66 #define VC4_DIRTY_VIEWPORT (1 << 12)
67 #define VC4_DIRTY_CONSTBUF (1 << 13)
68 #define VC4_DIRTY_VTXSTATE (1 << 14)
69 #define VC4_DIRTY_VTXBUF (1 << 15)
71 #define VC4_DIRTY_SCISSOR (1 << 17)
72 #define VC4_DIRTY_FLAT_SHADE_FLAGS (1 << 18)
73 #define VC4_DIRTY_PRIM_MODE (1 << 19)
74 #define VC4_DIRTY_CLIP (1 << 20)
75 #define VC4_DIRTY_UNCOMPILED_VS (1 << 21)
76 #define VC4_DIRTY_UNCOMPILED_FS (1 << 22)
77 #define VC4_DIRTY_COMPILED_CS (1 << 23)
78 #define VC4_DIRTY_COMPILED_VS (1 << 24)
79 #define VC4_DIRTY_COMPILED_FS (1 << 25)
80 #define VC4_DIRTY_FS_INPUTS (1 << 26)
81 #define VC4_DIRTY_UBO_1_SIZE (1 << 27)
83 struct vc4_sampler_view
{
84 struct pipe_sampler_view base
;
87 bool force_first_level
;
89 * Resource containing the actual texture that will be sampled.
91 * We may need to rebase the .base.texture resource to work around the
92 * lack of GL_TEXTURE_BASE_LEVEL, or to upload the texture as tiled.
94 struct pipe_resource
*texture
;
97 struct vc4_sampler_state
{
98 struct pipe_sampler_state base
;
102 struct vc4_texture_stateobj
{
103 struct pipe_sampler_view
*textures
[PIPE_MAX_SAMPLERS
];
104 unsigned num_textures
;
105 struct pipe_sampler_state
*samplers
[PIPE_MAX_SAMPLERS
];
106 unsigned num_samplers
;
109 struct vc4_shader_uniform_info
{
110 enum quniform_contents
*contents
;
113 uint32_t num_texture_samples
;
116 struct vc4_uncompiled_shader
{
117 /** A name for this program, so you can track it in shader-db output. */
119 /** How many variants of this program were compiled, for shader-db. */
120 uint32_t compiled_variant_count
;
121 struct pipe_shader_state base
;
124 struct vc4_ubo_range
{
126 * offset in bytes from the start of the ubo where this range is
129 * Only set once used is set.
134 * offset in bytes from the start of the gallium uniforms where the
139 /** size in bytes of this ubo range */
143 struct vc4_fs_inputs
{
145 * Array of the meanings of the VPM inputs this shader needs.
147 * It doesn't include those that aren't part of the VPM, like
148 * point/line coordinates.
150 struct vc4_varying_slot
*input_slots
;
154 struct vc4_compiled_shader
{
158 struct vc4_shader_uniform_info uniforms
;
160 struct vc4_ubo_range
*ubo_ranges
;
161 uint32_t num_ubo_ranges
;
164 * VC4_DIRTY_* flags that, when set in vc4->dirty, mean that the
165 * uniforms have to be rewritten (and therefore the shader state
168 uint32_t uniform_dirty_bits
;
170 /** bitmask of which inputs are color inputs, for flat shade handling. */
171 uint32_t color_inputs
;
173 bool disable_early_z
;
175 /* Set if the compile failed, likely due to register allocation
176 * failure. In this case, we have no shader to run and should not try
185 /* Byte offsets for the start of the vertex attributes 0-7, and the
186 * total size as "attribute" 8.
188 uint8_t vattr_offsets
[9];
191 const struct vc4_fs_inputs
*fs_inputs
;
194 struct vc4_program_stateobj
{
195 struct vc4_uncompiled_shader
*bind_vs
, *bind_fs
;
196 struct vc4_compiled_shader
*cs
, *vs
, *fs
;
199 struct vc4_constbuf_stateobj
{
200 struct pipe_constant_buffer cb
[PIPE_MAX_CONSTANT_BUFFERS
];
201 uint32_t enabled_mask
;
205 struct vc4_vertexbuf_stateobj
{
206 struct pipe_vertex_buffer vb
[PIPE_MAX_ATTRIBS
];
208 uint32_t enabled_mask
;
212 struct vc4_vertex_stateobj
{
213 struct pipe_vertex_element pipe
[PIPE_MAX_ATTRIBS
];
214 unsigned num_elements
;
217 /* Hash table key for vc4->jobs */
219 struct pipe_surface
*cbuf
;
220 struct pipe_surface
*zsbuf
;
223 struct vc4_hwperfmon
{
226 uint8_t events
[DRM_VC4_MAX_PERF_COUNTERS
];
227 uint64_t counters
[DRM_VC4_MAX_PERF_COUNTERS
];
231 * A complete bin/render job.
233 * This is all of the state necessary to submit a bin/render to the kernel.
234 * We want to be able to have multiple in progress at a time, so that we don't
235 * need to flush an existing CL just to switch to rendering to a new render
236 * target (which would mean reading back from the old render target when
237 * starting to render to it again).
241 struct vc4_cl shader_rec
;
242 struct vc4_cl uniforms
;
243 struct vc4_cl bo_handles
;
244 struct vc4_cl bo_pointers
;
245 uint32_t shader_rec_count
;
247 * Amount of memory used by the BOs in bo_pointers.
249 * Used for checking when we should flush the job early so we don't
254 /* Last BO hindex referenced from VC4_PACKET_GEM_HANDLES. */
255 uint32_t last_gem_handle_hindex
;
257 /** @{ Surfaces to submit rendering for. */
258 struct pipe_surface
*color_read
;
259 struct pipe_surface
*color_write
;
260 struct pipe_surface
*zs_read
;
261 struct pipe_surface
*zs_write
;
262 struct pipe_surface
*msaa_color_write
;
263 struct pipe_surface
*msaa_zs_write
;
266 * Bounding box of the scissor across all queued drawing.
268 * Note that the max values are exclusive.
276 * Width/height of the color framebuffer being rendered to,
277 * for VC4_TILE_RENDERING_MODE_CONFIG.
280 uint32_t draw_height
;
282 /** @{ Tile information, depending on MSAA and float color buffer. */
283 uint32_t draw_tiles_x
; /** @< Number of tiles wide for framebuffer. */
284 uint32_t draw_tiles_y
; /** @< Number of tiles high for framebuffer. */
286 uint32_t tile_width
; /** @< Width of a tile. */
287 uint32_t tile_height
; /** @< Height of a tile. */
288 /** Whether the current rendering is in a 4X MSAA tile buffer. */
292 /* Bitmask of PIPE_CLEAR_* of buffers that were cleared before the
296 /* Bitmask of PIPE_CLEAR_* of buffers that have been rendered to
297 * (either clears or draws).
300 uint32_t clear_color
[2];
301 uint32_t clear_depth
; /**< 24-bit unorm depth */
302 uint8_t clear_stencil
;
305 * Set if some drawing (triangles, blits, or just a glClear()) has
306 * been done to the FBO, meaning that we need to
307 * DRM_IOCTL_VC4_SUBMIT_CL.
312 * Number of draw calls (not counting full buffer clears) queued in
315 uint32_t draw_calls_queued
;
317 /** Any flags to be passed in drm_vc4_submit_cl.flags. */
320 /* Performance monitor attached to this job. */
321 struct vc4_hwperfmon
*perfmon
;
323 struct vc4_job_key key
;
327 struct pipe_context base
;
330 struct vc4_screen
*screen
;
332 /** The 3D rendering job for the currently bound FBO. */
335 /* Map from struct vc4_job_key to the job for that FBO.
337 struct hash_table
*jobs
;
340 * Map from vc4_resource to a job writing to that resource.
342 * Primarily for flushing jobs rendering to textures that are now
345 struct hash_table
*write_jobs
;
347 struct slab_child_pool transfer_pool
;
348 struct blitter_context
*blitter
;
350 /** bitfield of VC4_DIRTY_* */
353 struct primconvert_context
*primconvert
;
355 struct hash_table
*fs_cache
, *vs_cache
;
356 struct set
*fs_inputs_set
;
357 uint32_t next_uncompiled_program_id
;
358 uint64_t next_compiled_program_id
;
360 struct ra_regs
*regs
;
361 unsigned int reg_class_any
[2];
362 unsigned int reg_class_a_or_b
[2];
363 unsigned int reg_class_a_or_b_or_acc
[2];
364 unsigned int reg_class_r0_r3
;
365 unsigned int reg_class_r4_or_a
[2];
366 unsigned int reg_class_a
[2];
370 /** Maximum index buffer valid for the current shader_rec. */
372 /** Last index bias baked into the current shader_rec. */
373 uint32_t last_index_bias
;
375 /** Seqno of the last CL flush's job. */
376 uint64_t last_emit_seqno
;
378 struct u_upload_mgr
*uploader
;
380 struct pipe_shader_state
*yuv_linear_blit_vs
;
381 struct pipe_shader_state
*yuv_linear_blit_fs_8bit
;
382 struct pipe_shader_state
*yuv_linear_blit_fs_16bit
;
384 /** @{ Current pipeline state objects */
385 struct pipe_scissor_state scissor
;
386 struct pipe_blend_state
*blend
;
387 struct vc4_rasterizer_state
*rasterizer
;
388 struct vc4_depth_stencil_alpha_state
*zsa
;
390 struct vc4_texture_stateobj verttex
, fragtex
;
392 struct vc4_program_stateobj prog
;
394 struct vc4_vertex_stateobj
*vtx
;
397 struct pipe_blend_color f
;
400 struct pipe_stencil_ref stencil_ref
;
401 unsigned sample_mask
;
402 struct pipe_framebuffer_state framebuffer
;
403 struct pipe_poly_stipple stipple
;
404 struct pipe_clip_state clip
;
405 struct pipe_viewport_state viewport
;
406 struct vc4_constbuf_stateobj constbuf
[PIPE_SHADER_TYPES
];
407 struct vc4_vertexbuf_stateobj vertexbuf
;
409 struct vc4_hwperfmon
*perfmon
;
413 struct vc4_rasterizer_state
{
414 struct pipe_rasterizer_state base
;
416 /* VC4_CONFIGURATION_BITS */
417 uint8_t config_bits
[V3D21_CONFIGURATION_BITS_length
];
420 uint8_t depth_offset
[V3D21_DEPTH_OFFSET_length
];
421 uint8_t point_size
[V3D21_POINT_SIZE_length
];
422 uint8_t line_width
[V3D21_LINE_WIDTH_length
];
425 /** Raster order flags to be passed in struct drm_vc4_submit_cl.flags. */
426 uint32_t tile_raster_order_flags
;
429 struct vc4_depth_stencil_alpha_state
{
430 struct pipe_depth_stencil_alpha_state base
;
432 /* VC4_CONFIGURATION_BITS */
433 uint8_t config_bits
[V3D21_CONFIGURATION_BITS_length
];
435 /** Uniforms for stencil state.
437 * Index 0 is either the front config, or the front-and-back config.
438 * Index 1 is the back config if doing separate back stencil.
439 * Index 2 is the writemask config if it's not a common mask value.
441 uint32_t stencil_uniforms
[3];
444 #define perf_debug(...) do { \
445 if (unlikely(vc4_debug & VC4_DEBUG_PERF)) \
446 fprintf(stderr, __VA_ARGS__); \
449 static inline struct vc4_context
*
450 vc4_context(struct pipe_context
*pcontext
)
452 return (struct vc4_context
*)pcontext
;
455 static inline struct vc4_sampler_view
*
456 vc4_sampler_view(struct pipe_sampler_view
*psview
)
458 return (struct vc4_sampler_view
*)psview
;
461 static inline struct vc4_sampler_state
*
462 vc4_sampler_state(struct pipe_sampler_state
*psampler
)
464 return (struct vc4_sampler_state
*)psampler
;
467 int vc4_get_driver_query_group_info(struct pipe_screen
*pscreen
,
469 struct pipe_driver_query_group_info
*info
);
470 int vc4_get_driver_query_info(struct pipe_screen
*pscreen
, unsigned index
,
471 struct pipe_driver_query_info
*info
);
473 struct pipe_context
*vc4_context_create(struct pipe_screen
*pscreen
,
474 void *priv
, unsigned flags
);
475 void vc4_draw_init(struct pipe_context
*pctx
);
476 void vc4_state_init(struct pipe_context
*pctx
);
477 void vc4_program_init(struct pipe_context
*pctx
);
478 void vc4_program_fini(struct pipe_context
*pctx
);
479 void vc4_query_init(struct pipe_context
*pctx
);
480 void vc4_simulator_init(struct vc4_screen
*screen
);
481 void vc4_simulator_destroy(struct vc4_screen
*screen
);
482 int vc4_simulator_flush(struct vc4_context
*vc4
,
483 struct drm_vc4_submit_cl
*args
,
484 struct vc4_job
*job
);
485 int vc4_simulator_ioctl(int fd
, unsigned long request
, void *arg
);
486 void vc4_simulator_open_from_handle(int fd
, uint32_t winsys_stride
,
487 int handle
, uint32_t size
);
490 vc4_ioctl(int fd
, unsigned long request
, void *arg
)
492 if (using_vc4_simulator
)
493 return vc4_simulator_ioctl(fd
, request
, arg
);
495 return drmIoctl(fd
, request
, arg
);
498 void vc4_set_shader_uniform_dirty_flags(struct vc4_compiled_shader
*shader
);
499 void vc4_write_uniforms(struct vc4_context
*vc4
,
500 struct vc4_compiled_shader
*shader
,
501 struct vc4_constbuf_stateobj
*cb
,
502 struct vc4_texture_stateobj
*texstate
);
504 void vc4_flush(struct pipe_context
*pctx
);
505 void vc4_job_init(struct vc4_context
*vc4
);
506 struct vc4_job
*vc4_get_job(struct vc4_context
*vc4
,
507 struct pipe_surface
*cbuf
,
508 struct pipe_surface
*zsbuf
);
509 struct vc4_job
*vc4_get_job_for_fbo(struct vc4_context
*vc4
);
511 void vc4_job_submit(struct vc4_context
*vc4
, struct vc4_job
*job
);
512 void vc4_flush_jobs_writing_resource(struct vc4_context
*vc4
,
513 struct pipe_resource
*prsc
);
514 void vc4_flush_jobs_reading_resource(struct vc4_context
*vc4
,
515 struct pipe_resource
*prsc
);
516 void vc4_emit_state(struct pipe_context
*pctx
);
517 void vc4_generate_code(struct vc4_context
*vc4
, struct vc4_compile
*c
);
518 struct qpu_reg
*vc4_register_allocate(struct vc4_context
*vc4
, struct vc4_compile
*c
);
519 bool vc4_update_compiled_shaders(struct vc4_context
*vc4
, uint8_t prim_mode
);
521 bool vc4_rt_format_supported(enum pipe_format f
);
522 bool vc4_rt_format_is_565(enum pipe_format f
);
523 bool vc4_tex_format_supported(enum pipe_format f
);
524 uint8_t vc4_get_tex_format(enum pipe_format f
);
525 const uint8_t *vc4_get_format_swizzle(enum pipe_format f
);
526 void vc4_init_query_functions(struct vc4_context
*vc4
);
527 void vc4_blit(struct pipe_context
*pctx
, const struct pipe_blit_info
*blit_info
);
528 void vc4_blitter_save(struct vc4_context
*vc4
);
529 #endif /* VC4_CONTEXT_H */