vc4: Disable early Z with computed depth.
[mesa.git] / src / gallium / drivers / vc4 / vc4_context.h
1 /*
2 * Copyright © 2014 Broadcom
3 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #ifndef VC4_CONTEXT_H
26 #define VC4_CONTEXT_H
27
28 #include <stdio.h>
29
30 #include "pipe/p_context.h"
31 #include "pipe/p_state.h"
32 #include "util/u_slab.h"
33
34 #define __user
35 #include "vc4_drm.h"
36 #include "vc4_bufmgr.h"
37 #include "vc4_resource.h"
38 #include "vc4_cl.h"
39 #include "vc4_qir.h"
40
41 #ifdef USE_VC4_SIMULATOR
42 #define using_vc4_simulator true
43 #else
44 #define using_vc4_simulator false
45 #endif
46
47 #define VC4_DIRTY_BLEND (1 << 0)
48 #define VC4_DIRTY_RASTERIZER (1 << 1)
49 #define VC4_DIRTY_ZSA (1 << 2)
50 #define VC4_DIRTY_FRAGTEX (1 << 3)
51 #define VC4_DIRTY_VERTTEX (1 << 4)
52
53 #define VC4_DIRTY_BLEND_COLOR (1 << 7)
54 #define VC4_DIRTY_STENCIL_REF (1 << 8)
55 #define VC4_DIRTY_SAMPLE_MASK (1 << 9)
56 #define VC4_DIRTY_FRAMEBUFFER (1 << 10)
57 #define VC4_DIRTY_STIPPLE (1 << 11)
58 #define VC4_DIRTY_VIEWPORT (1 << 12)
59 #define VC4_DIRTY_CONSTBUF (1 << 13)
60 #define VC4_DIRTY_VTXSTATE (1 << 14)
61 #define VC4_DIRTY_VTXBUF (1 << 15)
62 #define VC4_DIRTY_INDEXBUF (1 << 16)
63 #define VC4_DIRTY_SCISSOR (1 << 17)
64 #define VC4_DIRTY_FLAT_SHADE_FLAGS (1 << 18)
65 #define VC4_DIRTY_PRIM_MODE (1 << 19)
66 #define VC4_DIRTY_CLIP (1 << 20)
67 #define VC4_DIRTY_UNCOMPILED_VS (1 << 21)
68 #define VC4_DIRTY_UNCOMPILED_FS (1 << 22)
69 #define VC4_DIRTY_COMPILED_CS (1 << 23)
70 #define VC4_DIRTY_COMPILED_VS (1 << 24)
71 #define VC4_DIRTY_COMPILED_FS (1 << 25)
72
73 struct vc4_sampler_view {
74 struct pipe_sampler_view base;
75 uint32_t texture_p0;
76 uint32_t texture_p1;
77 bool force_first_level;
78 };
79
80 struct vc4_sampler_state {
81 struct pipe_sampler_state base;
82 uint32_t texture_p1;
83 };
84
85 struct vc4_texture_stateobj {
86 struct pipe_sampler_view *textures[PIPE_MAX_SAMPLERS];
87 unsigned num_textures;
88 struct pipe_sampler_state *samplers[PIPE_MAX_SAMPLERS];
89 unsigned num_samplers;
90 };
91
92 struct vc4_shader_uniform_info {
93 enum quniform_contents *contents;
94 uint32_t *data;
95 uint32_t count;
96 uint32_t num_texture_samples;
97 };
98
99 struct vc4_uncompiled_shader {
100 /** A name for this program, so you can track it in shader-db output. */
101 uint32_t program_id;
102 /** How many variants of this program were compiled, for shader-db. */
103 uint32_t compiled_variant_count;
104 struct pipe_shader_state base;
105 };
106
107 struct vc4_ubo_range {
108 /**
109 * offset in bytes from the start of the ubo where this range is
110 * uploaded.
111 *
112 * Only set once used is set.
113 */
114 uint32_t dst_offset;
115
116 /**
117 * offset in bytes from the start of the gallium uniforms where the
118 * data comes from.
119 */
120 uint32_t src_offset;
121
122 /** size in bytes of this ubo range */
123 uint32_t size;
124 };
125
126 struct vc4_compiled_shader {
127 uint64_t program_id;
128 struct vc4_bo *bo;
129
130 struct vc4_shader_uniform_info uniforms;
131
132 struct vc4_ubo_range *ubo_ranges;
133 uint32_t num_ubo_ranges;
134 uint32_t ubo_size;
135 /**
136 * VC4_DIRTY_* flags that, when set in vc4->dirty, mean that the
137 * uniforms have to be rewritten (and therefore the shader state
138 * reemitted).
139 */
140 uint32_t uniform_dirty_bits;
141
142 /** bitmask of which inputs are color inputs, for flat shade handling. */
143 uint32_t color_inputs;
144
145 bool disable_early_z;
146
147 uint8_t num_inputs;
148
149 /* Byte offsets for the start of the vertex attributes 0-7, and the
150 * total size as "attribute" 8.
151 */
152 uint8_t vattr_offsets[9];
153 uint8_t vattrs_live;
154
155 /**
156 * Array of the meanings of the VPM inputs this shader needs.
157 *
158 * It doesn't include those that aren't part of the VPM, like
159 * point/line coordinates.
160 */
161 struct vc4_varying_slot *input_slots;
162 };
163
164 struct vc4_program_stateobj {
165 struct vc4_uncompiled_shader *bind_vs, *bind_fs;
166 struct vc4_compiled_shader *cs, *vs, *fs;
167 };
168
169 struct vc4_constbuf_stateobj {
170 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
171 uint32_t enabled_mask;
172 uint32_t dirty_mask;
173 };
174
175 struct vc4_vertexbuf_stateobj {
176 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
177 unsigned count;
178 uint32_t enabled_mask;
179 uint32_t dirty_mask;
180 };
181
182 struct vc4_vertex_stateobj {
183 struct pipe_vertex_element pipe[PIPE_MAX_ATTRIBS];
184 unsigned num_elements;
185 };
186
187 struct vc4_context {
188 struct pipe_context base;
189
190 int fd;
191 struct vc4_screen *screen;
192
193 struct vc4_cl bcl;
194 struct vc4_cl shader_rec;
195 struct vc4_cl uniforms;
196 struct vc4_cl bo_handles;
197 struct vc4_cl bo_pointers;
198 uint32_t shader_rec_count;
199
200 /** @{ Surfaces to submit rendering for. */
201 struct pipe_surface *color_read;
202 struct pipe_surface *color_write;
203 struct pipe_surface *zs_read;
204 struct pipe_surface *zs_write;
205 struct pipe_surface *msaa_color_write;
206 struct pipe_surface *msaa_zs_write;
207 /** @} */
208 /** @{
209 * Bounding box of the scissor across all queued drawing.
210 *
211 * Note that the max values are exclusive.
212 */
213 uint32_t draw_min_x;
214 uint32_t draw_min_y;
215 uint32_t draw_max_x;
216 uint32_t draw_max_y;
217 /** @} */
218 /** @{
219 * Width/height of the color framebuffer being rendered to,
220 * for VC4_TILE_RENDERING_MODE_CONFIG.
221 */
222 uint32_t draw_width;
223 uint32_t draw_height;
224 /** @} */
225 /** @{ Tile information, depending on MSAA and float color buffer. */
226 uint32_t draw_tiles_x; /** @< Number of tiles wide for framebuffer. */
227 uint32_t draw_tiles_y; /** @< Number of tiles high for framebuffer. */
228
229 uint32_t tile_width; /** @< Width of a tile. */
230 uint32_t tile_height; /** @< Height of a tile. */
231 /** Whether the current rendering is in a 4X MSAA tile buffer. */
232 bool msaa;
233 /** @} */
234
235 struct util_slab_mempool transfer_pool;
236 struct blitter_context *blitter;
237
238 /** bitfield of VC4_DIRTY_* */
239 uint32_t dirty;
240 /* Bitmask of PIPE_CLEAR_* of buffers that were cleared before the
241 * first rendering.
242 */
243 uint32_t cleared;
244 /* Bitmask of PIPE_CLEAR_* of buffers that have been rendered to
245 * (either clears or draws).
246 */
247 uint32_t resolve;
248 uint32_t clear_color[2];
249 uint32_t clear_depth; /**< 24-bit unorm depth */
250 uint8_t clear_stencil;
251
252 /**
253 * Set if some drawing (triangles, blits, or just a glClear()) has
254 * been done to the FBO, meaning that we need to
255 * DRM_IOCTL_VC4_SUBMIT_CL.
256 */
257 bool needs_flush;
258
259 /**
260 * Number of draw calls (not counting full buffer clears) queued in
261 * the current job.
262 */
263 uint32_t draw_calls_queued;
264
265 /** Maximum index buffer valid for the current shader_rec. */
266 uint32_t max_index;
267 /** Last index bias baked into the current shader_rec. */
268 uint32_t last_index_bias;
269
270 struct primconvert_context *primconvert;
271
272 struct hash_table *fs_cache, *vs_cache;
273 uint32_t next_uncompiled_program_id;
274 uint64_t next_compiled_program_id;
275
276 struct ra_regs *regs;
277 unsigned int reg_class_any;
278 unsigned int reg_class_a_or_b_or_acc;
279 unsigned int reg_class_r4_or_a;
280 unsigned int reg_class_a;
281
282 uint8_t prim_mode;
283
284 /** Seqno of the last CL flush's job. */
285 uint64_t last_emit_seqno;
286
287 struct u_upload_mgr *uploader;
288
289 /** @{ Current pipeline state objects */
290 struct pipe_scissor_state scissor;
291 struct pipe_blend_state *blend;
292 struct vc4_rasterizer_state *rasterizer;
293 struct vc4_depth_stencil_alpha_state *zsa;
294
295 struct vc4_texture_stateobj verttex, fragtex;
296
297 struct vc4_program_stateobj prog;
298
299 struct vc4_vertex_stateobj *vtx;
300
301 struct {
302 struct pipe_blend_color f;
303 uint8_t ub[4];
304 } blend_color;
305 struct pipe_stencil_ref stencil_ref;
306 unsigned sample_mask;
307 struct pipe_framebuffer_state framebuffer;
308 struct pipe_poly_stipple stipple;
309 struct pipe_clip_state clip;
310 struct pipe_viewport_state viewport;
311 struct vc4_constbuf_stateobj constbuf[PIPE_SHADER_TYPES];
312 struct vc4_vertexbuf_stateobj vertexbuf;
313 struct pipe_index_buffer indexbuf;
314 /** @} */
315 };
316
317 struct vc4_rasterizer_state {
318 struct pipe_rasterizer_state base;
319
320 /* VC4_CONFIGURATION_BITS */
321 uint8_t config_bits[3];
322
323 float point_size;
324
325 /**
326 * Half-float (1/8/7 bits) value of polygon offset units for
327 * VC4_PACKET_DEPTH_OFFSET
328 */
329 uint16_t offset_units;
330 /**
331 * Half-float (1/8/7 bits) value of polygon offset scale for
332 * VC4_PACKET_DEPTH_OFFSET
333 */
334 uint16_t offset_factor;
335 };
336
337 struct vc4_depth_stencil_alpha_state {
338 struct pipe_depth_stencil_alpha_state base;
339
340 /* VC4_CONFIGURATION_BITS */
341 uint8_t config_bits[3];
342
343 /** Uniforms for stencil state.
344 *
345 * Index 0 is either the front config, or the front-and-back config.
346 * Index 1 is the back config if doing separate back stencil.
347 * Index 2 is the writemask config if it's not a common mask value.
348 */
349 uint32_t stencil_uniforms[3];
350 };
351
352 #define perf_debug(...) do { \
353 if (unlikely(vc4_debug & VC4_DEBUG_PERF)) \
354 fprintf(stderr, __VA_ARGS__); \
355 } while (0)
356
357 static inline struct vc4_context *
358 vc4_context(struct pipe_context *pcontext)
359 {
360 return (struct vc4_context *)pcontext;
361 }
362
363 static inline struct vc4_sampler_view *
364 vc4_sampler_view(struct pipe_sampler_view *psview)
365 {
366 return (struct vc4_sampler_view *)psview;
367 }
368
369 static inline struct vc4_sampler_state *
370 vc4_sampler_state(struct pipe_sampler_state *psampler)
371 {
372 return (struct vc4_sampler_state *)psampler;
373 }
374
375 struct pipe_context *vc4_context_create(struct pipe_screen *pscreen,
376 void *priv, unsigned flags);
377 void vc4_draw_init(struct pipe_context *pctx);
378 void vc4_state_init(struct pipe_context *pctx);
379 void vc4_program_init(struct pipe_context *pctx);
380 void vc4_program_fini(struct pipe_context *pctx);
381 void vc4_query_init(struct pipe_context *pctx);
382 void vc4_simulator_init(struct vc4_screen *screen);
383 int vc4_simulator_flush(struct vc4_context *vc4,
384 struct drm_vc4_submit_cl *args);
385
386 void vc4_set_shader_uniform_dirty_flags(struct vc4_compiled_shader *shader);
387 void vc4_write_uniforms(struct vc4_context *vc4,
388 struct vc4_compiled_shader *shader,
389 struct vc4_constbuf_stateobj *cb,
390 struct vc4_texture_stateobj *texstate);
391
392 void vc4_flush(struct pipe_context *pctx);
393 void vc4_job_init(struct vc4_context *vc4);
394 void vc4_job_submit(struct vc4_context *vc4);
395 void vc4_job_reset(struct vc4_context *vc4);
396 bool vc4_cl_references_bo(struct pipe_context *pctx, struct vc4_bo *bo,
397 bool include_reads);
398 void vc4_emit_state(struct pipe_context *pctx);
399 void vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c);
400 struct qpu_reg *vc4_register_allocate(struct vc4_context *vc4, struct vc4_compile *c);
401 void vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode);
402
403 bool vc4_rt_format_supported(enum pipe_format f);
404 bool vc4_rt_format_is_565(enum pipe_format f);
405 bool vc4_tex_format_supported(enum pipe_format f);
406 uint8_t vc4_get_tex_format(enum pipe_format f);
407 const uint8_t *vc4_get_format_swizzle(enum pipe_format f);
408 void vc4_init_query_functions(struct vc4_context *vc4);
409 void vc4_blit(struct pipe_context *pctx, const struct pipe_blit_info *blit_info);
410 #endif /* VC4_CONTEXT_H */