src/gallium/drivers/vc4/vc4_context.h

   1 /*
   2  * Copyright © 2014 Broadcom
   3  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #ifndef VC4_CONTEXT_H
  26 #define VC4_CONTEXT_H
  27
  28 #include <stdio.h>
  29
  30 #include "pipe/p_context.h"
  31 #include "pipe/p_state.h"
  32 #include "util/slab.h"
  33
  34 #define __user
  35 #include "vc4_drm.h"
  36 #include "vc4_bufmgr.h"
  37 #include "vc4_resource.h"
  38 #include "vc4_cl.h"
  39 #include "vc4_qir.h"
  40
  41 #ifdef USE_VC4_SIMULATOR
  42 #define using_vc4_simulator true
  43 #else
  44 #define using_vc4_simulator false
  45 #endif
  46
  47 #define VC4_DIRTY_BLEND         (1 <<  0)
  48 #define VC4_DIRTY_RASTERIZER    (1 <<  1)
  49 #define VC4_DIRTY_ZSA           (1 <<  2)
  50 #define VC4_DIRTY_FRAGTEX       (1 <<  3)
  51 #define VC4_DIRTY_VERTTEX       (1 <<  4)
  52
  53 #define VC4_DIRTY_BLEND_COLOR   (1 <<  7)
  54 #define VC4_DIRTY_STENCIL_REF   (1 <<  8)
  55 #define VC4_DIRTY_SAMPLE_MASK   (1 <<  9)
  56 #define VC4_DIRTY_FRAMEBUFFER   (1 << 10)
  57 #define VC4_DIRTY_STIPPLE       (1 << 11)
  58 #define VC4_DIRTY_VIEWPORT      (1 << 12)
  59 #define VC4_DIRTY_CONSTBUF      (1 << 13)
  60 #define VC4_DIRTY_VTXSTATE      (1 << 14)
  61 #define VC4_DIRTY_VTXBUF        (1 << 15)
  62 #define VC4_DIRTY_INDEXBUF      (1 << 16)
  63 #define VC4_DIRTY_SCISSOR       (1 << 17)
  64 #define VC4_DIRTY_FLAT_SHADE_FLAGS (1 << 18)
  65 #define VC4_DIRTY_PRIM_MODE     (1 << 19)
  66 #define VC4_DIRTY_CLIP          (1 << 20)
  67 #define VC4_DIRTY_UNCOMPILED_VS (1 << 21)
  68 #define VC4_DIRTY_UNCOMPILED_FS (1 << 22)
  69 #define VC4_DIRTY_COMPILED_CS   (1 << 23)
  70 #define VC4_DIRTY_COMPILED_VS   (1 << 24)
  71 #define VC4_DIRTY_COMPILED_FS   (1 << 25)
  72 #define VC4_DIRTY_FS_INPUTS     (1 << 26)
  73
  74 struct vc4_sampler_view {
  75         struct pipe_sampler_view base;
  76         uint32_t texture_p0;
  77         uint32_t texture_p1;
  78         bool force_first_level;
  79 };
  80
  81 struct vc4_sampler_state {
  82         struct pipe_sampler_state base;
  83         uint32_t texture_p1;
  84 };
  85
  86 struct vc4_texture_stateobj {
  87         struct pipe_sampler_view *textures[PIPE_MAX_SAMPLERS];
  88         unsigned num_textures;
  89         struct pipe_sampler_state *samplers[PIPE_MAX_SAMPLERS];
  90         unsigned num_samplers;
  91 };
  92
  93 struct vc4_shader_uniform_info {
  94         enum quniform_contents *contents;
  95         uint32_t *data;
  96         uint32_t count;
  97         uint32_t num_texture_samples;
  98 };
  99
 100 struct vc4_uncompiled_shader {
 101         /** A name for this program, so you can track it in shader-db output. */
 102         uint32_t program_id;
 103         /** How many variants of this program were compiled, for shader-db. */
 104         uint32_t compiled_variant_count;
 105         struct pipe_shader_state base;
 106 };
 107
 108 struct vc4_ubo_range {
 109         /**
 110          * offset in bytes from the start of the ubo where this range is
 111          * uploaded.
 112          *
 113          * Only set once used is set.
 114          */
 115         uint32_t dst_offset;
 116
 117         /**
 118          * offset in bytes from the start of the gallium uniforms where the
 119          * data comes from.
 120          */
 121         uint32_t src_offset;
 122
 123         /** size in bytes of this ubo range */
 124         uint32_t size;
 125 };
 126
 127 struct vc4_fs_inputs {
 128         /**
 129          * Array of the meanings of the VPM inputs this shader needs.
 130          *
 131          * It doesn't include those that aren't part of the VPM, like
 132          * point/line coordinates.
 133          */
 134         struct vc4_varying_slot *input_slots;
 135         uint32_t num_inputs;
 136 };
 137
 138 struct vc4_compiled_shader {
 139         uint64_t program_id;
 140         struct vc4_bo *bo;
 141
 142         struct vc4_shader_uniform_info uniforms;
 143
 144         struct vc4_ubo_range *ubo_ranges;
 145         uint32_t num_ubo_ranges;
 146         uint32_t ubo_size;
 147         /**
 148          * VC4_DIRTY_* flags that, when set in vc4->dirty, mean that the
 149          * uniforms have to be rewritten (and therefore the shader state
 150          * reemitted).
 151          */
 152         uint32_t uniform_dirty_bits;
 153
 154         /** bitmask of which inputs are color inputs, for flat shade handling. */
 155         uint32_t color_inputs;
 156
 157         bool disable_early_z;
 158
 159         uint8_t num_inputs;
 160
 161         /* Byte offsets for the start of the vertex attributes 0-7, and the
 162          * total size as "attribute" 8.
 163          */
 164         uint8_t vattr_offsets[9];
 165         uint8_t vattrs_live;
 166
 167         const struct vc4_fs_inputs *fs_inputs;
 168 };
 169
 170 struct vc4_program_stateobj {
 171         struct vc4_uncompiled_shader *bind_vs, *bind_fs;
 172         struct vc4_compiled_shader *cs, *vs, *fs;
 173 };
 174
 175 struct vc4_constbuf_stateobj {
 176         struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
 177         uint32_t enabled_mask;
 178         uint32_t dirty_mask;
 179 };
 180
 181 struct vc4_vertexbuf_stateobj {
 182         struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
 183         unsigned count;
 184         uint32_t enabled_mask;
 185         uint32_t dirty_mask;
 186 };
 187
 188 struct vc4_vertex_stateobj {
 189         struct pipe_vertex_element pipe[PIPE_MAX_ATTRIBS];
 190         unsigned num_elements;
 191 };
 192
 193 /* Hash table key for vc4->jobs */
 194 struct vc4_job_key {
 195         struct pipe_surface *cbuf;
 196         struct pipe_surface *zsbuf;
 197 };
 198
 199 /**
 200  * A complete bin/render job.
 201  *
 202  * This is all of the state necessary to submit a bin/render to the kernel.
 203  * We want to be able to have multiple in progress at a time, so that we don't
 204  * need to flush an existing CL just to switch to rendering to a new render
 205  * target (which would mean reading back from the old render target when
 206  * starting to render to it again).
 207  */
 208 struct vc4_job {
 209         struct vc4_cl bcl;
 210         struct vc4_cl shader_rec;
 211         struct vc4_cl uniforms;
 212         struct vc4_cl bo_handles;
 213         struct vc4_cl bo_pointers;
 214         uint32_t shader_rec_count;
 215
 216         /** @{ Surfaces to submit rendering for. */
 217         struct pipe_surface *color_read;
 218         struct pipe_surface *color_write;
 219         struct pipe_surface *zs_read;
 220         struct pipe_surface *zs_write;
 221         struct pipe_surface *msaa_color_write;
 222         struct pipe_surface *msaa_zs_write;
 223         /** @} */
 224         /** @{
 225          * Bounding box of the scissor across all queued drawing.
 226          *
 227          * Note that the max values are exclusive.
 228          */
 229         uint32_t draw_min_x;
 230         uint32_t draw_min_y;
 231         uint32_t draw_max_x;
 232         uint32_t draw_max_y;
 233         /** @} */
 234         /** @{
 235          * Width/height of the color framebuffer being rendered to,
 236          * for VC4_TILE_RENDERING_MODE_CONFIG.
 237         */
 238         uint32_t draw_width;
 239         uint32_t draw_height;
 240         /** @} */
 241         /** @{ Tile information, depending on MSAA and float color buffer. */
 242         uint32_t draw_tiles_x; /** @< Number of tiles wide for framebuffer. */
 243         uint32_t draw_tiles_y; /** @< Number of tiles high for framebuffer. */
 244
 245         uint32_t tile_width; /** @< Width of a tile. */
 246         uint32_t tile_height; /** @< Height of a tile. */
 247         /** Whether the current rendering is in a 4X MSAA tile buffer. */
 248         bool msaa;
 249         /** @} */
 250
 251         /* Bitmask of PIPE_CLEAR_* of buffers that were cleared before the
 252          * first rendering.
 253          */
 254         uint32_t cleared;
 255         /* Bitmask of PIPE_CLEAR_* of buffers that have been rendered to
 256          * (either clears or draws).
 257          */
 258         uint32_t resolve;
 259         uint32_t clear_color[2];
 260         uint32_t clear_depth; /**< 24-bit unorm depth */
 261         uint8_t clear_stencil;
 262
 263         /**
 264          * Set if some drawing (triangles, blits, or just a glClear()) has
 265          * been done to the FBO, meaning that we need to
 266          * DRM_IOCTL_VC4_SUBMIT_CL.
 267          */
 268         bool needs_flush;
 269
 270         /**
 271          * Number of draw calls (not counting full buffer clears) queued in
 272          * the current job.
 273          */
 274         uint32_t draw_calls_queued;
 275
 276         struct vc4_job_key key;
 277 };
 278
 279 struct vc4_context {
 280         struct pipe_context base;
 281
 282         int fd;
 283         struct vc4_screen *screen;
 284
 285         /** The 3D rendering job for the currently bound FBO. */
 286         struct vc4_job *job;
 287
 288         /* Map from struct vc4_job_key to the job for that FBO.
 289          */
 290         struct hash_table *jobs;
 291
 292         /**
 293          * Map from vc4_resource to a job writing to that resource.
 294          *
 295          * Primarily for flushing jobs rendering to textures that are now
 296          * being read from.
 297          */
 298         struct hash_table *write_jobs;
 299
 300         struct slab_mempool transfer_pool;
 301         struct blitter_context *blitter;
 302
 303         /** bitfield of VC4_DIRTY_* */
 304         uint32_t dirty;
 305
 306         struct primconvert_context *primconvert;
 307
 308         struct hash_table *fs_cache, *vs_cache;
 309         struct set *fs_inputs_set;
 310         uint32_t next_uncompiled_program_id;
 311         uint64_t next_compiled_program_id;
 312
 313         struct ra_regs *regs;
 314         unsigned int reg_class_any;
 315         unsigned int reg_class_a_or_b_or_acc;
 316         unsigned int reg_class_r0_r3;
 317         unsigned int reg_class_r4_or_a;
 318         unsigned int reg_class_a;
 319
 320         uint8_t prim_mode;
 321
 322         /** Maximum index buffer valid for the current shader_rec. */
 323         uint32_t max_index;
 324         /** Last index bias baked into the current shader_rec. */
 325         uint32_t last_index_bias;
 326
 327         /** Seqno of the last CL flush's job. */
 328         uint64_t last_emit_seqno;
 329
 330         struct u_upload_mgr *uploader;
 331
 332         /** @{ Current pipeline state objects */
 333         struct pipe_scissor_state scissor;
 334         struct pipe_blend_state *blend;
 335         struct vc4_rasterizer_state *rasterizer;
 336         struct vc4_depth_stencil_alpha_state *zsa;
 337
 338         struct vc4_texture_stateobj verttex, fragtex;
 339
 340         struct vc4_program_stateobj prog;
 341
 342         struct vc4_vertex_stateobj *vtx;
 343
 344         struct {
 345                 struct pipe_blend_color f;
 346                 uint8_t ub[4];
 347         } blend_color;
 348         struct pipe_stencil_ref stencil_ref;
 349         unsigned sample_mask;
 350         struct pipe_framebuffer_state framebuffer;
 351         struct pipe_poly_stipple stipple;
 352         struct pipe_clip_state clip;
 353         struct pipe_viewport_state viewport;
 354         struct vc4_constbuf_stateobj constbuf[PIPE_SHADER_TYPES];
 355         struct vc4_vertexbuf_stateobj vertexbuf;
 356         struct pipe_index_buffer indexbuf;
 357         /** @} */
 358 };
 359
 360 struct vc4_rasterizer_state {
 361         struct pipe_rasterizer_state base;
 362
 363         /* VC4_CONFIGURATION_BITS */
 364         uint8_t config_bits[3];
 365
 366         float point_size;
 367
 368         /**
 369          * Half-float (1/8/7 bits) value of polygon offset units for
 370          * VC4_PACKET_DEPTH_OFFSET
 371          */
 372         uint16_t offset_units;
 373         /**
 374          * Half-float (1/8/7 bits) value of polygon offset scale for
 375          * VC4_PACKET_DEPTH_OFFSET
 376          */
 377         uint16_t offset_factor;
 378 };
 379
 380 struct vc4_depth_stencil_alpha_state {
 381         struct pipe_depth_stencil_alpha_state base;
 382
 383         /* VC4_CONFIGURATION_BITS */
 384         uint8_t config_bits[3];
 385
 386         /** Uniforms for stencil state.
 387          *
 388          * Index 0 is either the front config, or the front-and-back config.
 389          * Index 1 is the back config if doing separate back stencil.
 390          * Index 2 is the writemask config if it's not a common mask value.
 391          */
 392         uint32_t stencil_uniforms[3];
 393 };
 394
 395 #define perf_debug(...) do {                            \
 396         if (unlikely(vc4_debug & VC4_DEBUG_PERF))       \
 397                 fprintf(stderr, __VA_ARGS__);           \
 398 } while (0)
 399
 400 static inline struct vc4_context *
 401 vc4_context(struct pipe_context *pcontext)
 402 {
 403         return (struct vc4_context *)pcontext;
 404 }
 405
 406 static inline struct vc4_sampler_view *
 407 vc4_sampler_view(struct pipe_sampler_view *psview)
 408 {
 409         return (struct vc4_sampler_view *)psview;
 410 }
 411
 412 static inline struct vc4_sampler_state *
 413 vc4_sampler_state(struct pipe_sampler_state *psampler)
 414 {
 415         return (struct vc4_sampler_state *)psampler;
 416 }
 417
 418 struct pipe_context *vc4_context_create(struct pipe_screen *pscreen,
 419                                         void *priv, unsigned flags);
 420 void vc4_draw_init(struct pipe_context *pctx);
 421 void vc4_state_init(struct pipe_context *pctx);
 422 void vc4_program_init(struct pipe_context *pctx);
 423 void vc4_program_fini(struct pipe_context *pctx);
 424 void vc4_query_init(struct pipe_context *pctx);
 425 void vc4_simulator_init(struct vc4_screen *screen);
 426 int vc4_simulator_flush(struct vc4_context *vc4,
 427                         struct drm_vc4_submit_cl *args,
 428                         struct vc4_job *job);
 429
 430 void vc4_set_shader_uniform_dirty_flags(struct vc4_compiled_shader *shader);
 431 void vc4_write_uniforms(struct vc4_context *vc4,
 432                         struct vc4_compiled_shader *shader,
 433                         struct vc4_constbuf_stateobj *cb,
 434                         struct vc4_texture_stateobj *texstate);
 435
 436 void vc4_flush(struct pipe_context *pctx);
 437 void vc4_job_init(struct vc4_context *vc4);
 438 struct vc4_job *vc4_get_job(struct vc4_context *vc4,
 439                             struct pipe_surface *cbuf,
 440                             struct pipe_surface *zsbuf);
 441 struct vc4_job *vc4_get_job_for_fbo(struct vc4_context *vc4);
 442
 443 void vc4_job_submit(struct vc4_context *vc4, struct vc4_job *job);
 444 void vc4_flush_jobs_writing_resource(struct vc4_context *vc4,
 445                                      struct pipe_resource *prsc);
 446 void vc4_flush_jobs_reading_resource(struct vc4_context *vc4,
 447                                      struct pipe_resource *prsc);
 448 void vc4_emit_state(struct pipe_context *pctx);
 449 void vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c);
 450 struct qpu_reg *vc4_register_allocate(struct vc4_context *vc4, struct vc4_compile *c);
 451 void vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode);
 452
 453 bool vc4_rt_format_supported(enum pipe_format f);
 454 bool vc4_rt_format_is_565(enum pipe_format f);
 455 bool vc4_tex_format_supported(enum pipe_format f);
 456 uint8_t vc4_get_tex_format(enum pipe_format f);
 457 const uint8_t *vc4_get_format_swizzle(enum pipe_format f);
 458 void vc4_init_query_functions(struct vc4_context *vc4);
 459 void vc4_blit(struct pipe_context *pctx, const struct pipe_blit_info *blit_info);
 460 void vc4_blitter_save(struct vc4_context *vc4);
 461 #endif /* VC4_CONTEXT_H */