src/gallium/drivers/vc4/vc4_draw.c

   1 /*
   2  * Copyright (c) 2014 Scott Mansell
   3  * Copyright © 2014 Broadcom
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #include "util/u_prim.h"
  26 #include "util/u_format.h"
  27 #include "util/u_pack_color.h"
  28 #include "indices/u_primconvert.h"
  29
  30 #include "vc4_context.h"
  31 #include "vc4_resource.h"
  32
  33 static void
  34 vc4_get_draw_cl_space(struct vc4_context *vc4)
  35 {
  36         /* Binner gets our packet state -- vc4_emit.c contents,
  37          * and the primitive itself.
  38          */
  39         cl_ensure_space(&vc4->bcl, 256);
  40
  41         /* Nothing for rcl -- that's covered by vc4_context.c */
  42
  43         /* shader_rec gets up to 12 dwords of reloc handles plus a maximally
  44          * sized shader_rec (104 bytes base for 8 vattrs plus 32 bytes of
  45          * vattr stride).
  46          */
  47         cl_ensure_space(&vc4->shader_rec, 12 * sizeof(uint32_t) + 104 + 8 * 32);
  48
  49         /* Uniforms are covered by vc4_write_uniforms(). */
  50
  51         /* There could be up to 16 textures per stage, plus misc other
  52          * pointers.
  53          */
  54         cl_ensure_space(&vc4->bo_handles, (2 * 16 + 20) * sizeof(uint32_t));
  55         cl_ensure_space(&vc4->bo_pointers,
  56                         (2 * 16 + 20) * sizeof(struct vc4_bo *));
  57 }
  58
  59 /**
  60  * Does the initial bining command list setup for drawing to a given FBO.
  61  */
  62 static void
  63 vc4_start_draw(struct vc4_context *vc4)
  64 {
  65         if (vc4->needs_flush)
  66                 return;
  67
  68         vc4_get_draw_cl_space(vc4);
  69
  70         uint32_t width = vc4->framebuffer.width;
  71         uint32_t height = vc4->framebuffer.height;
  72         uint32_t tilew = align(width, 64) / 64;
  73         uint32_t tileh = align(height, 64) / 64;
  74
  75         /* Tile alloc memory setup: We use an initial alloc size of 32b.  The
  76          * hardware then aligns that to 256b (we use 4096, because all of our
  77          * BO allocations align to that anyway), then for some reason the
  78          * simulator wants an extra page available, even if you have overflow
  79          * memory set up.
  80          *
  81          * XXX: The binner only does 28-bit addressing math, so the tile alloc
  82          * and tile state should be in the same BO and that BO needs to not
  83          * cross a 256MB boundary, somehow.
  84          */
  85         uint32_t tile_alloc_size = 32 * tilew * tileh;
  86         tile_alloc_size = align(tile_alloc_size, 4096);
  87         tile_alloc_size += 4096;
  88         uint32_t tile_state_size = 48 * tilew * tileh;
  89         if (!vc4->tile_alloc || vc4->tile_alloc->size < tile_alloc_size) {
  90                 vc4_bo_unreference(&vc4->tile_alloc);
  91                 vc4->tile_alloc = vc4_bo_alloc(vc4->screen, tile_alloc_size,
  92                                                "tile_alloc");
  93         }
  94         if (!vc4->tile_state || vc4->tile_state->size < tile_state_size) {
  95                 vc4_bo_unreference(&vc4->tile_state);
  96                 vc4->tile_state = vc4_bo_alloc(vc4->screen, tile_state_size,
  97                                                "tile_state");
  98         }
  99
 100         //   Tile state data is 48 bytes per tile, I think it can be thrown away
 101         //   as soon as binning is finished.
 102         cl_start_reloc(&vc4->bcl, 2);
 103         cl_u8(&vc4->bcl, VC4_PACKET_TILE_BINNING_MODE_CONFIG);
 104         cl_reloc(vc4, &vc4->bcl, vc4->tile_alloc, 0);
 105         cl_u32(&vc4->bcl, vc4->tile_alloc->size);
 106         cl_reloc(vc4, &vc4->bcl, vc4->tile_state, 0);
 107         cl_u8(&vc4->bcl, tilew);
 108         cl_u8(&vc4->bcl, tileh);
 109         cl_u8(&vc4->bcl,
 110               VC4_BIN_CONFIG_AUTO_INIT_TSDA |
 111               VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_32 |
 112               VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_32);
 113
 114         /* START_TILE_BINNING resets the statechange counters in the hardware,
 115          * which are what is used when a primitive is binned to a tile to
 116          * figure out what new state packets need to be written to that tile's
 117          * command list.
 118          */
 119         cl_u8(&vc4->bcl, VC4_PACKET_START_TILE_BINNING);
 120
 121         /* Reset the current compressed primitives format.  This gets modified
 122          * by VC4_PACKET_GL_INDEXED_PRIMITIVE and
 123          * VC4_PACKET_GL_ARRAY_PRIMITIVE, so it needs to be reset at the start
 124          * of every tile.
 125          */
 126         cl_u8(&vc4->bcl, VC4_PACKET_PRIMITIVE_LIST_FORMAT);
 127         cl_u8(&vc4->bcl, (VC4_PRIMITIVE_LIST_FORMAT_16_INDEX |
 128                           VC4_PRIMITIVE_LIST_FORMAT_TYPE_TRIANGLES));
 129
 130         vc4->needs_flush = true;
 131         vc4->draw_call_queued = true;
 132 }
 133
 134 static void
 135 vc4_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
 136 {
 137         struct vc4_context *vc4 = vc4_context(pctx);
 138
 139         if (info->mode >= PIPE_PRIM_QUADS) {
 140                 util_primconvert_save_index_buffer(vc4->primconvert, &vc4->indexbuf);
 141                 util_primconvert_save_rasterizer_state(vc4->primconvert, &vc4->rasterizer->base);
 142                 util_primconvert_draw_vbo(vc4->primconvert, info);
 143                 perf_debug("Fallback conversion for %d %s vertices\n",
 144                            info->count, u_prim_name(info->mode));
 145                 return;
 146         }
 147
 148         vc4_get_draw_cl_space(vc4);
 149
 150         struct vc4_vertex_stateobj *vtx = vc4->vtx;
 151         struct vc4_vertexbuf_stateobj *vertexbuf = &vc4->vertexbuf;
 152
 153         if (vc4->prim_mode != info->mode) {
 154                 vc4->prim_mode = info->mode;
 155                 vc4->dirty |= VC4_DIRTY_PRIM_MODE;
 156         }
 157
 158         vc4_start_draw(vc4);
 159         vc4_update_compiled_shaders(vc4, info->mode);
 160
 161         vc4_emit_state(pctx);
 162         vc4->dirty = 0;
 163
 164         vc4_write_uniforms(vc4, vc4->prog.fs,
 165                            &vc4->constbuf[PIPE_SHADER_FRAGMENT],
 166                            &vc4->fragtex);
 167         vc4_write_uniforms(vc4, vc4->prog.vs,
 168                            &vc4->constbuf[PIPE_SHADER_VERTEX],
 169                            &vc4->verttex);
 170         vc4_write_uniforms(vc4, vc4->prog.cs,
 171                            &vc4->constbuf[PIPE_SHADER_VERTEX],
 172                            &vc4->verttex);
 173
 174         /* The simulator throws a fit if VS or CS don't read an attribute, so
 175          * we emit a dummy read.
 176          */
 177         uint32_t num_elements_emit = MAX2(vtx->num_elements, 1);
 178         /* Emit the shader record. */
 179         cl_start_shader_reloc(&vc4->shader_rec, 3 + num_elements_emit);
 180         cl_u16(&vc4->shader_rec,
 181                VC4_SHADER_FLAG_ENABLE_CLIPPING |
 182                ((info->mode == PIPE_PRIM_POINTS &&
 183                  vc4->rasterizer->base.point_size_per_vertex) ?
 184                 VC4_SHADER_FLAG_VS_POINT_SIZE : 0));
 185         cl_u8(&vc4->shader_rec, 0); /* fs num uniforms (unused) */
 186         cl_u8(&vc4->shader_rec, vc4->prog.fs->num_inputs);
 187         cl_reloc(vc4, &vc4->shader_rec, vc4->prog.fs->bo, 0);
 188         cl_u32(&vc4->shader_rec, 0); /* UBO offset written by kernel */
 189
 190         cl_u16(&vc4->shader_rec, 0); /* vs num uniforms */
 191         cl_u8(&vc4->shader_rec, vc4->prog.vs->vattrs_live);
 192         cl_u8(&vc4->shader_rec, vc4->prog.vs->vattr_offsets[8]);
 193         cl_reloc(vc4, &vc4->shader_rec, vc4->prog.vs->bo, 0);
 194         cl_u32(&vc4->shader_rec, 0); /* UBO offset written by kernel */
 195
 196         cl_u16(&vc4->shader_rec, 0); /* cs num uniforms */
 197         cl_u8(&vc4->shader_rec, vc4->prog.cs->vattrs_live);
 198         cl_u8(&vc4->shader_rec, vc4->prog.cs->vattr_offsets[8]);
 199         cl_reloc(vc4, &vc4->shader_rec, vc4->prog.cs->bo, 0);
 200         cl_u32(&vc4->shader_rec, 0); /* UBO offset written by kernel */
 201
 202         uint32_t max_index = 0xffff;
 203         uint32_t vpm_offset = 0;
 204         for (int i = 0; i < vtx->num_elements; i++) {
 205                 struct pipe_vertex_element *elem = &vtx->pipe[i];
 206                 struct pipe_vertex_buffer *vb =
 207                         &vertexbuf->vb[elem->vertex_buffer_index];
 208                 struct vc4_resource *rsc = vc4_resource(vb->buffer);
 209                 uint32_t offset = vb->buffer_offset + elem->src_offset;
 210                 uint32_t vb_size = rsc->bo->size - offset;
 211                 uint32_t elem_size =
 212                         util_format_get_blocksize(elem->src_format);
 213
 214                 cl_reloc(vc4, &vc4->shader_rec, rsc->bo, offset);
 215                 cl_u8(&vc4->shader_rec, elem_size - 1);
 216                 cl_u8(&vc4->shader_rec, vb->stride);
 217                 cl_u8(&vc4->shader_rec, vc4->prog.vs->vattr_offsets[i]);
 218                 cl_u8(&vc4->shader_rec, vc4->prog.cs->vattr_offsets[i]);
 219
 220                 vpm_offset += align(elem_size, 4);
 221
 222                 if (vb->stride > 0) {
 223                         max_index = MIN2(max_index,
 224                                          (vb_size - elem_size) / vb->stride);
 225                 }
 226         }
 227
 228         if (vtx->num_elements == 0) {
 229                 assert(num_elements_emit == 1);
 230                 struct vc4_bo *bo = vc4_bo_alloc(vc4->screen, 4096, "scratch VBO");
 231                 cl_reloc(vc4, &vc4->shader_rec, bo, 0);
 232                 cl_u8(&vc4->shader_rec, 16 - 1); /* element size */
 233                 cl_u8(&vc4->shader_rec, 0); /* stride */
 234                 cl_u8(&vc4->shader_rec, 0); /* VS VPM offset */
 235                 cl_u8(&vc4->shader_rec, 0); /* CS VPM offset */
 236                 vc4_bo_unreference(&bo);
 237         }
 238
 239         /* the actual draw call. */
 240         cl_u8(&vc4->bcl, VC4_PACKET_GL_SHADER_STATE);
 241         assert(vtx->num_elements <= 8);
 242         /* Note that number of attributes == 0 in the packet means 8
 243          * attributes.  This field also contains the offset into shader_rec.
 244          */
 245         cl_u32(&vc4->bcl, num_elements_emit & 0x7);
 246
 247         /* Note that the primitive type fields match with OpenGL/gallium
 248          * definitions, up to but not including QUADS.
 249          */
 250         if (info->indexed) {
 251                 struct vc4_resource *rsc = vc4_resource(vc4->indexbuf.buffer);
 252                 uint32_t offset = vc4->indexbuf.offset;
 253                 uint32_t index_size = vc4->indexbuf.index_size;
 254                 if (rsc->shadow_parent) {
 255                         vc4_update_shadow_index_buffer(pctx, &vc4->indexbuf);
 256                         offset = 0;
 257                 }
 258
 259                 cl_start_reloc(&vc4->bcl, 1);
 260                 cl_u8(&vc4->bcl, VC4_PACKET_GL_INDEXED_PRIMITIVE);
 261                 cl_u8(&vc4->bcl,
 262                       info->mode |
 263                       (index_size == 2 ?
 264                        VC4_INDEX_BUFFER_U16:
 265                        VC4_INDEX_BUFFER_U8));
 266                 cl_u32(&vc4->bcl, info->count);
 267                 cl_reloc(vc4, &vc4->bcl, rsc->bo, offset);
 268                 cl_u32(&vc4->bcl, max_index);
 269         } else {
 270                 cl_u8(&vc4->bcl, VC4_PACKET_GL_ARRAY_PRIMITIVE);
 271                 cl_u8(&vc4->bcl, info->mode);
 272                 cl_u32(&vc4->bcl, info->count);
 273                 cl_u32(&vc4->bcl, info->start);
 274         }
 275
 276         if (vc4->zsa && vc4->zsa->base.depth.enabled) {
 277                 vc4->resolve |= PIPE_CLEAR_DEPTH;
 278         }
 279         if (vc4->zsa && vc4->zsa->base.stencil[0].enabled)
 280                 vc4->resolve |= PIPE_CLEAR_STENCIL;
 281         vc4->resolve |= PIPE_CLEAR_COLOR0;
 282
 283         vc4->shader_rec_count++;
 284
 285         if (vc4_debug & VC4_DEBUG_ALWAYS_FLUSH)
 286                 vc4_flush(pctx);
 287 }
 288
 289 static uint32_t
 290 pack_rgba(enum pipe_format format, const float *rgba)
 291 {
 292         union util_color uc;
 293         util_pack_color(rgba, format, &uc);
 294         if (util_format_get_blocksize(format) == 2)
 295                 return uc.us;
 296         else
 297                 return uc.ui[0];
 298 }
 299
 300 static void
 301 vc4_clear(struct pipe_context *pctx, unsigned buffers,
 302           const union pipe_color_union *color, double depth, unsigned stencil)
 303 {
 304         struct vc4_context *vc4 = vc4_context(pctx);
 305
 306         /* We can't flag new buffers for clearing once we've queued draws.  We
 307          * could avoid this by using the 3d engine to clear.
 308          */
 309         if (vc4->draw_call_queued) {
 310                 perf_debug("Flushing rendering to process new clear.");
 311                 vc4_flush(pctx);
 312         }
 313
 314         if (buffers & PIPE_CLEAR_COLOR0) {
 315                 vc4->clear_color[0] = vc4->clear_color[1] =
 316                         pack_rgba(vc4->framebuffer.cbufs[0]->format,
 317                                   color->f);
 318         }
 319
 320         if (buffers & PIPE_CLEAR_DEPTH) {
 321                 /* Though the depth buffer is stored with Z in the high 24,
 322                  * for this field we just need to store it in the low 24.
 323                  */
 324                 vc4->clear_depth = util_pack_z(PIPE_FORMAT_Z24X8_UNORM, depth);
 325         }
 326
 327         if (buffers & PIPE_CLEAR_STENCIL)
 328                 vc4->clear_stencil = stencil;
 329
 330         vc4->draw_min_x = 0;
 331         vc4->draw_min_y = 0;
 332         vc4->draw_max_x = vc4->framebuffer.width;
 333         vc4->draw_max_y = vc4->framebuffer.height;
 334         vc4->cleared |= buffers;
 335         vc4->resolve |= buffers;
 336
 337         vc4_start_draw(vc4);
 338 }
 339
 340 static void
 341 vc4_clear_render_target(struct pipe_context *pctx, struct pipe_surface *ps,
 342                         const union pipe_color_union *color,
 343                         unsigned x, unsigned y, unsigned w, unsigned h)
 344 {
 345         fprintf(stderr, "unimpl: clear RT\n");
 346 }
 347
 348 static void
 349 vc4_clear_depth_stencil(struct pipe_context *pctx, struct pipe_surface *ps,
 350                         unsigned buffers, double depth, unsigned stencil,
 351                         unsigned x, unsigned y, unsigned w, unsigned h)
 352 {
 353         fprintf(stderr, "unimpl: clear DS\n");
 354 }
 355
 356 void
 357 vc4_draw_init(struct pipe_context *pctx)
 358 {
 359         pctx->draw_vbo = vc4_draw_vbo;
 360         pctx->clear = vc4_clear;
 361         pctx->clear_render_target = vc4_clear_render_target;
 362         pctx->clear_depth_stencil = vc4_clear_depth_stencil;
 363 }