src/gallium/drivers/vc4/vc4_draw.c

   1 /*
   2  * Copyright (c) 2014 Scott Mansell
   3  * Copyright © 2014 Broadcom
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #include "util/u_prim.h"
  26 #include "util/u_format.h"
  27 #include "util/u_pack_color.h"
  28 #include "indices/u_primconvert.h"
  29
  30 #include "vc4_context.h"
  31 #include "vc4_resource.h"
  32
  33 static void
  34 vc4_get_draw_cl_space(struct vc4_context *vc4)
  35 {
  36         /* Binner gets our packet state -- vc4_emit.c contents,
  37          * and the primitive itself.
  38          */
  39         cl_ensure_space(&vc4->bcl, 256);
  40
  41         /* Nothing for rcl -- that's covered by vc4_context.c */
  42
  43         /* shader_rec gets up to 12 dwords of reloc handles plus a maximally
  44          * sized shader_rec (104 bytes base for 8 vattrs plus 32 bytes of
  45          * vattr stride).
  46          */
  47         cl_ensure_space(&vc4->shader_rec, 12 * sizeof(uint32_t) + 104 + 8 * 32);
  48
  49         /* Uniforms are covered by vc4_write_uniforms(). */
  50
  51         /* There could be up to 16 textures per stage, plus misc other
  52          * pointers.
  53          */
  54         cl_ensure_space(&vc4->bo_handles, (2 * 16 + 20) * sizeof(uint32_t));
  55         cl_ensure_space(&vc4->bo_pointers,
  56                         (2 * 16 + 20) * sizeof(struct vc4_bo *));
  57 }
  58
  59 /**
  60  * Does the initial bining command list setup for drawing to a given FBO.
  61  */
  62 static void
  63 vc4_start_draw(struct vc4_context *vc4)
  64 {
  65         if (vc4->needs_flush)
  66                 return;
  67
  68         vc4_get_draw_cl_space(vc4);
  69
  70         uint32_t width = vc4->framebuffer.width;
  71         uint32_t height = vc4->framebuffer.height;
  72         uint32_t tilew = align(width, 64) / 64;
  73         uint32_t tileh = align(height, 64) / 64;
  74         struct vc4_cl_out *bcl = cl_start(&vc4->bcl);
  75
  76         //   Tile state data is 48 bytes per tile, I think it can be thrown away
  77         //   as soon as binning is finished.
  78         cl_u8(&bcl, VC4_PACKET_TILE_BINNING_MODE_CONFIG);
  79         cl_u32(&bcl, 0); /* tile alloc addr, filled by kernel */
  80         cl_u32(&bcl, 0); /* tile alloc size, filled by kernel */
  81         cl_u32(&bcl, 0); /* tile state addr, filled by kernel */
  82         cl_u8(&bcl, tilew);
  83         cl_u8(&bcl, tileh);
  84         cl_u8(&bcl, 0); /* flags, filled by kernel. */
  85
  86         /* START_TILE_BINNING resets the statechange counters in the hardware,
  87          * which are what is used when a primitive is binned to a tile to
  88          * figure out what new state packets need to be written to that tile's
  89          * command list.
  90          */
  91         cl_u8(&bcl, VC4_PACKET_START_TILE_BINNING);
  92
  93         /* Reset the current compressed primitives format.  This gets modified
  94          * by VC4_PACKET_GL_INDEXED_PRIMITIVE and
  95          * VC4_PACKET_GL_ARRAY_PRIMITIVE, so it needs to be reset at the start
  96          * of every tile.
  97          */
  98         cl_u8(&bcl, VC4_PACKET_PRIMITIVE_LIST_FORMAT);
  99         cl_u8(&bcl, (VC4_PRIMITIVE_LIST_FORMAT_16_INDEX |
 100                      VC4_PRIMITIVE_LIST_FORMAT_TYPE_TRIANGLES));
 101
 102         vc4->needs_flush = true;
 103         vc4->draw_call_queued = true;
 104         vc4->draw_width = width;
 105         vc4->draw_height = height;
 106
 107         cl_end(&vc4->bcl, bcl);
 108 }
 109
 110 static void
 111 vc4_update_shadow_textures(struct pipe_context *pctx,
 112                            struct vc4_texture_stateobj *stage_tex)
 113 {
 114         for (int i = 0; i < stage_tex->num_textures; i++) {
 115                 struct pipe_sampler_view *view = stage_tex->textures[i];
 116                 if (!view)
 117                         continue;
 118                 struct vc4_resource *rsc = vc4_resource(view->texture);
 119                 if (rsc->shadow_parent)
 120                         vc4_update_shadow_baselevel_texture(pctx, view);
 121         }
 122 }
 123
 124 static void
 125 vc4_emit_gl_shader_state(struct vc4_context *vc4, const struct pipe_draw_info *info)
 126 {
 127         /* VC4_DIRTY_VTXSTATE */
 128         struct vc4_vertex_stateobj *vtx = vc4->vtx;
 129         /* VC4_DIRTY_VTXBUF */
 130         struct vc4_vertexbuf_stateobj *vertexbuf = &vc4->vertexbuf;
 131
 132         /* The simulator throws a fit if VS or CS don't read an attribute, so
 133          * we emit a dummy read.
 134          */
 135         uint32_t num_elements_emit = MAX2(vtx->num_elements, 1);
 136         /* Emit the shader record. */
 137         struct vc4_cl_out *shader_rec =
 138                 cl_start_shader_reloc(&vc4->shader_rec, 3 + num_elements_emit);
 139         /* VC4_DIRTY_PRIM_MODE | VC4_DIRTY_RASTERIZER */
 140         cl_u16(&shader_rec,
 141                VC4_SHADER_FLAG_ENABLE_CLIPPING |
 142                VC4_SHADER_FLAG_FS_SINGLE_THREAD |
 143                ((info->mode == PIPE_PRIM_POINTS &&
 144                  vc4->rasterizer->base.point_size_per_vertex) ?
 145                 VC4_SHADER_FLAG_VS_POINT_SIZE : 0));
 146
 147         /* VC4_DIRTY_COMPILED_FS */
 148         cl_u8(&shader_rec, 0); /* fs num uniforms (unused) */
 149         cl_u8(&shader_rec, vc4->prog.fs->num_inputs);
 150         cl_reloc(vc4, &vc4->shader_rec, &shader_rec, vc4->prog.fs->bo, 0);
 151         cl_u32(&shader_rec, 0); /* UBO offset written by kernel */
 152
 153         /* VC4_DIRTY_COMPILED_VS */
 154         cl_u16(&shader_rec, 0); /* vs num uniforms */
 155         cl_u8(&shader_rec, vc4->prog.vs->vattrs_live);
 156         cl_u8(&shader_rec, vc4->prog.vs->vattr_offsets[8]);
 157         cl_reloc(vc4, &vc4->shader_rec, &shader_rec, vc4->prog.vs->bo, 0);
 158         cl_u32(&shader_rec, 0); /* UBO offset written by kernel */
 159
 160         /* VC4_DIRTY_COMPILED_CS */
 161         cl_u16(&shader_rec, 0); /* cs num uniforms */
 162         cl_u8(&shader_rec, vc4->prog.cs->vattrs_live);
 163         cl_u8(&shader_rec, vc4->prog.cs->vattr_offsets[8]);
 164         cl_reloc(vc4, &vc4->shader_rec, &shader_rec, vc4->prog.cs->bo, 0);
 165         cl_u32(&shader_rec, 0); /* UBO offset written by kernel */
 166
 167         uint32_t max_index = 0xffff;
 168         for (int i = 0; i < vtx->num_elements; i++) {
 169                 struct pipe_vertex_element *elem = &vtx->pipe[i];
 170                 struct pipe_vertex_buffer *vb =
 171                         &vertexbuf->vb[elem->vertex_buffer_index];
 172                 struct vc4_resource *rsc = vc4_resource(vb->buffer);
 173                 /* not vc4->dirty tracked: vc4->last_index_bias */
 174                 uint32_t offset = (vb->buffer_offset +
 175                                    elem->src_offset +
 176                                    vb->stride * info->index_bias);
 177                 uint32_t vb_size = rsc->bo->size - offset;
 178                 uint32_t elem_size =
 179                         util_format_get_blocksize(elem->src_format);
 180
 181                 cl_reloc(vc4, &vc4->shader_rec, &shader_rec, rsc->bo, offset);
 182                 cl_u8(&shader_rec, elem_size - 1);
 183                 cl_u8(&shader_rec, vb->stride);
 184                 cl_u8(&shader_rec, vc4->prog.vs->vattr_offsets[i]);
 185                 cl_u8(&shader_rec, vc4->prog.cs->vattr_offsets[i]);
 186
 187                 if (vb->stride > 0) {
 188                         max_index = MIN2(max_index,
 189                                          (vb_size - elem_size) / vb->stride);
 190                 }
 191         }
 192
 193         if (vtx->num_elements == 0) {
 194                 assert(num_elements_emit == 1);
 195                 struct vc4_bo *bo = vc4_bo_alloc(vc4->screen, 4096, "scratch VBO");
 196                 cl_reloc(vc4, &vc4->shader_rec, &shader_rec, bo, 0);
 197                 cl_u8(&shader_rec, 16 - 1); /* element size */
 198                 cl_u8(&shader_rec, 0); /* stride */
 199                 cl_u8(&shader_rec, 0); /* VS VPM offset */
 200                 cl_u8(&shader_rec, 0); /* CS VPM offset */
 201                 vc4_bo_unreference(&bo);
 202         }
 203         cl_end(&vc4->shader_rec, shader_rec);
 204
 205         struct vc4_cl_out *bcl = cl_start(&vc4->bcl);
 206         /* the actual draw call. */
 207         cl_u8(&bcl, VC4_PACKET_GL_SHADER_STATE);
 208         assert(vtx->num_elements <= 8);
 209         /* Note that number of attributes == 0 in the packet means 8
 210          * attributes.  This field also contains the offset into shader_rec.
 211          */
 212         cl_u32(&bcl, num_elements_emit & 0x7);
 213         cl_end(&vc4->bcl, bcl);
 214
 215         vc4_write_uniforms(vc4, vc4->prog.fs,
 216                            &vc4->constbuf[PIPE_SHADER_FRAGMENT],
 217                            &vc4->fragtex);
 218         vc4_write_uniforms(vc4, vc4->prog.vs,
 219                            &vc4->constbuf[PIPE_SHADER_VERTEX],
 220                            &vc4->verttex);
 221         vc4_write_uniforms(vc4, vc4->prog.cs,
 222                            &vc4->constbuf[PIPE_SHADER_VERTEX],
 223                            &vc4->verttex);
 224
 225         vc4->last_index_bias = info->index_bias;
 226         vc4->max_index = max_index;
 227 }
 228
 229 static void
 230 vc4_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
 231 {
 232         struct vc4_context *vc4 = vc4_context(pctx);
 233
 234         if (info->mode >= PIPE_PRIM_QUADS) {
 235                 util_primconvert_save_index_buffer(vc4->primconvert, &vc4->indexbuf);
 236                 util_primconvert_save_rasterizer_state(vc4->primconvert, &vc4->rasterizer->base);
 237                 util_primconvert_draw_vbo(vc4->primconvert, info);
 238                 perf_debug("Fallback conversion for %d %s vertices\n",
 239                            info->count, u_prim_name(info->mode));
 240                 return;
 241         }
 242
 243         /* Before setting up the draw, do any fixup blits necessary. */
 244         vc4_update_shadow_textures(pctx, &vc4->verttex);
 245         vc4_update_shadow_textures(pctx, &vc4->fragtex);
 246
 247         vc4_get_draw_cl_space(vc4);
 248
 249         if (vc4->prim_mode != info->mode) {
 250                 vc4->prim_mode = info->mode;
 251                 vc4->dirty |= VC4_DIRTY_PRIM_MODE;
 252         }
 253
 254         vc4_start_draw(vc4);
 255         vc4_update_compiled_shaders(vc4, info->mode);
 256
 257         vc4_emit_state(pctx);
 258
 259         if ((vc4->dirty & (VC4_DIRTY_VTXBUF |
 260                            VC4_DIRTY_VTXSTATE |
 261                            VC4_DIRTY_PRIM_MODE |
 262                            VC4_DIRTY_RASTERIZER |
 263                            VC4_DIRTY_COMPILED_CS |
 264                            VC4_DIRTY_COMPILED_VS |
 265                            VC4_DIRTY_COMPILED_FS |
 266                            vc4->prog.cs->uniform_dirty_bits |
 267                            vc4->prog.vs->uniform_dirty_bits |
 268                            vc4->prog.fs->uniform_dirty_bits)) ||
 269             vc4->last_index_bias != info->index_bias) {
 270                 vc4_emit_gl_shader_state(vc4, info);
 271         }
 272
 273         vc4->dirty = 0;
 274
 275         /* Note that the primitive type fields match with OpenGL/gallium
 276          * definitions, up to but not including QUADS.
 277          */
 278         struct vc4_cl_out *bcl = cl_start(&vc4->bcl);
 279         if (info->indexed) {
 280                 uint32_t offset = vc4->indexbuf.offset;
 281                 uint32_t index_size = vc4->indexbuf.index_size;
 282                 struct pipe_resource *prsc;
 283                 if (vc4->indexbuf.index_size == 4) {
 284                         prsc = vc4_get_shadow_index_buffer(pctx, &vc4->indexbuf,
 285                                                            info->count, &offset);
 286                         index_size = 2;
 287                 } else {
 288                         prsc = vc4->indexbuf.buffer;
 289                 }
 290                 struct vc4_resource *rsc = vc4_resource(prsc);
 291
 292                 cl_start_reloc(&vc4->bcl, &bcl, 1);
 293                 cl_u8(&bcl, VC4_PACKET_GL_INDEXED_PRIMITIVE);
 294                 cl_u8(&bcl,
 295                       info->mode |
 296                       (index_size == 2 ?
 297                        VC4_INDEX_BUFFER_U16:
 298                        VC4_INDEX_BUFFER_U8));
 299                 cl_u32(&bcl, info->count);
 300                 cl_reloc(vc4, &vc4->bcl, &bcl, rsc->bo, offset);
 301                 cl_u32(&bcl, vc4->max_index);
 302
 303                 if (vc4->indexbuf.index_size == 4)
 304                         pipe_resource_reference(&prsc, NULL);
 305         } else {
 306                 cl_u8(&bcl, VC4_PACKET_GL_ARRAY_PRIMITIVE);
 307                 cl_u8(&bcl, info->mode);
 308                 cl_u32(&bcl, info->count);
 309                 cl_u32(&bcl, info->start);
 310         }
 311         cl_end(&vc4->bcl, bcl);
 312
 313         if (vc4->zsa && vc4->zsa->base.depth.enabled) {
 314                 vc4->resolve |= PIPE_CLEAR_DEPTH;
 315         }
 316         if (vc4->zsa && vc4->zsa->base.stencil[0].enabled)
 317                 vc4->resolve |= PIPE_CLEAR_STENCIL;
 318         vc4->resolve |= PIPE_CLEAR_COLOR0;
 319
 320         vc4->shader_rec_count++;
 321
 322         if (vc4_debug & VC4_DEBUG_ALWAYS_FLUSH)
 323                 vc4_flush(pctx);
 324 }
 325
 326 static uint32_t
 327 pack_rgba(enum pipe_format format, const float *rgba)
 328 {
 329         union util_color uc;
 330         util_pack_color(rgba, format, &uc);
 331         if (util_format_get_blocksize(format) == 2)
 332                 return uc.us;
 333         else
 334                 return uc.ui[0];
 335 }
 336
 337 static void
 338 vc4_clear(struct pipe_context *pctx, unsigned buffers,
 339           const union pipe_color_union *color, double depth, unsigned stencil)
 340 {
 341         struct vc4_context *vc4 = vc4_context(pctx);
 342
 343         /* We can't flag new buffers for clearing once we've queued draws.  We
 344          * could avoid this by using the 3d engine to clear.
 345          */
 346         if (vc4->draw_call_queued) {
 347                 perf_debug("Flushing rendering to process new clear.");
 348                 vc4_flush(pctx);
 349         }
 350
 351         if (buffers & PIPE_CLEAR_COLOR0) {
 352                 vc4->clear_color[0] = vc4->clear_color[1] =
 353                         pack_rgba(vc4->framebuffer.cbufs[0]->format,
 354                                   color->f);
 355         }
 356
 357         if (buffers & PIPE_CLEAR_DEPTH) {
 358                 /* Though the depth buffer is stored with Z in the high 24,
 359                  * for this field we just need to store it in the low 24.
 360                  */
 361                 vc4->clear_depth = util_pack_z(PIPE_FORMAT_Z24X8_UNORM, depth);
 362         }
 363
 364         if (buffers & PIPE_CLEAR_STENCIL)
 365                 vc4->clear_stencil = stencil;
 366
 367         vc4->draw_min_x = 0;
 368         vc4->draw_min_y = 0;
 369         vc4->draw_max_x = vc4->framebuffer.width;
 370         vc4->draw_max_y = vc4->framebuffer.height;
 371         vc4->cleared |= buffers;
 372         vc4->resolve |= buffers;
 373
 374         vc4_start_draw(vc4);
 375 }
 376
 377 static void
 378 vc4_clear_render_target(struct pipe_context *pctx, struct pipe_surface *ps,
 379                         const union pipe_color_union *color,
 380                         unsigned x, unsigned y, unsigned w, unsigned h)
 381 {
 382         fprintf(stderr, "unimpl: clear RT\n");
 383 }
 384
 385 static void
 386 vc4_clear_depth_stencil(struct pipe_context *pctx, struct pipe_surface *ps,
 387                         unsigned buffers, double depth, unsigned stencil,
 388                         unsigned x, unsigned y, unsigned w, unsigned h)
 389 {
 390         fprintf(stderr, "unimpl: clear DS\n");
 391 }
 392
 393 void
 394 vc4_draw_init(struct pipe_context *pctx)
 395 {
 396         pctx->draw_vbo = vc4_draw_vbo;
 397         pctx->clear = vc4_clear;
 398         pctx->clear_render_target = vc4_clear_render_target;
 399         pctx->clear_depth_stencil = vc4_clear_depth_stencil;
 400 }