2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "util/u_prim.h"
26 #include "util/u_format.h"
27 #include "util/u_pack_color.h"
28 #include "util/u_upload_mgr.h"
29 #include "indices/u_primconvert.h"
31 #include "vc4_context.h"
32 #include "vc4_resource.h"
35 vc4_get_draw_cl_space(struct vc4_context
*vc4
, int vert_count
)
37 /* The SW-5891 workaround may cause us to emit multiple shader recs
40 int num_draws
= DIV_ROUND_UP(vert_count
, 65535) + 1;
42 /* Binner gets our packet state -- vc4_emit.c contents,
43 * and the primitive itself.
45 cl_ensure_space(&vc4
->bcl
,
46 256 + (VC4_PACKET_GL_ARRAY_PRIMITIVE_SIZE
+
47 VC4_PACKET_GL_SHADER_STATE_SIZE
) * num_draws
);
49 /* Nothing for rcl -- that's covered by vc4_context.c */
51 /* shader_rec gets up to 12 dwords of reloc handles plus a maximally
52 * sized shader_rec (104 bytes base for 8 vattrs plus 32 bytes of
55 cl_ensure_space(&vc4
->shader_rec
,
56 (12 * sizeof(uint32_t) + 104 + 8 * 32) * num_draws
);
58 /* Uniforms are covered by vc4_write_uniforms(). */
60 /* There could be up to 16 textures per stage, plus misc other
63 cl_ensure_space(&vc4
->bo_handles
, (2 * 16 + 20) * sizeof(uint32_t));
64 cl_ensure_space(&vc4
->bo_pointers
,
65 (2 * 16 + 20) * sizeof(struct vc4_bo
*));
69 * Does the initial bining command list setup for drawing to a given FBO.
72 vc4_start_draw(struct vc4_context
*vc4
, int vert_count
)
77 vc4_get_draw_cl_space(vc4
, 0);
79 struct vc4_cl_out
*bcl
= cl_start(&vc4
->bcl
);
80 // Tile state data is 48 bytes per tile, I think it can be thrown away
81 // as soon as binning is finished.
82 cl_u8(&bcl
, VC4_PACKET_TILE_BINNING_MODE_CONFIG
);
83 cl_u32(&bcl
, 0); /* tile alloc addr, filled by kernel */
84 cl_u32(&bcl
, 0); /* tile alloc size, filled by kernel */
85 cl_u32(&bcl
, 0); /* tile state addr, filled by kernel */
86 cl_u8(&bcl
, vc4
->draw_tiles_x
);
87 cl_u8(&bcl
, vc4
->draw_tiles_y
);
88 /* Other flags are filled by kernel. */
89 cl_u8(&bcl
, vc4
->msaa
? VC4_BIN_CONFIG_MS_MODE_4X
: 0);
91 /* START_TILE_BINNING resets the statechange counters in the hardware,
92 * which are what is used when a primitive is binned to a tile to
93 * figure out what new state packets need to be written to that tile's
96 cl_u8(&bcl
, VC4_PACKET_START_TILE_BINNING
);
98 /* Reset the current compressed primitives format. This gets modified
99 * by VC4_PACKET_GL_INDEXED_PRIMITIVE and
100 * VC4_PACKET_GL_ARRAY_PRIMITIVE, so it needs to be reset at the start
103 cl_u8(&bcl
, VC4_PACKET_PRIMITIVE_LIST_FORMAT
);
104 cl_u8(&bcl
, (VC4_PRIMITIVE_LIST_FORMAT_16_INDEX
|
105 VC4_PRIMITIVE_LIST_FORMAT_TYPE_TRIANGLES
));
107 vc4
->needs_flush
= true;
108 vc4
->draw_calls_queued
++;
109 vc4
->draw_width
= vc4
->framebuffer
.width
;
110 vc4
->draw_height
= vc4
->framebuffer
.height
;
112 cl_end(&vc4
->bcl
, bcl
);
116 vc4_update_shadow_textures(struct pipe_context
*pctx
,
117 struct vc4_texture_stateobj
*stage_tex
)
119 for (int i
= 0; i
< stage_tex
->num_textures
; i
++) {
120 struct pipe_sampler_view
*view
= stage_tex
->textures
[i
];
123 struct vc4_resource
*rsc
= vc4_resource(view
->texture
);
124 if (rsc
->shadow_parent
)
125 vc4_update_shadow_baselevel_texture(pctx
, view
);
130 vc4_emit_gl_shader_state(struct vc4_context
*vc4
, const struct pipe_draw_info
*info
,
131 uint32_t extra_index_bias
)
133 /* VC4_DIRTY_VTXSTATE */
134 struct vc4_vertex_stateobj
*vtx
= vc4
->vtx
;
135 /* VC4_DIRTY_VTXBUF */
136 struct vc4_vertexbuf_stateobj
*vertexbuf
= &vc4
->vertexbuf
;
138 /* The simulator throws a fit if VS or CS don't read an attribute, so
139 * we emit a dummy read.
141 uint32_t num_elements_emit
= MAX2(vtx
->num_elements
, 1);
142 /* Emit the shader record. */
143 struct vc4_cl_out
*shader_rec
=
144 cl_start_shader_reloc(&vc4
->shader_rec
, 3 + num_elements_emit
);
145 /* VC4_DIRTY_PRIM_MODE | VC4_DIRTY_RASTERIZER */
147 VC4_SHADER_FLAG_ENABLE_CLIPPING
|
148 VC4_SHADER_FLAG_FS_SINGLE_THREAD
|
149 ((info
->mode
== PIPE_PRIM_POINTS
&&
150 vc4
->rasterizer
->base
.point_size_per_vertex
) ?
151 VC4_SHADER_FLAG_VS_POINT_SIZE
: 0));
153 /* VC4_DIRTY_COMPILED_FS */
154 cl_u8(&shader_rec
, 0); /* fs num uniforms (unused) */
155 cl_u8(&shader_rec
, vc4
->prog
.fs
->num_inputs
);
156 cl_reloc(vc4
, &vc4
->shader_rec
, &shader_rec
, vc4
->prog
.fs
->bo
, 0);
157 cl_u32(&shader_rec
, 0); /* UBO offset written by kernel */
159 /* VC4_DIRTY_COMPILED_VS */
160 cl_u16(&shader_rec
, 0); /* vs num uniforms */
161 cl_u8(&shader_rec
, vc4
->prog
.vs
->vattrs_live
);
162 cl_u8(&shader_rec
, vc4
->prog
.vs
->vattr_offsets
[8]);
163 cl_reloc(vc4
, &vc4
->shader_rec
, &shader_rec
, vc4
->prog
.vs
->bo
, 0);
164 cl_u32(&shader_rec
, 0); /* UBO offset written by kernel */
166 /* VC4_DIRTY_COMPILED_CS */
167 cl_u16(&shader_rec
, 0); /* cs num uniforms */
168 cl_u8(&shader_rec
, vc4
->prog
.cs
->vattrs_live
);
169 cl_u8(&shader_rec
, vc4
->prog
.cs
->vattr_offsets
[8]);
170 cl_reloc(vc4
, &vc4
->shader_rec
, &shader_rec
, vc4
->prog
.cs
->bo
, 0);
171 cl_u32(&shader_rec
, 0); /* UBO offset written by kernel */
173 uint32_t max_index
= 0xffff;
174 for (int i
= 0; i
< vtx
->num_elements
; i
++) {
175 struct pipe_vertex_element
*elem
= &vtx
->pipe
[i
];
176 struct pipe_vertex_buffer
*vb
=
177 &vertexbuf
->vb
[elem
->vertex_buffer_index
];
178 struct vc4_resource
*rsc
= vc4_resource(vb
->buffer
);
179 /* not vc4->dirty tracked: vc4->last_index_bias */
180 uint32_t offset
= (vb
->buffer_offset
+
182 vb
->stride
* (info
->index_bias
+
184 uint32_t vb_size
= rsc
->bo
->size
- offset
;
186 util_format_get_blocksize(elem
->src_format
);
188 cl_reloc(vc4
, &vc4
->shader_rec
, &shader_rec
, rsc
->bo
, offset
);
189 cl_u8(&shader_rec
, elem_size
- 1);
190 cl_u8(&shader_rec
, vb
->stride
);
191 cl_u8(&shader_rec
, vc4
->prog
.vs
->vattr_offsets
[i
]);
192 cl_u8(&shader_rec
, vc4
->prog
.cs
->vattr_offsets
[i
]);
194 if (vb
->stride
> 0) {
195 max_index
= MIN2(max_index
,
196 (vb_size
- elem_size
) / vb
->stride
);
200 if (vtx
->num_elements
== 0) {
201 assert(num_elements_emit
== 1);
202 struct vc4_bo
*bo
= vc4_bo_alloc(vc4
->screen
, 4096, "scratch VBO");
203 cl_reloc(vc4
, &vc4
->shader_rec
, &shader_rec
, bo
, 0);
204 cl_u8(&shader_rec
, 16 - 1); /* element size */
205 cl_u8(&shader_rec
, 0); /* stride */
206 cl_u8(&shader_rec
, 0); /* VS VPM offset */
207 cl_u8(&shader_rec
, 0); /* CS VPM offset */
208 vc4_bo_unreference(&bo
);
210 cl_end(&vc4
->shader_rec
, shader_rec
);
212 struct vc4_cl_out
*bcl
= cl_start(&vc4
->bcl
);
213 /* the actual draw call. */
214 cl_u8(&bcl
, VC4_PACKET_GL_SHADER_STATE
);
215 assert(vtx
->num_elements
<= 8);
216 /* Note that number of attributes == 0 in the packet means 8
217 * attributes. This field also contains the offset into shader_rec.
219 cl_u32(&bcl
, num_elements_emit
& 0x7);
220 cl_end(&vc4
->bcl
, bcl
);
222 vc4_write_uniforms(vc4
, vc4
->prog
.fs
,
223 &vc4
->constbuf
[PIPE_SHADER_FRAGMENT
],
225 vc4_write_uniforms(vc4
, vc4
->prog
.vs
,
226 &vc4
->constbuf
[PIPE_SHADER_VERTEX
],
228 vc4_write_uniforms(vc4
, vc4
->prog
.cs
,
229 &vc4
->constbuf
[PIPE_SHADER_VERTEX
],
232 vc4
->last_index_bias
= info
->index_bias
+ extra_index_bias
;
233 vc4
->max_index
= max_index
;
234 vc4
->shader_rec_count
++;
238 * HW-2116 workaround: Flush the batch before triggering the hardware state
239 * counter wraparound behavior.
241 * State updates are tracked by a global counter which increments at the first
242 * state update after a draw or a START_BINNING. Tiles can then have their
243 * state updated at draw time with a set of cheap checks for whether the
244 * state's copy of the global counter matches the global counter the last time
245 * that state was written to the tile.
247 * The state counters are relatively small and wrap around quickly, so you
248 * could get false negatives for needing to update a particular state in the
249 * tile. To avoid this, the hardware attempts to write all of the state in
250 * the tile at wraparound time. This apparently is broken, so we just flush
251 * everything before that behavior is triggered. A batch flush is sufficient
252 * to get our current contents drawn and reset the counters to 0.
254 * Note that we can't just use VC4_PACKET_FLUSH_ALL, because that caps the
255 * tiles with VC4_PACKET_RETURN_FROM_LIST.
258 vc4_hw_2116_workaround(struct pipe_context
*pctx
)
260 struct vc4_context
*vc4
= vc4_context(pctx
);
262 if (vc4
->draw_calls_queued
== 0x1ef0) {
263 perf_debug("Flushing batch due to HW-2116 workaround "
264 "(too many draw calls per scene\n");
270 vc4_draw_vbo(struct pipe_context
*pctx
, const struct pipe_draw_info
*info
)
272 struct vc4_context
*vc4
= vc4_context(pctx
);
274 if (info
->mode
>= PIPE_PRIM_QUADS
) {
275 util_primconvert_save_index_buffer(vc4
->primconvert
, &vc4
->indexbuf
);
276 util_primconvert_save_rasterizer_state(vc4
->primconvert
, &vc4
->rasterizer
->base
);
277 util_primconvert_draw_vbo(vc4
->primconvert
, info
);
278 perf_debug("Fallback conversion for %d %s vertices\n",
279 info
->count
, u_prim_name(info
->mode
));
283 /* Before setting up the draw, do any fixup blits necessary. */
284 vc4_update_shadow_textures(pctx
, &vc4
->verttex
);
285 vc4_update_shadow_textures(pctx
, &vc4
->fragtex
);
287 vc4_hw_2116_workaround(pctx
);
289 vc4_get_draw_cl_space(vc4
, info
->count
);
291 if (vc4
->prim_mode
!= info
->mode
) {
292 vc4
->prim_mode
= info
->mode
;
293 vc4
->dirty
|= VC4_DIRTY_PRIM_MODE
;
296 vc4_start_draw(vc4
, info
->count
);
297 vc4_update_compiled_shaders(vc4
, info
->mode
);
299 uint32_t start_draw_calls_queued
= vc4
->draw_calls_queued
;
300 vc4_emit_state(pctx
);
302 if ((vc4
->dirty
& (VC4_DIRTY_VTXBUF
|
304 VC4_DIRTY_PRIM_MODE
|
305 VC4_DIRTY_RASTERIZER
|
306 VC4_DIRTY_COMPILED_CS
|
307 VC4_DIRTY_COMPILED_VS
|
308 VC4_DIRTY_COMPILED_FS
|
309 vc4
->prog
.cs
->uniform_dirty_bits
|
310 vc4
->prog
.vs
->uniform_dirty_bits
|
311 vc4
->prog
.fs
->uniform_dirty_bits
)) ||
312 vc4
->last_index_bias
!= info
->index_bias
) {
313 vc4_emit_gl_shader_state(vc4
, info
, 0);
318 /* Note that the primitive type fields match with OpenGL/gallium
319 * definitions, up to but not including QUADS.
321 struct vc4_cl_out
*bcl
= cl_start(&vc4
->bcl
);
323 uint32_t offset
= vc4
->indexbuf
.offset
;
324 uint32_t index_size
= vc4
->indexbuf
.index_size
;
325 struct pipe_resource
*prsc
;
326 if (vc4
->indexbuf
.index_size
== 4) {
327 prsc
= vc4_get_shadow_index_buffer(pctx
, &vc4
->indexbuf
,
328 info
->count
, &offset
);
331 if (vc4
->indexbuf
.user_buffer
) {
333 u_upload_data(vc4
->uploader
, 0,
334 info
->count
* index_size
, 4,
335 vc4
->indexbuf
.user_buffer
,
338 prsc
= vc4
->indexbuf
.buffer
;
341 struct vc4_resource
*rsc
= vc4_resource(prsc
);
343 cl_start_reloc(&vc4
->bcl
, &bcl
, 1);
344 cl_u8(&bcl
, VC4_PACKET_GL_INDEXED_PRIMITIVE
);
348 VC4_INDEX_BUFFER_U16
:
349 VC4_INDEX_BUFFER_U8
));
350 cl_u32(&bcl
, info
->count
);
351 cl_reloc(vc4
, &vc4
->bcl
, &bcl
, rsc
->bo
, offset
);
352 cl_u32(&bcl
, vc4
->max_index
);
354 if (vc4
->indexbuf
.index_size
== 4 || vc4
->indexbuf
.user_buffer
)
355 pipe_resource_reference(&prsc
, NULL
);
357 uint32_t count
= info
->count
;
358 uint32_t start
= info
->start
;
359 uint32_t extra_index_bias
= 0;
362 uint32_t this_count
= count
;
363 uint32_t step
= count
;
364 static const uint32_t max_verts
= 65535;
366 /* GFXH-515 / SW-5891: The binner emits 16 bit indices
367 * for drawarrays, which means that if start + count >
368 * 64k it would truncate the top bits. Work around
369 * this by emitting a limited number of primitives at
370 * a time and reemitting the shader state pointing
371 * farther down the vertex attribute arrays.
373 * To do this properly for line loops or trifans, we'd
374 * need to make a new VB containing the first vertex
375 * plus whatever remainder.
377 if (extra_index_bias
) {
378 cl_end(&vc4
->bcl
, bcl
);
379 vc4_emit_gl_shader_state(vc4
, info
,
381 bcl
= cl_start(&vc4
->bcl
);
384 if (start
+ count
> max_verts
) {
385 switch (info
->mode
) {
386 case PIPE_PRIM_POINTS
:
387 this_count
= step
= max_verts
;
389 case PIPE_PRIM_LINES
:
390 this_count
= step
= max_verts
- (max_verts
% 2);
392 case PIPE_PRIM_LINE_STRIP
:
393 this_count
= max_verts
;
394 step
= max_verts
- 1;
396 case PIPE_PRIM_LINE_LOOP
:
397 this_count
= max_verts
;
398 step
= max_verts
- 1;
399 debug_warn_once("unhandled line loop "
400 "looping behavior with "
403 case PIPE_PRIM_TRIANGLES
:
404 this_count
= step
= max_verts
- (max_verts
% 3);
406 case PIPE_PRIM_TRIANGLE_STRIP
:
407 this_count
= max_verts
;
408 step
= max_verts
- 2;
411 debug_warn_once("unhandled primitive "
412 "max vert count, truncating\n");
413 this_count
= step
= max_verts
;
417 cl_u8(&bcl
, VC4_PACKET_GL_ARRAY_PRIMITIVE
);
418 cl_u8(&bcl
, info
->mode
);
419 cl_u32(&bcl
, this_count
);
423 extra_index_bias
+= start
+ step
;
427 cl_end(&vc4
->bcl
, bcl
);
429 /* No flushes of the job should have happened between when we started
430 * emitting state for our draw and when we just emitted our draw's
433 assert(start_draw_calls_queued
== vc4
->draw_calls_queued
);
435 if (vc4
->zsa
&& vc4
->zsa
->base
.depth
.enabled
) {
436 vc4
->resolve
|= PIPE_CLEAR_DEPTH
;
438 if (vc4
->zsa
&& vc4
->zsa
->base
.stencil
[0].enabled
)
439 vc4
->resolve
|= PIPE_CLEAR_STENCIL
;
440 vc4
->resolve
|= PIPE_CLEAR_COLOR0
;
442 if (vc4_debug
& VC4_DEBUG_ALWAYS_FLUSH
)
447 pack_rgba(enum pipe_format format
, const float *rgba
)
450 util_pack_color(rgba
, format
, &uc
);
451 if (util_format_get_blocksize(format
) == 2)
458 vc4_clear(struct pipe_context
*pctx
, unsigned buffers
,
459 const union pipe_color_union
*color
, double depth
, unsigned stencil
)
461 struct vc4_context
*vc4
= vc4_context(pctx
);
463 /* We can't flag new buffers for clearing once we've queued draws. We
464 * could avoid this by using the 3d engine to clear.
466 if (vc4
->draw_calls_queued
) {
467 perf_debug("Flushing rendering to process new clear.\n");
471 if (buffers
& PIPE_CLEAR_COLOR0
) {
472 vc4
->clear_color
[0] = vc4
->clear_color
[1] =
473 pack_rgba(vc4
->framebuffer
.cbufs
[0]->format
,
477 if (buffers
& PIPE_CLEAR_DEPTH
) {
478 /* Though the depth buffer is stored with Z in the high 24,
479 * for this field we just need to store it in the low 24.
481 vc4
->clear_depth
= util_pack_z(PIPE_FORMAT_Z24X8_UNORM
, depth
);
484 if (buffers
& PIPE_CLEAR_STENCIL
)
485 vc4
->clear_stencil
= stencil
;
489 vc4
->draw_max_x
= vc4
->framebuffer
.width
;
490 vc4
->draw_max_y
= vc4
->framebuffer
.height
;
491 vc4
->cleared
|= buffers
;
492 vc4
->resolve
|= buffers
;
494 vc4_start_draw(vc4
, 0);
498 vc4_clear_render_target(struct pipe_context
*pctx
, struct pipe_surface
*ps
,
499 const union pipe_color_union
*color
,
500 unsigned x
, unsigned y
, unsigned w
, unsigned h
)
502 fprintf(stderr
, "unimpl: clear RT\n");
506 vc4_clear_depth_stencil(struct pipe_context
*pctx
, struct pipe_surface
*ps
,
507 unsigned buffers
, double depth
, unsigned stencil
,
508 unsigned x
, unsigned y
, unsigned w
, unsigned h
)
510 fprintf(stderr
, "unimpl: clear DS\n");
514 vc4_draw_init(struct pipe_context
*pctx
)
516 pctx
->draw_vbo
= vc4_draw_vbo
;
517 pctx
->clear
= vc4_clear
;
518 pctx
->clear_render_target
= vc4_clear_render_target
;
519 pctx
->clear_depth_stencil
= vc4_clear_depth_stencil
;