2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "util/u_format.h"
26 #include "util/u_pack_color.h"
27 #include "indices/u_primconvert.h"
29 #include "vc4_context.h"
30 #include "vc4_resource.h"
33 vc4_get_draw_cl_space(struct vc4_context
*vc4
)
35 /* Binner gets our packet state -- vc4_emit.c contents,
36 * and the primitive itself.
38 cl_ensure_space(&vc4
->bcl
, 256);
40 /* Nothing for rcl -- that's covered by vc4_context.c */
42 /* shader_rec gets up to 12 dwords of reloc handles plus a maximally
43 * sized shader_rec (104 bytes base for 8 vattrs plus 32 bytes of
46 cl_ensure_space(&vc4
->shader_rec
, 12 * sizeof(uint32_t) + 104 + 8 * 32);
48 /* Uniforms are covered by vc4_write_uniforms(). */
50 /* There could be up to 16 textures per stage, plus misc other
53 cl_ensure_space(&vc4
->bo_handles
, (2 * 16 + 20) * sizeof(uint32_t));
54 cl_ensure_space(&vc4
->bo_pointers
,
55 (2 * 16 + 20) * sizeof(struct vc4_bo
*));
59 * Does the initial bining command list setup for drawing to a given FBO.
62 vc4_start_draw(struct vc4_context
*vc4
)
67 vc4_get_draw_cl_space(vc4
);
69 uint32_t width
= vc4
->framebuffer
.width
;
70 uint32_t height
= vc4
->framebuffer
.height
;
71 uint32_t tilew
= align(width
, 64) / 64;
72 uint32_t tileh
= align(height
, 64) / 64;
74 /* Tile alloc memory setup: We use an initial alloc size of 32b. The
75 * hardware then aligns that to 256b (we use 4096, because all of our
76 * BO allocations align to that anyway), then for some reason the
77 * simulator wants an extra page available, even if you have overflow
80 * XXX: The binner only does 28-bit addressing math, so the tile alloc
81 * and tile state should be in the same BO and that BO needs to not
82 * cross a 256MB boundary, somehow.
84 uint32_t tile_alloc_size
= 32 * tilew
* tileh
;
85 tile_alloc_size
= align(tile_alloc_size
, 4096);
86 tile_alloc_size
+= 4096;
87 uint32_t tile_state_size
= 48 * tilew
* tileh
;
88 if (!vc4
->tile_alloc
|| vc4
->tile_alloc
->size
< tile_alloc_size
) {
89 vc4_bo_unreference(&vc4
->tile_alloc
);
90 vc4
->tile_alloc
= vc4_bo_alloc(vc4
->screen
, tile_alloc_size
,
93 if (!vc4
->tile_state
|| vc4
->tile_state
->size
< tile_state_size
) {
94 vc4_bo_unreference(&vc4
->tile_state
);
95 vc4
->tile_state
= vc4_bo_alloc(vc4
->screen
, tile_state_size
,
99 // Tile state data is 48 bytes per tile, I think it can be thrown away
100 // as soon as binning is finished.
101 cl_start_reloc(&vc4
->bcl
, 2);
102 cl_u8(&vc4
->bcl
, VC4_PACKET_TILE_BINNING_MODE_CONFIG
);
103 cl_reloc(vc4
, &vc4
->bcl
, vc4
->tile_alloc
, 0);
104 cl_u32(&vc4
->bcl
, vc4
->tile_alloc
->size
);
105 cl_reloc(vc4
, &vc4
->bcl
, vc4
->tile_state
, 0);
106 cl_u8(&vc4
->bcl
, tilew
);
107 cl_u8(&vc4
->bcl
, tileh
);
109 VC4_BIN_CONFIG_AUTO_INIT_TSDA
|
110 VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_32
|
111 VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_32
);
113 /* START_TILE_BINNING resets the statechange counters in the hardware,
114 * which are what is used when a primitive is binned to a tile to
115 * figure out what new state packets need to be written to that tile's
118 cl_u8(&vc4
->bcl
, VC4_PACKET_START_TILE_BINNING
);
120 /* Reset the current compressed primitives format. This gets modified
121 * by VC4_PACKET_GL_INDEXED_PRIMITIVE and
122 * VC4_PACKET_GL_ARRAY_PRIMITIVE, so it needs to be reset at the start
125 cl_u8(&vc4
->bcl
, VC4_PACKET_PRIMITIVE_LIST_FORMAT
);
126 cl_u8(&vc4
->bcl
, (VC4_PRIMITIVE_LIST_FORMAT_16_INDEX
|
127 VC4_PRIMITIVE_LIST_FORMAT_TYPE_TRIANGLES
));
129 vc4
->needs_flush
= true;
130 vc4
->draw_call_queued
= true;
134 vc4_draw_vbo(struct pipe_context
*pctx
, const struct pipe_draw_info
*info
)
136 struct vc4_context
*vc4
= vc4_context(pctx
);
138 if (info
->mode
>= PIPE_PRIM_QUADS
) {
139 util_primconvert_save_index_buffer(vc4
->primconvert
, &vc4
->indexbuf
);
140 util_primconvert_save_rasterizer_state(vc4
->primconvert
, &vc4
->rasterizer
->base
);
141 util_primconvert_draw_vbo(vc4
->primconvert
, info
);
145 vc4_get_draw_cl_space(vc4
);
147 struct vc4_vertex_stateobj
*vtx
= vc4
->vtx
;
148 struct vc4_vertexbuf_stateobj
*vertexbuf
= &vc4
->vertexbuf
;
150 if (vc4
->prim_mode
!= info
->mode
) {
151 vc4
->prim_mode
= info
->mode
;
152 vc4
->dirty
|= VC4_DIRTY_PRIM_MODE
;
156 vc4_update_compiled_shaders(vc4
, info
->mode
);
158 vc4_emit_state(pctx
);
161 vc4_write_uniforms(vc4
, vc4
->prog
.fs
,
162 &vc4
->constbuf
[PIPE_SHADER_FRAGMENT
],
164 vc4_write_uniforms(vc4
, vc4
->prog
.vs
,
165 &vc4
->constbuf
[PIPE_SHADER_VERTEX
],
167 vc4_write_uniforms(vc4
, vc4
->prog
.cs
,
168 &vc4
->constbuf
[PIPE_SHADER_VERTEX
],
171 /* The simulator throws a fit if VS or CS don't read an attribute, so
172 * we emit a dummy read.
174 uint32_t num_elements_emit
= MAX2(vtx
->num_elements
, 1);
175 /* Emit the shader record. */
176 cl_start_shader_reloc(&vc4
->shader_rec
, 3 + num_elements_emit
);
177 cl_u16(&vc4
->shader_rec
,
178 VC4_SHADER_FLAG_ENABLE_CLIPPING
|
179 ((info
->mode
== PIPE_PRIM_POINTS
&&
180 vc4
->rasterizer
->base
.point_size_per_vertex
) ?
181 VC4_SHADER_FLAG_VS_POINT_SIZE
: 0));
182 cl_u8(&vc4
->shader_rec
, 0); /* fs num uniforms (unused) */
183 cl_u8(&vc4
->shader_rec
, vc4
->prog
.fs
->num_inputs
);
184 cl_reloc(vc4
, &vc4
->shader_rec
, vc4
->prog
.fs
->bo
, 0);
185 cl_u32(&vc4
->shader_rec
, 0); /* UBO offset written by kernel */
187 cl_u16(&vc4
->shader_rec
, 0); /* vs num uniforms */
188 cl_u8(&vc4
->shader_rec
, (1 << num_elements_emit
) - 1); /* vs attribute array bitfield */
189 cl_u8(&vc4
->shader_rec
, 16 * num_elements_emit
); /* vs total attribute size */
190 cl_reloc(vc4
, &vc4
->shader_rec
, vc4
->prog
.vs
->bo
, 0);
191 cl_u32(&vc4
->shader_rec
, 0); /* UBO offset written by kernel */
193 cl_u16(&vc4
->shader_rec
, 0); /* cs num uniforms */
194 cl_u8(&vc4
->shader_rec
, (1 << num_elements_emit
) - 1); /* cs attribute array bitfield */
195 cl_u8(&vc4
->shader_rec
, 16 * num_elements_emit
); /* cs total attribute size */
196 cl_reloc(vc4
, &vc4
->shader_rec
, vc4
->prog
.cs
->bo
, 0);
197 cl_u32(&vc4
->shader_rec
, 0); /* UBO offset written by kernel */
199 uint32_t max_index
= 0xffff;
200 for (int i
= 0; i
< vtx
->num_elements
; i
++) {
201 struct pipe_vertex_element
*elem
= &vtx
->pipe
[i
];
202 struct pipe_vertex_buffer
*vb
=
203 &vertexbuf
->vb
[elem
->vertex_buffer_index
];
204 struct vc4_resource
*rsc
= vc4_resource(vb
->buffer
);
205 uint32_t offset
= vb
->buffer_offset
+ elem
->src_offset
;
206 uint32_t vb_size
= rsc
->bo
->size
- offset
;
208 util_format_get_blocksize(elem
->src_format
);
210 cl_reloc(vc4
, &vc4
->shader_rec
, rsc
->bo
, offset
);
211 cl_u8(&vc4
->shader_rec
, elem_size
- 1);
212 cl_u8(&vc4
->shader_rec
, vb
->stride
);
213 cl_u8(&vc4
->shader_rec
, i
* 16); /* VS VPM offset */
214 cl_u8(&vc4
->shader_rec
, i
* 16); /* CS VPM offset */
216 if (vb
->stride
> 0) {
217 max_index
= MIN2(max_index
,
218 (vb_size
- elem_size
) / vb
->stride
);
222 if (vtx
->num_elements
== 0) {
223 assert(num_elements_emit
== 1);
224 struct vc4_bo
*bo
= vc4_bo_alloc(vc4
->screen
, 4096, "scratch VBO");
225 cl_reloc(vc4
, &vc4
->shader_rec
, bo
, 0);
226 cl_u8(&vc4
->shader_rec
, 16 - 1); /* element size */
227 cl_u8(&vc4
->shader_rec
, 0); /* stride */
228 cl_u8(&vc4
->shader_rec
, 0); /* VS VPM offset */
229 cl_u8(&vc4
->shader_rec
, 0); /* CS VPM offset */
230 vc4_bo_unreference(&bo
);
233 /* the actual draw call. */
234 cl_u8(&vc4
->bcl
, VC4_PACKET_GL_SHADER_STATE
);
235 assert(vtx
->num_elements
<= 8);
236 /* Note that number of attributes == 0 in the packet means 8
237 * attributes. This field also contains the offset into shader_rec.
239 cl_u32(&vc4
->bcl
, num_elements_emit
& 0x7);
241 /* Note that the primitive type fields match with OpenGL/gallium
242 * definitions, up to but not including QUADS.
245 struct vc4_resource
*rsc
= vc4_resource(vc4
->indexbuf
.buffer
);
246 uint32_t offset
= vc4
->indexbuf
.offset
;
247 uint32_t index_size
= vc4
->indexbuf
.index_size
;
248 if (rsc
->shadow_parent
) {
249 vc4_update_shadow_index_buffer(pctx
, &vc4
->indexbuf
);
253 cl_start_reloc(&vc4
->bcl
, 1);
254 cl_u8(&vc4
->bcl
, VC4_PACKET_GL_INDEXED_PRIMITIVE
);
258 VC4_INDEX_BUFFER_U16
:
259 VC4_INDEX_BUFFER_U8
));
260 cl_u32(&vc4
->bcl
, info
->count
);
261 cl_reloc(vc4
, &vc4
->bcl
, rsc
->bo
, offset
);
262 cl_u32(&vc4
->bcl
, max_index
);
264 cl_u8(&vc4
->bcl
, VC4_PACKET_GL_ARRAY_PRIMITIVE
);
265 cl_u8(&vc4
->bcl
, info
->mode
);
266 cl_u32(&vc4
->bcl
, info
->count
);
267 cl_u32(&vc4
->bcl
, info
->start
);
270 if (vc4
->zsa
&& vc4
->zsa
->base
.depth
.enabled
) {
271 vc4
->resolve
|= PIPE_CLEAR_DEPTH
;
273 if (vc4
->zsa
&& vc4
->zsa
->base
.stencil
[0].enabled
)
274 vc4
->resolve
|= PIPE_CLEAR_STENCIL
;
275 vc4
->resolve
|= PIPE_CLEAR_COLOR0
;
277 vc4
->shader_rec_count
++;
279 if (vc4_debug
& VC4_DEBUG_ALWAYS_FLUSH
)
284 pack_rgba(enum pipe_format format
, const float *rgba
)
287 util_pack_color(rgba
, format
, &uc
);
292 vc4_clear(struct pipe_context
*pctx
, unsigned buffers
,
293 const union pipe_color_union
*color
, double depth
, unsigned stencil
)
295 struct vc4_context
*vc4
= vc4_context(pctx
);
297 /* We can't flag new buffers for clearing once we've queued draws. We
298 * could avoid this by using the 3d engine to clear.
300 if (vc4
->draw_call_queued
)
303 if (buffers
& PIPE_CLEAR_COLOR0
) {
304 vc4
->clear_color
[0] = vc4
->clear_color
[1] =
305 pack_rgba(vc4
->framebuffer
.cbufs
[0]->format
,
309 if (buffers
& PIPE_CLEAR_DEPTH
) {
310 /* Though the depth buffer is stored with Z in the high 24,
311 * for this field we just need to store it in the low 24.
313 vc4
->clear_depth
= util_pack_z(PIPE_FORMAT_Z24X8_UNORM
, depth
);
316 if (buffers
& PIPE_CLEAR_STENCIL
)
317 vc4
->clear_stencil
= stencil
;
321 vc4
->draw_max_x
= vc4
->framebuffer
.width
;
322 vc4
->draw_max_y
= vc4
->framebuffer
.height
;
323 vc4
->cleared
|= buffers
;
324 vc4
->resolve
|= buffers
;
330 vc4_clear_render_target(struct pipe_context
*pctx
, struct pipe_surface
*ps
,
331 const union pipe_color_union
*color
,
332 unsigned x
, unsigned y
, unsigned w
, unsigned h
)
334 fprintf(stderr
, "unimpl: clear RT\n");
338 vc4_clear_depth_stencil(struct pipe_context
*pctx
, struct pipe_surface
*ps
,
339 unsigned buffers
, double depth
, unsigned stencil
,
340 unsigned x
, unsigned y
, unsigned w
, unsigned h
)
342 fprintf(stderr
, "unimpl: clear DS\n");
346 vc4_draw_init(struct pipe_context
*pctx
)
348 pctx
->draw_vbo
= vc4_draw_vbo
;
349 pctx
->clear
= vc4_clear
;
350 pctx
->clear_render_target
= vc4_clear_render_target
;
351 pctx
->clear_depth_stencil
= vc4_clear_depth_stencil
;