2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "util/u_blitter.h"
26 #include "util/u_prim.h"
27 #include "util/u_format.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_upload_mgr.h"
30 #include "indices/u_primconvert.h"
32 #include "vc4_context.h"
33 #include "vc4_resource.h"
35 #define VC4_HW_2116_COUNT 0x1ef0
38 vc4_get_draw_cl_space(struct vc4_job
*job
, int vert_count
)
40 /* The SW-5891 workaround may cause us to emit multiple shader recs
43 int num_draws
= DIV_ROUND_UP(vert_count
, 65535 - 2) + 1;
45 /* Binner gets our packet state -- vc4_emit.c contents,
46 * and the primitive itself.
48 cl_ensure_space(&job
->bcl
,
49 256 + (VC4_PACKET_GL_ARRAY_PRIMITIVE_SIZE
+
50 VC4_PACKET_GL_SHADER_STATE_SIZE
) * num_draws
);
52 /* Nothing for rcl -- that's covered by vc4_context.c */
54 /* shader_rec gets up to 12 dwords of reloc handles plus a maximally
55 * sized shader_rec (104 bytes base for 8 vattrs plus 32 bytes of
58 cl_ensure_space(&job
->shader_rec
,
59 (12 * sizeof(uint32_t) + 104 + 8 * 32) * num_draws
);
61 /* Uniforms are covered by vc4_write_uniforms(). */
63 /* There could be up to 16 textures per stage, plus misc other
66 cl_ensure_space(&job
->bo_handles
, (2 * 16 + 20) * sizeof(uint32_t));
67 cl_ensure_space(&job
->bo_pointers
,
68 (2 * 16 + 20) * sizeof(struct vc4_bo
*));
72 * Does the initial bining command list setup for drawing to a given FBO.
75 vc4_start_draw(struct vc4_context
*vc4
)
77 struct vc4_job
*job
= vc4
->job
;
82 vc4_get_draw_cl_space(job
, 0);
84 cl_emit(&job
->bcl
, TILE_BINNING_MODE_CONFIGURATION
, bin
) {
85 bin
.width_in_tiles
= job
->draw_tiles_x
;
86 bin
.height_in_tiles
= job
->draw_tiles_y
;
87 bin
.multisample_mode_4x
= job
->msaa
;
90 /* START_TILE_BINNING resets the statechange counters in the hardware,
91 * which are what is used when a primitive is binned to a tile to
92 * figure out what new state packets need to be written to that tile's
95 cl_emit(&job
->bcl
, START_TILE_BINNING
, start
);
97 /* Reset the current compressed primitives format. This gets modified
98 * by VC4_PACKET_GL_INDEXED_PRIMITIVE and
99 * VC4_PACKET_GL_ARRAY_PRIMITIVE, so it needs to be reset at the start
102 cl_emit(&job
->bcl
, PRIMITIVE_LIST_FORMAT
, list
) {
103 list
.data_type
= _16_BIT_INDEX
;
104 list
.primitive_type
= TRIANGLES_LIST
;
107 job
->needs_flush
= true;
108 job
->draw_width
= vc4
->framebuffer
.width
;
109 job
->draw_height
= vc4
->framebuffer
.height
;
113 vc4_predraw_check_textures(struct pipe_context
*pctx
,
114 struct vc4_texture_stateobj
*stage_tex
)
116 struct vc4_context
*vc4
= vc4_context(pctx
);
118 for (int i
= 0; i
< stage_tex
->num_textures
; i
++) {
119 struct vc4_sampler_view
*view
=
120 vc4_sampler_view(stage_tex
->textures
[i
]);
124 if (view
->texture
!= view
->base
.texture
)
125 vc4_update_shadow_baselevel_texture(pctx
, &view
->base
);
127 vc4_flush_jobs_writing_resource(vc4
, view
->texture
);
132 vc4_emit_gl_shader_state(struct vc4_context
*vc4
,
133 const struct pipe_draw_info
*info
,
134 uint32_t extra_index_bias
)
136 struct vc4_job
*job
= vc4
->job
;
137 /* VC4_DIRTY_VTXSTATE */
138 struct vc4_vertex_stateobj
*vtx
= vc4
->vtx
;
139 /* VC4_DIRTY_VTXBUF */
140 struct vc4_vertexbuf_stateobj
*vertexbuf
= &vc4
->vertexbuf
;
142 /* The simulator throws a fit if VS or CS don't read an attribute, so
143 * we emit a dummy read.
145 uint32_t num_elements_emit
= MAX2(vtx
->num_elements
, 1);
147 /* Emit the shader record. */
148 cl_start_shader_reloc(&job
->shader_rec
, 3 + num_elements_emit
);
150 cl_emit(&job
->shader_rec
, SHADER_RECORD
, rec
) {
151 rec
.enable_clipping
= true;
153 /* VC4_DIRTY_COMPILED_FS */
154 rec
.fragment_shader_is_single_threaded
=
155 !vc4
->prog
.fs
->fs_threaded
;
157 /* VC4_DIRTY_PRIM_MODE | VC4_DIRTY_RASTERIZER */
158 rec
.point_size_included_in_shaded_vertex_data
=
159 (info
->mode
== PIPE_PRIM_POINTS
&&
160 vc4
->rasterizer
->base
.point_size_per_vertex
);
162 /* VC4_DIRTY_COMPILED_FS */
163 rec
.fragment_shader_number_of_varyings
=
164 vc4
->prog
.fs
->num_inputs
;
165 rec
.fragment_shader_code_address
=
166 cl_address(vc4
->prog
.fs
->bo
, 0);
168 rec
.coordinate_shader_attribute_array_select_bits
=
169 vc4
->prog
.cs
->vattrs_live
;
170 rec
.coordinate_shader_total_attributes_size
=
171 vc4
->prog
.cs
->vattr_offsets
[8];
172 rec
.coordinate_shader_code_address
=
173 cl_address(vc4
->prog
.cs
->bo
, 0);
175 rec
.vertex_shader_attribute_array_select_bits
=
176 vc4
->prog
.vs
->vattrs_live
;
177 rec
.vertex_shader_total_attributes_size
=
178 vc4
->prog
.vs
->vattr_offsets
[8];
179 rec
.vertex_shader_code_address
=
180 cl_address(vc4
->prog
.vs
->bo
, 0);
183 uint32_t max_index
= 0xffff;
184 for (int i
= 0; i
< vtx
->num_elements
; i
++) {
185 struct pipe_vertex_element
*elem
= &vtx
->pipe
[i
];
186 struct pipe_vertex_buffer
*vb
=
187 &vertexbuf
->vb
[elem
->vertex_buffer_index
];
188 struct vc4_resource
*rsc
= vc4_resource(vb
->buffer
.resource
);
189 /* not vc4->dirty tracked: vc4->last_index_bias */
190 uint32_t offset
= (vb
->buffer_offset
+
192 vb
->stride
* (info
->index_bias
+
194 uint32_t vb_size
= rsc
->bo
->size
- offset
;
196 util_format_get_blocksize(elem
->src_format
);
198 cl_emit(&job
->shader_rec
, ATTRIBUTE_RECORD
, attr
) {
199 attr
.address
= cl_address(rsc
->bo
, offset
);
200 attr
.number_of_bytes_minus_1
= elem_size
- 1;
201 attr
.stride
= vb
->stride
;
202 attr
.coordinate_shader_vpm_offset
=
203 vc4
->prog
.cs
->vattr_offsets
[i
];
204 attr
.vertex_shader_vpm_offset
=
205 vc4
->prog
.vs
->vattr_offsets
[i
];
208 if (vb
->stride
> 0) {
209 max_index
= MIN2(max_index
,
210 (vb_size
- elem_size
) / vb
->stride
);
214 if (vtx
->num_elements
== 0) {
215 assert(num_elements_emit
== 1);
216 struct vc4_bo
*bo
= vc4_bo_alloc(vc4
->screen
, 4096, "scratch VBO");
218 cl_emit(&job
->shader_rec
, ATTRIBUTE_RECORD
, attr
) {
219 attr
.address
= cl_address(bo
, 0);
220 attr
.number_of_bytes_minus_1
= 16 - 1;
222 attr
.coordinate_shader_vpm_offset
= 0;
223 attr
.vertex_shader_vpm_offset
= 0;
227 cl_emit(&job
->bcl
, GL_SHADER_STATE
, shader_state
) {
228 /* Note that number of attributes == 0 in the packet means 8
229 * attributes. This field also contains the offset into
232 assert(vtx
->num_elements
<= 8);
233 shader_state
.number_of_attribute_arrays
=
234 num_elements_emit
& 0x7;
237 vc4_write_uniforms(vc4
, vc4
->prog
.fs
,
238 &vc4
->constbuf
[PIPE_SHADER_FRAGMENT
],
240 vc4_write_uniforms(vc4
, vc4
->prog
.vs
,
241 &vc4
->constbuf
[PIPE_SHADER_VERTEX
],
243 vc4_write_uniforms(vc4
, vc4
->prog
.cs
,
244 &vc4
->constbuf
[PIPE_SHADER_VERTEX
],
247 vc4
->last_index_bias
= info
->index_bias
+ extra_index_bias
;
248 vc4
->max_index
= max_index
;
249 job
->shader_rec_count
++;
253 * HW-2116 workaround: Flush the batch before triggering the hardware state
254 * counter wraparound behavior.
256 * State updates are tracked by a global counter which increments at the first
257 * state update after a draw or a START_BINNING. Tiles can then have their
258 * state updated at draw time with a set of cheap checks for whether the
259 * state's copy of the global counter matches the global counter the last time
260 * that state was written to the tile.
262 * The state counters are relatively small and wrap around quickly, so you
263 * could get false negatives for needing to update a particular state in the
264 * tile. To avoid this, the hardware attempts to write all of the state in
265 * the tile at wraparound time. This apparently is broken, so we just flush
266 * everything before that behavior is triggered. A batch flush is sufficient
267 * to get our current contents drawn and reset the counters to 0.
269 * Note that we can't just use VC4_PACKET_FLUSH_ALL, because that caps the
270 * tiles with VC4_PACKET_RETURN_FROM_LIST.
273 vc4_hw_2116_workaround(struct pipe_context
*pctx
, int vert_count
)
275 struct vc4_context
*vc4
= vc4_context(pctx
);
276 struct vc4_job
*job
= vc4_get_job_for_fbo(vc4
);
278 if (job
->draw_calls_queued
+ vert_count
/ 65535 >= VC4_HW_2116_COUNT
) {
279 perf_debug("Flushing batch due to HW-2116 workaround "
280 "(too many draw calls per scene\n");
281 vc4_job_submit(vc4
, job
);
286 vc4_draw_vbo(struct pipe_context
*pctx
, const struct pipe_draw_info
*info
)
288 struct vc4_context
*vc4
= vc4_context(pctx
);
290 if (!info
->count_from_stream_output
&& !info
->indirect
&&
291 !info
->primitive_restart
&&
292 !u_trim_pipe_prim(info
->mode
, (unsigned*)&info
->count
))
295 if (info
->mode
>= PIPE_PRIM_QUADS
) {
296 util_primconvert_save_rasterizer_state(vc4
->primconvert
, &vc4
->rasterizer
->base
);
297 util_primconvert_draw_vbo(vc4
->primconvert
, info
);
298 perf_debug("Fallback conversion for %d %s vertices\n",
299 info
->count
, u_prim_name(info
->mode
));
303 /* Before setting up the draw, do any fixup blits necessary. */
304 vc4_predraw_check_textures(pctx
, &vc4
->verttex
);
305 vc4_predraw_check_textures(pctx
, &vc4
->fragtex
);
307 vc4_hw_2116_workaround(pctx
, info
->count
);
309 struct vc4_job
*job
= vc4_get_job_for_fbo(vc4
);
311 /* Make sure that the raster order flags haven't changed, which can
312 * only be set at job granularity.
314 if (job
->flags
!= vc4
->rasterizer
->tile_raster_order_flags
) {
315 vc4_job_submit(vc4
, job
);
316 job
= vc4_get_job_for_fbo(vc4
);
319 vc4_get_draw_cl_space(job
, info
->count
);
321 if (vc4
->prim_mode
!= info
->mode
) {
322 vc4
->prim_mode
= info
->mode
;
323 vc4
->dirty
|= VC4_DIRTY_PRIM_MODE
;
327 if (!vc4_update_compiled_shaders(vc4
, info
->mode
)) {
328 debug_warn_once("shader compile failed, skipping draw call.\n");
332 vc4_emit_state(pctx
);
334 bool needs_drawarrays_shader_state
= false;
335 if ((vc4
->dirty
& (VC4_DIRTY_VTXBUF
|
337 VC4_DIRTY_PRIM_MODE
|
338 VC4_DIRTY_RASTERIZER
|
339 VC4_DIRTY_COMPILED_CS
|
340 VC4_DIRTY_COMPILED_VS
|
341 VC4_DIRTY_COMPILED_FS
|
342 vc4
->prog
.cs
->uniform_dirty_bits
|
343 vc4
->prog
.vs
->uniform_dirty_bits
|
344 vc4
->prog
.fs
->uniform_dirty_bits
)) ||
345 vc4
->last_index_bias
!= info
->index_bias
) {
346 if (info
->index_size
)
347 vc4_emit_gl_shader_state(vc4
, info
, 0);
349 needs_drawarrays_shader_state
= true;
354 /* Note that the primitive type fields match with OpenGL/gallium
355 * definitions, up to but not including QUADS.
357 if (info
->index_size
) {
358 uint32_t index_size
= info
->index_size
;
359 uint32_t offset
= info
->start
* index_size
;
360 struct pipe_resource
*prsc
;
361 if (info
->index_size
== 4) {
362 prsc
= vc4_get_shadow_index_buffer(pctx
, info
,
364 info
->count
, &offset
);
367 if (info
->has_user_indices
) {
369 u_upload_data(vc4
->uploader
, 0,
370 info
->count
* index_size
, 4,
374 prsc
= info
->index
.resource
;
377 struct vc4_resource
*rsc
= vc4_resource(prsc
);
379 struct vc4_cl_out
*bcl
= cl_start(&job
->bcl
);
381 /* The original design for the VC4 kernel UABI had multiple
382 * packets that used relocations in the BCL (some of which
383 * needed two BOs), but later modifications eliminated all but
384 * this one usage. We have an arbitrary 32-bit offset value,
385 * and need to also supply an arbitrary 32-bit index buffer
386 * GEM handle, so we have this fake packet we emit in our BCL
387 * to be validated, which the kernel uses at validation time
388 * to perform the relocation in the IB packet (without
389 * emitting to the actual HW).
391 uint32_t hindex
= vc4_gem_hindex(job
, rsc
->bo
);
392 if (job
->last_gem_handle_hindex
!= hindex
) {
393 cl_u8(&bcl
, VC4_PACKET_GEM_HANDLES
);
394 cl_u32(&bcl
, hindex
);
396 job
->last_gem_handle_hindex
= hindex
;
399 cl_u8(&bcl
, VC4_PACKET_GL_INDEXED_PRIMITIVE
);
403 VC4_INDEX_BUFFER_U16
:
404 VC4_INDEX_BUFFER_U8
));
405 cl_u32(&bcl
, info
->count
);
406 cl_u32(&bcl
, offset
);
407 cl_u32(&bcl
, vc4
->max_index
);
409 cl_end(&job
->bcl
, bcl
);
410 job
->draw_calls_queued
++;
412 if (info
->index_size
== 4 || info
->has_user_indices
)
413 pipe_resource_reference(&prsc
, NULL
);
415 uint32_t count
= info
->count
;
416 uint32_t start
= info
->start
;
417 uint32_t extra_index_bias
= 0;
418 static const uint32_t max_verts
= 65535;
420 /* GFXH-515 / SW-5891: The binner emits 16 bit indices for
421 * drawarrays, which means that if start + count > 64k it
422 * would truncate the top bits. Work around this by emitting
423 * a limited number of primitives at a time and reemitting the
424 * shader state pointing farther down the vertex attribute
427 * To do this properly for line loops or trifans, we'd need to
428 * make a new VB containing the first vertex plus whatever
431 if (start
+ count
> max_verts
) {
432 extra_index_bias
= start
;
434 needs_drawarrays_shader_state
= true;
438 uint32_t this_count
= count
;
439 uint32_t step
= count
;
441 if (needs_drawarrays_shader_state
) {
442 vc4_emit_gl_shader_state(vc4
, info
,
446 if (count
> max_verts
) {
447 switch (info
->mode
) {
448 case PIPE_PRIM_POINTS
:
449 this_count
= step
= max_verts
;
451 case PIPE_PRIM_LINES
:
452 this_count
= step
= max_verts
- (max_verts
% 2);
454 case PIPE_PRIM_LINE_STRIP
:
455 this_count
= max_verts
;
456 step
= max_verts
- 1;
458 case PIPE_PRIM_LINE_LOOP
:
459 this_count
= max_verts
;
460 step
= max_verts
- 1;
461 debug_warn_once("unhandled line loop "
462 "looping behavior with "
465 case PIPE_PRIM_TRIANGLES
:
466 this_count
= step
= max_verts
- (max_verts
% 3);
468 case PIPE_PRIM_TRIANGLE_STRIP
:
469 this_count
= max_verts
;
470 step
= max_verts
- 2;
473 debug_warn_once("unhandled primitive "
474 "max vert count, truncating\n");
475 this_count
= step
= max_verts
;
479 cl_emit(&job
->bcl
, VERTEX_ARRAY_PRIMITIVES
, array
) {
480 array
.primitive_mode
= info
->mode
;
481 array
.length
= this_count
;
482 array
.index_of_first_vertex
= start
;
484 job
->draw_calls_queued
++;
487 extra_index_bias
+= start
+ step
;
489 needs_drawarrays_shader_state
= true;
493 /* We shouldn't have tripped the HW_2116 bug with the GFXH-515
496 assert(job
->draw_calls_queued
<= VC4_HW_2116_COUNT
);
498 if (vc4
->zsa
&& vc4
->framebuffer
.zsbuf
) {
499 struct vc4_resource
*rsc
=
500 vc4_resource(vc4
->framebuffer
.zsbuf
->texture
);
502 if (vc4
->zsa
->base
.depth
.enabled
) {
503 job
->resolve
|= PIPE_CLEAR_DEPTH
;
504 rsc
->initialized_buffers
= PIPE_CLEAR_DEPTH
;
507 if (vc4
->zsa
->base
.stencil
[0].enabled
) {
508 job
->resolve
|= PIPE_CLEAR_STENCIL
;
509 rsc
->initialized_buffers
|= PIPE_CLEAR_STENCIL
;
513 job
->resolve
|= PIPE_CLEAR_COLOR0
;
515 /* If we've used half of the presumably 256MB CMA area, flush the job
516 * so that we don't accumulate a job that will end up not being
519 if (job
->bo_space
> 128 * 1024 * 1024)
522 if (vc4_debug
& VC4_DEBUG_ALWAYS_FLUSH
)
527 pack_rgba(enum pipe_format format
, const float *rgba
)
530 util_pack_color(rgba
, format
, &uc
);
531 if (util_format_get_blocksize(format
) == 2)
538 vc4_clear(struct pipe_context
*pctx
, unsigned buffers
,
539 const union pipe_color_union
*color
, double depth
, unsigned stencil
)
541 struct vc4_context
*vc4
= vc4_context(pctx
);
542 struct vc4_job
*job
= vc4_get_job_for_fbo(vc4
);
544 if (buffers
& PIPE_CLEAR_DEPTHSTENCIL
) {
545 struct vc4_resource
*rsc
=
546 vc4_resource(vc4
->framebuffer
.zsbuf
->texture
);
547 unsigned zsclear
= buffers
& PIPE_CLEAR_DEPTHSTENCIL
;
549 /* Clearing ZS will clear both Z and stencil, so if we're
550 * trying to clear just one then we need to draw a quad to do
551 * it instead. We need to do this before setting up
552 * tile-based clears in vc4->job, because the blitter may
553 * submit the current job.
555 if ((zsclear
== PIPE_CLEAR_DEPTH
||
556 zsclear
== PIPE_CLEAR_STENCIL
) &&
557 (rsc
->initialized_buffers
& ~(zsclear
| job
->cleared
)) &&
558 util_format_is_depth_and_stencil(vc4
->framebuffer
.zsbuf
->format
)) {
559 static const union pipe_color_union dummy_color
= {};
561 perf_debug("Partial clear of Z+stencil buffer, "
562 "drawing a quad instead of fast clearing\n");
563 vc4_blitter_save(vc4
);
564 util_blitter_clear(vc4
->blitter
,
565 vc4
->framebuffer
.width
,
566 vc4
->framebuffer
.height
,
569 &dummy_color
, depth
, stencil
);
573 job
= vc4_get_job_for_fbo(vc4
);
577 /* We can't flag new buffers for clearing once we've queued draws. We
578 * could avoid this by using the 3d engine to clear.
580 if (job
->draw_calls_queued
) {
581 perf_debug("Flushing rendering to process new clear.\n");
582 vc4_job_submit(vc4
, job
);
583 job
= vc4_get_job_for_fbo(vc4
);
586 if (buffers
& PIPE_CLEAR_COLOR0
) {
587 struct vc4_resource
*rsc
=
588 vc4_resource(vc4
->framebuffer
.cbufs
[0]->texture
);
589 uint32_t clear_color
;
591 if (vc4_rt_format_is_565(vc4
->framebuffer
.cbufs
[0]->format
)) {
592 /* In 565 mode, the hardware will be packing our color
595 clear_color
= pack_rgba(PIPE_FORMAT_R8G8B8A8_UNORM
,
598 /* Otherwise, we need to do this packing because we
599 * support multiple swizzlings of RGBA8888.
602 pack_rgba(vc4
->framebuffer
.cbufs
[0]->format
,
605 job
->clear_color
[0] = job
->clear_color
[1] = clear_color
;
606 rsc
->initialized_buffers
|= (buffers
& PIPE_CLEAR_COLOR0
);
609 if (buffers
& PIPE_CLEAR_DEPTHSTENCIL
) {
610 struct vc4_resource
*rsc
=
611 vc4_resource(vc4
->framebuffer
.zsbuf
->texture
);
613 /* Though the depth buffer is stored with Z in the high 24,
614 * for this field we just need to store it in the low 24.
616 if (buffers
& PIPE_CLEAR_DEPTH
) {
617 job
->clear_depth
= util_pack_z(PIPE_FORMAT_Z24X8_UNORM
,
620 if (buffers
& PIPE_CLEAR_STENCIL
)
621 job
->clear_stencil
= stencil
;
623 rsc
->initialized_buffers
|= (buffers
& PIPE_CLEAR_DEPTHSTENCIL
);
628 job
->draw_max_x
= vc4
->framebuffer
.width
;
629 job
->draw_max_y
= vc4
->framebuffer
.height
;
630 job
->cleared
|= buffers
;
631 job
->resolve
|= buffers
;
637 vc4_clear_render_target(struct pipe_context
*pctx
, struct pipe_surface
*ps
,
638 const union pipe_color_union
*color
,
639 unsigned x
, unsigned y
, unsigned w
, unsigned h
,
640 bool render_condition_enabled
)
642 fprintf(stderr
, "unimpl: clear RT\n");
646 vc4_clear_depth_stencil(struct pipe_context
*pctx
, struct pipe_surface
*ps
,
647 unsigned buffers
, double depth
, unsigned stencil
,
648 unsigned x
, unsigned y
, unsigned w
, unsigned h
,
649 bool render_condition_enabled
)
651 fprintf(stderr
, "unimpl: clear DS\n");
655 vc4_draw_init(struct pipe_context
*pctx
)
657 pctx
->draw_vbo
= vc4_draw_vbo
;
658 pctx
->clear
= vc4_clear
;
659 pctx
->clear_render_target
= vc4_clear_render_target
;
660 pctx
->clear_depth_stencil
= vc4_clear_depth_stencil
;