src/gallium/drivers/vc4/vc4_draw.c

   1 /*
   2  * Copyright (c) 2014 Scott Mansell
   3  * Copyright © 2014 Broadcom
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #include "util/u_prim.h"
  26 #include "util/u_format.h"
  27 #include "util/u_pack_color.h"
  28 #include "indices/u_primconvert.h"
  29
  30 #include "vc4_context.h"
  31 #include "vc4_resource.h"
  32
  33 static void
  34 vc4_get_draw_cl_space(struct vc4_context *vc4)
  35 {
  36         /* Binner gets our packet state -- vc4_emit.c contents,
  37          * and the primitive itself.
  38          */
  39         cl_ensure_space(&vc4->bcl, 256);
  40
  41         /* Nothing for rcl -- that's covered by vc4_context.c */
  42
  43         /* shader_rec gets up to 12 dwords of reloc handles plus a maximally
  44          * sized shader_rec (104 bytes base for 8 vattrs plus 32 bytes of
  45          * vattr stride).
  46          */
  47         cl_ensure_space(&vc4->shader_rec, 12 * sizeof(uint32_t) + 104 + 8 * 32);
  48
  49         /* Uniforms are covered by vc4_write_uniforms(). */
  50
  51         /* There could be up to 16 textures per stage, plus misc other
  52          * pointers.
  53          */
  54         cl_ensure_space(&vc4->bo_handles, (2 * 16 + 20) * sizeof(uint32_t));
  55         cl_ensure_space(&vc4->bo_pointers,
  56                         (2 * 16 + 20) * sizeof(struct vc4_bo *));
  57 }
  58
  59 /**
  60  * Does the initial bining command list setup for drawing to a given FBO.
  61  */
  62 static void
  63 vc4_start_draw(struct vc4_context *vc4)
  64 {
  65         if (vc4->needs_flush)
  66                 return;
  67
  68         vc4_get_draw_cl_space(vc4);
  69
  70         uint32_t width = vc4->framebuffer.width;
  71         uint32_t height = vc4->framebuffer.height;
  72         uint32_t tilew = align(width, 64) / 64;
  73         uint32_t tileh = align(height, 64) / 64;
  74         struct vc4_cl_out *bcl = cl_start(&vc4->bcl);
  75
  76         //   Tile state data is 48 bytes per tile, I think it can be thrown away
  77         //   as soon as binning is finished.
  78         cl_u8(&bcl, VC4_PACKET_TILE_BINNING_MODE_CONFIG);
  79         cl_u32(&bcl, 0); /* tile alloc addr, filled by kernel */
  80         cl_u32(&bcl, 0); /* tile alloc size, filled by kernel */
  81         cl_u32(&bcl, 0); /* tile state addr, filled by kernel */
  82         cl_u8(&bcl, tilew);
  83         cl_u8(&bcl, tileh);
  84         cl_u8(&bcl, 0); /* flags, filled by kernel. */
  85
  86         /* START_TILE_BINNING resets the statechange counters in the hardware,
  87          * which are what is used when a primitive is binned to a tile to
  88          * figure out what new state packets need to be written to that tile's
  89          * command list.
  90          */
  91         cl_u8(&bcl, VC4_PACKET_START_TILE_BINNING);
  92
  93         /* Reset the current compressed primitives format.  This gets modified
  94          * by VC4_PACKET_GL_INDEXED_PRIMITIVE and
  95          * VC4_PACKET_GL_ARRAY_PRIMITIVE, so it needs to be reset at the start
  96          * of every tile.
  97          */
  98         cl_u8(&bcl, VC4_PACKET_PRIMITIVE_LIST_FORMAT);
  99         cl_u8(&bcl, (VC4_PRIMITIVE_LIST_FORMAT_16_INDEX |
 100                      VC4_PRIMITIVE_LIST_FORMAT_TYPE_TRIANGLES));
 101
 102         vc4->needs_flush = true;
 103         vc4->draw_call_queued = true;
 104         vc4->draw_width = width;
 105         vc4->draw_height = height;
 106
 107         cl_end(&vc4->bcl, bcl);
 108 }
 109
 110 static void
 111 vc4_update_shadow_textures(struct pipe_context *pctx,
 112                            struct vc4_texture_stateobj *stage_tex)
 113 {
 114         for (int i = 0; i < stage_tex->num_textures; i++) {
 115                 struct pipe_sampler_view *view = stage_tex->textures[i];
 116                 if (!view)
 117                         continue;
 118                 struct vc4_resource *rsc = vc4_resource(view->texture);
 119                 if (rsc->shadow_parent)
 120                         vc4_update_shadow_baselevel_texture(pctx, view);
 121         }
 122 }
 123
 124 static void
 125 vc4_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
 126 {
 127         struct vc4_context *vc4 = vc4_context(pctx);
 128
 129         if (info->mode >= PIPE_PRIM_QUADS) {
 130                 util_primconvert_save_index_buffer(vc4->primconvert, &vc4->indexbuf);
 131                 util_primconvert_save_rasterizer_state(vc4->primconvert, &vc4->rasterizer->base);
 132                 util_primconvert_draw_vbo(vc4->primconvert, info);
 133                 perf_debug("Fallback conversion for %d %s vertices\n",
 134                            info->count, u_prim_name(info->mode));
 135                 return;
 136         }
 137
 138         /* Before setting up the draw, do any fixup blits necessary. */
 139         vc4_update_shadow_textures(pctx, &vc4->verttex);
 140         vc4_update_shadow_textures(pctx, &vc4->fragtex);
 141
 142         vc4_get_draw_cl_space(vc4);
 143
 144         struct vc4_vertex_stateobj *vtx = vc4->vtx;
 145         struct vc4_vertexbuf_stateobj *vertexbuf = &vc4->vertexbuf;
 146
 147         if (vc4->prim_mode != info->mode) {
 148                 vc4->prim_mode = info->mode;
 149                 vc4->dirty |= VC4_DIRTY_PRIM_MODE;
 150         }
 151
 152         vc4_start_draw(vc4);
 153         vc4_update_compiled_shaders(vc4, info->mode);
 154
 155         vc4_emit_state(pctx);
 156         vc4->dirty = 0;
 157
 158         vc4_write_uniforms(vc4, vc4->prog.fs,
 159                            &vc4->constbuf[PIPE_SHADER_FRAGMENT],
 160                            &vc4->fragtex);
 161         vc4_write_uniforms(vc4, vc4->prog.vs,
 162                            &vc4->constbuf[PIPE_SHADER_VERTEX],
 163                            &vc4->verttex);
 164         vc4_write_uniforms(vc4, vc4->prog.cs,
 165                            &vc4->constbuf[PIPE_SHADER_VERTEX],
 166                            &vc4->verttex);
 167
 168         /* The simulator throws a fit if VS or CS don't read an attribute, so
 169          * we emit a dummy read.
 170          */
 171         uint32_t num_elements_emit = MAX2(vtx->num_elements, 1);
 172         /* Emit the shader record. */
 173         struct vc4_cl_out *shader_rec =
 174                 cl_start_shader_reloc(&vc4->shader_rec, 3 + num_elements_emit);
 175         cl_u16(&shader_rec,
 176                VC4_SHADER_FLAG_ENABLE_CLIPPING |
 177                ((info->mode == PIPE_PRIM_POINTS &&
 178                  vc4->rasterizer->base.point_size_per_vertex) ?
 179                 VC4_SHADER_FLAG_VS_POINT_SIZE : 0));
 180         cl_u8(&shader_rec, 0); /* fs num uniforms (unused) */
 181         cl_u8(&shader_rec, vc4->prog.fs->num_inputs);
 182         cl_reloc(vc4, &vc4->shader_rec, &shader_rec, vc4->prog.fs->bo, 0);
 183         cl_u32(&shader_rec, 0); /* UBO offset written by kernel */
 184
 185         cl_u16(&shader_rec, 0); /* vs num uniforms */
 186         cl_u8(&shader_rec, vc4->prog.vs->vattrs_live);
 187         cl_u8(&shader_rec, vc4->prog.vs->vattr_offsets[8]);
 188         cl_reloc(vc4, &vc4->shader_rec, &shader_rec, vc4->prog.vs->bo, 0);
 189         cl_u32(&shader_rec, 0); /* UBO offset written by kernel */
 190
 191         cl_u16(&shader_rec, 0); /* cs num uniforms */
 192         cl_u8(&shader_rec, vc4->prog.cs->vattrs_live);
 193         cl_u8(&shader_rec, vc4->prog.cs->vattr_offsets[8]);
 194         cl_reloc(vc4, &vc4->shader_rec, &shader_rec, vc4->prog.cs->bo, 0);
 195         cl_u32(&shader_rec, 0); /* UBO offset written by kernel */
 196
 197         uint32_t max_index = 0xffff;
 198         uint32_t vpm_offset = 0;
 199         for (int i = 0; i < vtx->num_elements; i++) {
 200                 struct pipe_vertex_element *elem = &vtx->pipe[i];
 201                 struct pipe_vertex_buffer *vb =
 202                         &vertexbuf->vb[elem->vertex_buffer_index];
 203                 struct vc4_resource *rsc = vc4_resource(vb->buffer);
 204                 uint32_t offset = vb->buffer_offset + elem->src_offset;
 205                 uint32_t vb_size = rsc->bo->size - offset;
 206                 uint32_t elem_size =
 207                         util_format_get_blocksize(elem->src_format);
 208
 209                 cl_reloc(vc4, &vc4->shader_rec, &shader_rec, rsc->bo, offset);
 210                 cl_u8(&shader_rec, elem_size - 1);
 211                 cl_u8(&shader_rec, vb->stride);
 212                 cl_u8(&shader_rec, vc4->prog.vs->vattr_offsets[i]);
 213                 cl_u8(&shader_rec, vc4->prog.cs->vattr_offsets[i]);
 214
 215                 vpm_offset += align(elem_size, 4);
 216
 217                 if (vb->stride > 0) {
 218                         max_index = MIN2(max_index,
 219                                          (vb_size - elem_size) / vb->stride);
 220                 }
 221         }
 222
 223         if (vtx->num_elements == 0) {
 224                 assert(num_elements_emit == 1);
 225                 struct vc4_bo *bo = vc4_bo_alloc(vc4->screen, 4096, "scratch VBO");
 226                 cl_reloc(vc4, &vc4->shader_rec, &shader_rec, bo, 0);
 227                 cl_u8(&shader_rec, 16 - 1); /* element size */
 228                 cl_u8(&shader_rec, 0); /* stride */
 229                 cl_u8(&shader_rec, 0); /* VS VPM offset */
 230                 cl_u8(&shader_rec, 0); /* CS VPM offset */
 231                 vc4_bo_unreference(&bo);
 232         }
 233         cl_end(&vc4->shader_rec, shader_rec);
 234
 235         struct vc4_cl_out *bcl = cl_start(&vc4->bcl);
 236         /* the actual draw call. */
 237         cl_u8(&bcl, VC4_PACKET_GL_SHADER_STATE);
 238         assert(vtx->num_elements <= 8);
 239         /* Note that number of attributes == 0 in the packet means 8
 240          * attributes.  This field also contains the offset into shader_rec.
 241          */
 242         cl_u32(&bcl, num_elements_emit & 0x7);
 243
 244         /* Note that the primitive type fields match with OpenGL/gallium
 245          * definitions, up to but not including QUADS.
 246          */
 247         if (info->indexed) {
 248                 uint32_t offset = vc4->indexbuf.offset;
 249                 uint32_t index_size = vc4->indexbuf.index_size;
 250                 struct pipe_resource *prsc;
 251                 if (vc4->indexbuf.index_size == 4) {
 252                         prsc = vc4_get_shadow_index_buffer(pctx, &vc4->indexbuf,
 253                                                            info->count, &offset);
 254                         index_size = 2;
 255                 } else {
 256                         prsc = vc4->indexbuf.buffer;
 257                 }
 258                 struct vc4_resource *rsc = vc4_resource(prsc);
 259
 260                 cl_start_reloc(&vc4->bcl, &bcl, 1);
 261                 cl_u8(&bcl, VC4_PACKET_GL_INDEXED_PRIMITIVE);
 262                 cl_u8(&bcl,
 263                       info->mode |
 264                       (index_size == 2 ?
 265                        VC4_INDEX_BUFFER_U16:
 266                        VC4_INDEX_BUFFER_U8));
 267                 cl_u32(&bcl, info->count);
 268                 cl_reloc(vc4, &vc4->bcl, &bcl, rsc->bo, offset);
 269                 cl_u32(&bcl, max_index);
 270
 271                 if (vc4->indexbuf.index_size == 4)
 272                         pipe_resource_reference(&prsc, NULL);
 273         } else {
 274                 cl_u8(&bcl, VC4_PACKET_GL_ARRAY_PRIMITIVE);
 275                 cl_u8(&bcl, info->mode);
 276                 cl_u32(&bcl, info->count);
 277                 cl_u32(&bcl, info->start);
 278         }
 279         cl_end(&vc4->bcl, bcl);
 280
 281         if (vc4->zsa && vc4->zsa->base.depth.enabled) {
 282                 vc4->resolve |= PIPE_CLEAR_DEPTH;
 283         }
 284         if (vc4->zsa && vc4->zsa->base.stencil[0].enabled)
 285                 vc4->resolve |= PIPE_CLEAR_STENCIL;
 286         vc4->resolve |= PIPE_CLEAR_COLOR0;
 287
 288         vc4->shader_rec_count++;
 289
 290         if (vc4_debug & VC4_DEBUG_ALWAYS_FLUSH)
 291                 vc4_flush(pctx);
 292 }
 293
 294 static uint32_t
 295 pack_rgba(enum pipe_format format, const float *rgba)
 296 {
 297         union util_color uc;
 298         util_pack_color(rgba, format, &uc);
 299         if (util_format_get_blocksize(format) == 2)
 300                 return uc.us;
 301         else
 302                 return uc.ui[0];
 303 }
 304
 305 static void
 306 vc4_clear(struct pipe_context *pctx, unsigned buffers,
 307           const union pipe_color_union *color, double depth, unsigned stencil)
 308 {
 309         struct vc4_context *vc4 = vc4_context(pctx);
 310
 311         /* We can't flag new buffers for clearing once we've queued draws.  We
 312          * could avoid this by using the 3d engine to clear.
 313          */
 314         if (vc4->draw_call_queued) {
 315                 perf_debug("Flushing rendering to process new clear.");
 316                 vc4_flush(pctx);
 317         }
 318
 319         if (buffers & PIPE_CLEAR_COLOR0) {
 320                 vc4->clear_color[0] = vc4->clear_color[1] =
 321                         pack_rgba(vc4->framebuffer.cbufs[0]->format,
 322                                   color->f);
 323         }
 324
 325         if (buffers & PIPE_CLEAR_DEPTH) {
 326                 /* Though the depth buffer is stored with Z in the high 24,
 327                  * for this field we just need to store it in the low 24.
 328                  */
 329                 vc4->clear_depth = util_pack_z(PIPE_FORMAT_Z24X8_UNORM, depth);
 330         }
 331
 332         if (buffers & PIPE_CLEAR_STENCIL)
 333                 vc4->clear_stencil = stencil;
 334
 335         vc4->draw_min_x = 0;
 336         vc4->draw_min_y = 0;
 337         vc4->draw_max_x = vc4->framebuffer.width;
 338         vc4->draw_max_y = vc4->framebuffer.height;
 339         vc4->cleared |= buffers;
 340         vc4->resolve |= buffers;
 341
 342         vc4_start_draw(vc4);
 343 }
 344
 345 static void
 346 vc4_clear_render_target(struct pipe_context *pctx, struct pipe_surface *ps,
 347                         const union pipe_color_union *color,
 348                         unsigned x, unsigned y, unsigned w, unsigned h)
 349 {
 350         fprintf(stderr, "unimpl: clear RT\n");
 351 }
 352
 353 static void
 354 vc4_clear_depth_stencil(struct pipe_context *pctx, struct pipe_surface *ps,
 355                         unsigned buffers, double depth, unsigned stencil,
 356                         unsigned x, unsigned y, unsigned w, unsigned h)
 357 {
 358         fprintf(stderr, "unimpl: clear DS\n");
 359 }
 360
 361 void
 362 vc4_draw_init(struct pipe_context *pctx)
 363 {
 364         pctx->draw_vbo = vc4_draw_vbo;
 365         pctx->clear = vc4_clear;
 366         pctx->clear_render_target = vc4_clear_render_target;
 367         pctx->clear_depth_stencil = vc4_clear_depth_stencil;
 368 }