src/gallium/drivers/vc4/vc4_draw.c

   1 /*
   2  * Copyright (c) 2014 Scott Mansell
   3  * Copyright © 2014 Broadcom
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #include "util/u_format.h"
  26 #include "util/u_pack_color.h"
  27 #include "indices/u_primconvert.h"
  28
  29 #include "vc4_context.h"
  30 #include "vc4_resource.h"
  31
  32 /**
  33  * Does the initial bining command list setup for drawing to a given FBO.
  34  */
  35 static void
  36 vc4_start_draw(struct vc4_context *vc4)
  37 {
  38         if (vc4->needs_flush)
  39                 return;
  40
  41         uint32_t width = vc4->framebuffer.width;
  42         uint32_t height = vc4->framebuffer.height;
  43         uint32_t tilew = align(width, 64) / 64;
  44         uint32_t tileh = align(height, 64) / 64;
  45
  46         /* Tile alloc memory setup: We use an initial alloc size of 32b.  The
  47          * hardware then aligns that to 256b (we use 4096, because all of our
  48          * BO allocations align to that anyway), then for some reason the
  49          * simulator wants an extra page available, even if you have overflow
  50          * memory set up.
  51          */
  52         uint32_t tile_alloc_size = 32 * tilew * tileh;
  53         tile_alloc_size = align(tile_alloc_size, 4096);
  54         tile_alloc_size += 4096;
  55         uint32_t tile_state_size = 48 * tilew * tileh;
  56         if (!vc4->tile_alloc || vc4->tile_alloc->size < tile_alloc_size) {
  57                 vc4_bo_unreference(&vc4->tile_alloc);
  58                 vc4->tile_alloc = vc4_bo_alloc(vc4->screen, tile_alloc_size,
  59                                                "tile_alloc");
  60         }
  61         if (!vc4->tile_state || vc4->tile_state->size < tile_state_size) {
  62                 vc4_bo_unreference(&vc4->tile_state);
  63                 vc4->tile_state = vc4_bo_alloc(vc4->screen, tile_state_size,
  64                                                "tile_state");
  65         }
  66
  67         //   Tile state data is 48 bytes per tile, I think it can be thrown away
  68         //   as soon as binning is finished.
  69         cl_start_reloc(&vc4->bcl, 2);
  70         cl_u8(&vc4->bcl, VC4_PACKET_TILE_BINNING_MODE_CONFIG);
  71         cl_reloc(vc4, &vc4->bcl, vc4->tile_alloc, 0);
  72         cl_u32(&vc4->bcl, vc4->tile_alloc->size);
  73         cl_reloc(vc4, &vc4->bcl, vc4->tile_state, 0);
  74         cl_u8(&vc4->bcl, tilew);
  75         cl_u8(&vc4->bcl, tileh);
  76         cl_u8(&vc4->bcl,
  77               VC4_BIN_CONFIG_AUTO_INIT_TSDA |
  78               VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_32 |
  79               VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_32);
  80
  81         cl_u8(&vc4->bcl, VC4_PACKET_START_TILE_BINNING);
  82
  83         vc4->needs_flush = true;
  84         vc4->draw_call_queued = true;
  85 }
  86
  87 static void
  88 vc4_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
  89 {
  90         struct vc4_context *vc4 = vc4_context(pctx);
  91
  92         if (info->mode >= PIPE_PRIM_QUADS) {
  93                 util_primconvert_save_index_buffer(vc4->primconvert, &vc4->indexbuf);
  94                 util_primconvert_save_rasterizer_state(vc4->primconvert, &vc4->rasterizer->base);
  95                 util_primconvert_draw_vbo(vc4->primconvert, info);
  96                 return;
  97         }
  98
  99         vc4_start_draw(vc4);
 100         vc4_update_compiled_shaders(vc4, info->mode);
 101
 102         vc4_emit_state(pctx);
 103
 104         /* the actual draw call. */
 105         struct vc4_vertex_stateobj *vtx = vc4->vtx;
 106         struct vc4_vertexbuf_stateobj *vertexbuf = &vc4->vertexbuf;
 107         cl_u8(&vc4->bcl, VC4_PACKET_GL_SHADER_STATE);
 108         assert(vtx->num_elements <= 8);
 109         /* Note that number of attributes == 0 in the packet means 8
 110          * attributes.  This field also contains the offset into shader_rec.
 111          */
 112         cl_u32(&vc4->bcl, vtx->num_elements & 0x7);
 113
 114         /* Note that the primitive type fields match with OpenGL/gallium
 115          * definitions, up to but not including QUADS.
 116          */
 117         if (info->indexed) {
 118                 struct vc4_resource *rsc = vc4_resource(vc4->indexbuf.buffer);
 119
 120                 assert(vc4->indexbuf.index_size == 1 ||
 121                        vc4->indexbuf.index_size == 2);
 122
 123                 cl_start_reloc(&vc4->bcl, 1);
 124                 cl_u8(&vc4->bcl, VC4_PACKET_GL_INDEXED_PRIMITIVE);
 125                 cl_u8(&vc4->bcl,
 126                       info->mode |
 127                       (vc4->indexbuf.index_size == 2 ?
 128                        VC4_INDEX_BUFFER_U16:
 129                        VC4_INDEX_BUFFER_U8));
 130                 cl_u32(&vc4->bcl, info->count);
 131                 cl_reloc(vc4, &vc4->bcl, rsc->bo, vc4->indexbuf.offset);
 132                 cl_u32(&vc4->bcl, info->max_index);
 133         } else {
 134                 cl_u8(&vc4->bcl, VC4_PACKET_GL_ARRAY_PRIMITIVE);
 135                 cl_u8(&vc4->bcl, info->mode);
 136                 cl_u32(&vc4->bcl, info->count);
 137                 cl_u32(&vc4->bcl, info->start);
 138         }
 139
 140 // Shader Record
 141
 142         vc4_write_uniforms(vc4, vc4->prog.fs,
 143                            &vc4->constbuf[PIPE_SHADER_FRAGMENT],
 144                            &vc4->fragtex,
 145                            0);
 146         vc4_write_uniforms(vc4, vc4->prog.vs,
 147                            &vc4->constbuf[PIPE_SHADER_VERTEX],
 148                            &vc4->verttex,
 149                            0);
 150         vc4_write_uniforms(vc4, vc4->prog.vs,
 151                            &vc4->constbuf[PIPE_SHADER_VERTEX],
 152                            &vc4->verttex,
 153                            1);
 154
 155         cl_start_shader_reloc(&vc4->shader_rec, 3 + vtx->num_elements);
 156         cl_u16(&vc4->shader_rec, VC4_SHADER_FLAG_ENABLE_CLIPPING);
 157         cl_u8(&vc4->shader_rec, 0); /* fs num uniforms (unused) */
 158         cl_u8(&vc4->shader_rec, vc4->prog.fs->num_inputs);
 159         cl_reloc(vc4, &vc4->shader_rec, vc4->prog.fs->bo, 0);
 160         cl_u32(&vc4->shader_rec, 0); /* UBO offset written by kernel */
 161
 162         cl_u16(&vc4->shader_rec, 0); /* vs num uniforms */
 163         cl_u8(&vc4->shader_rec, (1 << vtx->num_elements) - 1); /* vs attribute array bitfield */
 164         cl_u8(&vc4->shader_rec, 16 * vtx->num_elements); /* vs total attribute size */
 165         cl_reloc(vc4, &vc4->shader_rec, vc4->prog.vs->bo, 0);
 166         cl_u32(&vc4->shader_rec, 0); /* UBO offset written by kernel */
 167
 168         cl_u16(&vc4->shader_rec, 0); /* cs num uniforms */
 169         cl_u8(&vc4->shader_rec, (1 << vtx->num_elements) - 1); /* cs attribute array bitfield */
 170         cl_u8(&vc4->shader_rec, 16 * vtx->num_elements); /* vs total attribute size */
 171         cl_reloc(vc4, &vc4->shader_rec, vc4->prog.vs->bo,
 172                 vc4->prog.vs->coord_shader_offset);
 173         cl_u32(&vc4->shader_rec, 0); /* UBO offset written by kernel */
 174
 175         for (int i = 0; i < vtx->num_elements; i++) {
 176                 struct pipe_vertex_element *elem = &vtx->pipe[i];
 177                 struct pipe_vertex_buffer *vb =
 178                         &vertexbuf->vb[elem->vertex_buffer_index];
 179                 struct vc4_resource *rsc = vc4_resource(vb->buffer);
 180
 181                 cl_reloc(vc4, &vc4->shader_rec, rsc->bo,
 182                          vb->buffer_offset + elem->src_offset);
 183                 cl_u8(&vc4->shader_rec,
 184                       util_format_get_blocksize(elem->src_format) - 1);
 185                 cl_u8(&vc4->shader_rec, vb->stride);
 186                 cl_u8(&vc4->shader_rec, i * 16); /* VS VPM offset */
 187                 cl_u8(&vc4->shader_rec, i * 16); /* CS VPM offset */
 188         }
 189
 190         if (vc4->zsa && vc4->zsa->base.depth.enabled) {
 191                 vc4->resolve |= PIPE_CLEAR_DEPTH;
 192         }
 193         vc4->resolve |= PIPE_CLEAR_COLOR0;
 194
 195         vc4->shader_rec_count++;
 196 }
 197
 198 static uint32_t
 199 pack_rgba(enum pipe_format format, const float *rgba)
 200 {
 201         union util_color uc;
 202         util_pack_color(rgba, format, &uc);
 203         return uc.ui[0];
 204 }
 205
 206 static void
 207 vc4_clear(struct pipe_context *pctx, unsigned buffers,
 208           const union pipe_color_union *color, double depth, unsigned stencil)
 209 {
 210         struct vc4_context *vc4 = vc4_context(pctx);
 211
 212         /* We can't flag new buffers for clearing once we've queued draws.  We
 213          * could avoid this by using the 3d engine to clear.
 214          */
 215         if (vc4->draw_call_queued)
 216                 vc4_flush(pctx);
 217
 218         if (buffers & PIPE_CLEAR_COLOR0) {
 219                 vc4->clear_color[0] = vc4->clear_color[1] =
 220                         pack_rgba(vc4->framebuffer.cbufs[0]->format,
 221                                   color->f);
 222         }
 223
 224         if (buffers & PIPE_CLEAR_DEPTH)
 225                 vc4->clear_depth = util_pack_z(PIPE_FORMAT_Z24X8_UNORM, depth);
 226
 227         vc4->cleared |= buffers;
 228         vc4->resolve |= buffers;
 229
 230         vc4_start_draw(vc4);
 231 }
 232
 233 static void
 234 vc4_clear_render_target(struct pipe_context *pctx, struct pipe_surface *ps,
 235                         const union pipe_color_union *color,
 236                         unsigned x, unsigned y, unsigned w, unsigned h)
 237 {
 238         fprintf(stderr, "unimpl: clear RT\n");
 239 }
 240
 241 static void
 242 vc4_clear_depth_stencil(struct pipe_context *pctx, struct pipe_surface *ps,
 243                         unsigned buffers, double depth, unsigned stencil,
 244                         unsigned x, unsigned y, unsigned w, unsigned h)
 245 {
 246         fprintf(stderr, "unimpl: clear DS\n");
 247 }
 248
 249 void
 250 vc4_draw_init(struct pipe_context *pctx)
 251 {
 252         pctx->draw_vbo = vc4_draw_vbo;
 253         pctx->clear = vc4_clear;
 254         pctx->clear_render_target = vc4_clear_render_target;
 255         pctx->clear_depth_stencil = vc4_clear_depth_stencil;
 256 }