2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "util/u_format.h"
26 #include "util/u_pack_color.h"
27 #include "indices/u_primconvert.h"
29 #include "vc4_context.h"
30 #include "vc4_resource.h"
33 * Does the initial bining command list setup for drawing to a given FBO.
36 vc4_start_draw(struct vc4_context
*vc4
)
41 uint32_t width
= vc4
->framebuffer
.width
;
42 uint32_t height
= vc4
->framebuffer
.height
;
43 uint32_t tilew
= align(width
, 64) / 64;
44 uint32_t tileh
= align(height
, 64) / 64;
46 /* Tile alloc memory setup: We use an initial alloc size of 32b. The
47 * hardware then aligns that to 256b (we use 4096, because all of our
48 * BO allocations align to that anyway), then for some reason the
49 * simulator wants an extra page available, even if you have overflow
52 uint32_t tile_alloc_size
= 32 * tilew
* tileh
;
53 tile_alloc_size
= align(tile_alloc_size
, 4096);
54 tile_alloc_size
+= 4096;
55 uint32_t tile_state_size
= 48 * tilew
* tileh
;
56 if (!vc4
->tile_alloc
|| vc4
->tile_alloc
->size
< tile_alloc_size
) {
57 vc4_bo_unreference(&vc4
->tile_alloc
);
58 vc4
->tile_alloc
= vc4_bo_alloc(vc4
->screen
, tile_alloc_size
,
61 if (!vc4
->tile_state
|| vc4
->tile_state
->size
< tile_state_size
) {
62 vc4_bo_unreference(&vc4
->tile_state
);
63 vc4
->tile_state
= vc4_bo_alloc(vc4
->screen
, tile_state_size
,
67 // Tile state data is 48 bytes per tile, I think it can be thrown away
68 // as soon as binning is finished.
69 cl_start_reloc(&vc4
->bcl
, 2);
70 cl_u8(&vc4
->bcl
, VC4_PACKET_TILE_BINNING_MODE_CONFIG
);
71 cl_reloc(vc4
, &vc4
->bcl
, vc4
->tile_alloc
, 0);
72 cl_u32(&vc4
->bcl
, vc4
->tile_alloc
->size
);
73 cl_reloc(vc4
, &vc4
->bcl
, vc4
->tile_state
, 0);
74 cl_u8(&vc4
->bcl
, tilew
);
75 cl_u8(&vc4
->bcl
, tileh
);
77 VC4_BIN_CONFIG_AUTO_INIT_TSDA
|
78 VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_32
|
79 VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_32
);
81 cl_u8(&vc4
->bcl
, VC4_PACKET_START_TILE_BINNING
);
83 vc4
->needs_flush
= true;
84 vc4
->draw_call_queued
= true;
88 vc4_draw_vbo(struct pipe_context
*pctx
, const struct pipe_draw_info
*info
)
90 struct vc4_context
*vc4
= vc4_context(pctx
);
92 if (info
->mode
>= PIPE_PRIM_QUADS
) {
93 util_primconvert_save_index_buffer(vc4
->primconvert
, &vc4
->indexbuf
);
94 util_primconvert_save_rasterizer_state(vc4
->primconvert
, &vc4
->rasterizer
->base
);
95 util_primconvert_draw_vbo(vc4
->primconvert
, info
);
99 struct vc4_vertex_stateobj
*vtx
= vc4
->vtx
;
100 struct vc4_vertexbuf_stateobj
*vertexbuf
= &vc4
->vertexbuf
;
102 if (vc4
->prim_mode
!= info
->mode
) {
103 vc4
->prim_mode
= info
->mode
;
104 vc4
->dirty
|= VC4_DIRTY_PRIM_MODE
;
108 vc4_update_compiled_shaders(vc4
, info
->mode
);
110 vc4_emit_state(pctx
);
113 vc4_write_uniforms(vc4
, vc4
->prog
.fs
,
114 &vc4
->constbuf
[PIPE_SHADER_FRAGMENT
],
116 vc4_write_uniforms(vc4
, vc4
->prog
.vs
,
117 &vc4
->constbuf
[PIPE_SHADER_VERTEX
],
119 vc4_write_uniforms(vc4
, vc4
->prog
.cs
,
120 &vc4
->constbuf
[PIPE_SHADER_VERTEX
],
123 /* Emit the shader record. */
124 cl_start_shader_reloc(&vc4
->shader_rec
, 3 + vtx
->num_elements
);
125 cl_u16(&vc4
->shader_rec
,
126 VC4_SHADER_FLAG_ENABLE_CLIPPING
|
127 ((info
->mode
== PIPE_PRIM_POINTS
&&
128 vc4
->rasterizer
->base
.point_size_per_vertex
) ?
129 VC4_SHADER_FLAG_VS_POINT_SIZE
: 0));
130 cl_u8(&vc4
->shader_rec
, 0); /* fs num uniforms (unused) */
131 cl_u8(&vc4
->shader_rec
, vc4
->prog
.fs
->num_inputs
);
132 cl_reloc(vc4
, &vc4
->shader_rec
, vc4
->prog
.fs
->bo
, 0);
133 cl_u32(&vc4
->shader_rec
, 0); /* UBO offset written by kernel */
135 cl_u16(&vc4
->shader_rec
, 0); /* vs num uniforms */
136 cl_u8(&vc4
->shader_rec
, (1 << vtx
->num_elements
) - 1); /* vs attribute array bitfield */
137 cl_u8(&vc4
->shader_rec
, 16 * vtx
->num_elements
); /* vs total attribute size */
138 cl_reloc(vc4
, &vc4
->shader_rec
, vc4
->prog
.vs
->bo
, 0);
139 cl_u32(&vc4
->shader_rec
, 0); /* UBO offset written by kernel */
141 cl_u16(&vc4
->shader_rec
, 0); /* cs num uniforms */
142 cl_u8(&vc4
->shader_rec
, (1 << vtx
->num_elements
) - 1); /* cs attribute array bitfield */
143 cl_u8(&vc4
->shader_rec
, 16 * vtx
->num_elements
); /* cs total attribute size */
144 cl_reloc(vc4
, &vc4
->shader_rec
, vc4
->prog
.cs
->bo
, 0);
145 cl_u32(&vc4
->shader_rec
, 0); /* UBO offset written by kernel */
147 uint32_t max_index
= 0xffff;
148 for (int i
= 0; i
< vtx
->num_elements
; i
++) {
149 struct pipe_vertex_element
*elem
= &vtx
->pipe
[i
];
150 struct pipe_vertex_buffer
*vb
=
151 &vertexbuf
->vb
[elem
->vertex_buffer_index
];
152 struct vc4_resource
*rsc
= vc4_resource(vb
->buffer
);
153 uint32_t offset
= vb
->buffer_offset
+ elem
->src_offset
;
154 uint32_t vb_size
= rsc
->bo
->size
- offset
;
156 util_format_get_blocksize(elem
->src_format
);
158 cl_reloc(vc4
, &vc4
->shader_rec
, rsc
->bo
, offset
);
159 cl_u8(&vc4
->shader_rec
, elem_size
- 1);
160 cl_u8(&vc4
->shader_rec
, vb
->stride
);
161 cl_u8(&vc4
->shader_rec
, i
* 16); /* VS VPM offset */
162 cl_u8(&vc4
->shader_rec
, i
* 16); /* CS VPM offset */
164 if (vb
->stride
> 0) {
165 max_index
= MIN2(max_index
,
166 (vb_size
- elem_size
) / vb
->stride
);
170 /* the actual draw call. */
171 cl_u8(&vc4
->bcl
, VC4_PACKET_GL_SHADER_STATE
);
172 assert(vtx
->num_elements
<= 8);
173 /* Note that number of attributes == 0 in the packet means 8
174 * attributes. This field also contains the offset into shader_rec.
176 cl_u32(&vc4
->bcl
, vtx
->num_elements
& 0x7);
178 /* Note that the primitive type fields match with OpenGL/gallium
179 * definitions, up to but not including QUADS.
182 struct vc4_resource
*rsc
= vc4_resource(vc4
->indexbuf
.buffer
);
184 assert(vc4
->indexbuf
.index_size
== 1 ||
185 vc4
->indexbuf
.index_size
== 2);
187 cl_start_reloc(&vc4
->bcl
, 1);
188 cl_u8(&vc4
->bcl
, VC4_PACKET_GL_INDEXED_PRIMITIVE
);
191 (vc4
->indexbuf
.index_size
== 2 ?
192 VC4_INDEX_BUFFER_U16
:
193 VC4_INDEX_BUFFER_U8
));
194 cl_u32(&vc4
->bcl
, info
->count
);
195 cl_reloc(vc4
, &vc4
->bcl
, rsc
->bo
, vc4
->indexbuf
.offset
);
196 cl_u32(&vc4
->bcl
, max_index
);
198 cl_u8(&vc4
->bcl
, VC4_PACKET_GL_ARRAY_PRIMITIVE
);
199 cl_u8(&vc4
->bcl
, info
->mode
);
200 cl_u32(&vc4
->bcl
, info
->count
);
201 cl_u32(&vc4
->bcl
, info
->start
);
204 if (vc4
->zsa
&& vc4
->zsa
->base
.depth
.enabled
) {
205 vc4
->resolve
|= PIPE_CLEAR_DEPTH
;
207 if (vc4
->zsa
&& vc4
->zsa
->base
.stencil
[0].enabled
)
208 vc4
->resolve
|= PIPE_CLEAR_STENCIL
;
209 vc4
->resolve
|= PIPE_CLEAR_COLOR0
;
211 vc4
->shader_rec_count
++;
213 if (vc4_debug
& VC4_DEBUG_ALWAYS_FLUSH
)
218 pack_rgba(enum pipe_format format
, const float *rgba
)
221 util_pack_color(rgba
, format
, &uc
);
226 vc4_clear(struct pipe_context
*pctx
, unsigned buffers
,
227 const union pipe_color_union
*color
, double depth
, unsigned stencil
)
229 struct vc4_context
*vc4
= vc4_context(pctx
);
231 /* We can't flag new buffers for clearing once we've queued draws. We
232 * could avoid this by using the 3d engine to clear.
234 if (vc4
->draw_call_queued
)
237 if (buffers
& PIPE_CLEAR_COLOR0
) {
238 vc4
->clear_color
[0] = vc4
->clear_color
[1] =
239 pack_rgba(vc4
->framebuffer
.cbufs
[0]->format
,
243 if (buffers
& PIPE_CLEAR_DEPTH
) {
244 /* Though the depth buffer is stored with Z in the high 24,
245 * for this field we just need to store it in the low 24.
247 vc4
->clear_depth
= util_pack_z(PIPE_FORMAT_Z24X8_UNORM
, depth
);
250 if (buffers
& PIPE_CLEAR_STENCIL
)
251 vc4
->clear_stencil
= stencil
;
253 vc4
->cleared
|= buffers
;
254 vc4
->resolve
|= buffers
;
260 vc4_clear_render_target(struct pipe_context
*pctx
, struct pipe_surface
*ps
,
261 const union pipe_color_union
*color
,
262 unsigned x
, unsigned y
, unsigned w
, unsigned h
)
264 fprintf(stderr
, "unimpl: clear RT\n");
268 vc4_clear_depth_stencil(struct pipe_context
*pctx
, struct pipe_surface
*ps
,
269 unsigned buffers
, double depth
, unsigned stencil
,
270 unsigned x
, unsigned y
, unsigned w
, unsigned h
)
272 fprintf(stderr
, "unimpl: clear DS\n");
276 vc4_draw_init(struct pipe_context
*pctx
)
278 pctx
->draw_vbo
= vc4_draw_vbo
;
279 pctx
->clear
= vc4_clear
;
280 pctx
->clear_render_target
= vc4_clear_render_target
;
281 pctx
->clear_depth_stencil
= vc4_clear_depth_stencil
;