src/gallium/drivers/vc4/vc4_drm.h

   1 /*
   2  * Copyright © 2014 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef _UAPI_VC4_DRM_H_
  25 #define _UAPI_VC4_DRM_H_
  26
  27 #include <drm.h>
  28
  29 #define DRM_VC4_SUBMIT_CL                         0x00
  30 #define DRM_VC4_WAIT_SEQNO                        0x01
  31 #define DRM_VC4_WAIT_BO                           0x02
  32
  33 #define DRM_IOCTL_VC4_SUBMIT_CL           DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)
  34 #define DRM_IOCTL_VC4_WAIT_SEQNO          DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)
  35 #define DRM_IOCTL_VC4_WAIT_BO             DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo)
  36
  37
  38 /**
  39  * struct drm_vc4_submit_cl - ioctl argument for submitting commands to the 3D
  40  * engine.
  41  *
  42  * Drivers typically use GPU BOs to store batchbuffers / command lists and
  43  * their associated state.  However, because the VC4 lacks an MMU, we have to
  44  * do validation of memory accesses by the GPU commands.  If we were to store
  45  * our commands in BOs, we'd need to do uncached readback from them to do the
  46  * validation process, which is too expensive.  Instead, userspace accumulates
  47  * commands and associated state in plain memory, then the kernel copies the
  48  * data to its own address space, and then validates and stores it in a GPU
  49  * BO.
  50  */
  51 struct drm_vc4_submit_cl {
  52         /* Pointer to the binner command list.
  53          *
  54          * This is the first set of commands executed, which runs the
  55          * coordinate shader to determine where primitives land on the screen,
  56          * then writes out the state updates and draw calls necessary per tile
  57          * to the tile allocation BO.
  58          */
  59         void __user *bin_cl;
  60
  61         /* Pointer to the render command list.
  62          *
  63          * The render command list contains a set of packets to load the
  64          * current tile's state (reading from memory, or just clearing it)
  65          * into the GPU, then call into the tile allocation BO to run the
  66          * stored rendering for that tile, then store the tile's state back to
  67          * memory.
  68          */
  69         void __user *render_cl;
  70
  71         /* Pointer to the shader records.
  72          *
  73          * Shader records are the structures read by the hardware that contain
  74          * pointers to uniforms, shaders, and vertex attributes.  The
  75          * reference to the shader record has enough information to determine
  76          * how many pointers are necessary (fixed number for shaders/uniforms,
  77          * and an attribute count), so those BO indices into bo_handles are
  78          * just stored as uint32_ts before each shader record passed in.
  79          */
  80         void __user *shader_rec;
  81
  82         /* Pointer to uniform data and texture handles for the textures
  83          * referenced by the shader.
  84          *
  85          * For each shader state record, there is a set of uniform data in the
  86          * order referenced by the record (FS, VS, then CS).  Each set of
  87          * uniform data has a uint32_t index into bo_handles per texture
  88          * sample operation, in the order the QPU_W_TMUn_S writes appear in
  89          * the program.  Following the texture BO handle indices is the actual
  90          * uniform data.
  91          *
  92          * The individual uniform state blocks don't have sizes passed in,
  93          * because the kernel has to determine the sizes anyway during shader
  94          * code validation.
  95          */
  96         void __user *uniforms;
  97         void __user *bo_handles;
  98
  99         /* Size in bytes of the binner command list. */
 100         uint32_t bin_cl_size;
 101         /* Size in bytes of the render command list */
 102         uint32_t render_cl_size;
 103         /* Size in bytes of the set of shader records. */
 104         uint32_t shader_rec_size;
 105         /* Number of shader records.
 106          *
 107          * This could just be computed from the contents of shader_records and
 108          * the address bits of references to them from the bin CL, but it
 109          * keeps the kernel from having to resize some allocations it makes.
 110          */
 111         uint32_t shader_rec_count;
 112         /* Size in bytes of the uniform state. */
 113         uint32_t uniforms_size;
 114
 115         /* Number of BO handles passed in (size is that times 4). */
 116         uint32_t bo_handle_count;
 117
 118         uint32_t pad;
 119
 120         /* Returned value of the seqno of this render job (for the
 121          * wait ioctl).
 122          */
 123         uint64_t seqno;
 124 };
 125
 126 /**
 127  * struct drm_vc4_wait_seqno - ioctl argument for waiting for
 128  * DRM_VC4_SUBMIT_CL completion using its returned seqno.
 129  *
 130  * timeout_ns is the timeout in nanoseconds, where "0" means "don't
 131  * block, just return the status."
 132  */
 133 struct drm_vc4_wait_seqno {
 134         uint64_t seqno;
 135         uint64_t timeout_ns;
 136 };
 137
 138 /**
 139  * struct drm_vc4_wait_bo - ioctl argument for waiting for
 140  * completion of the last DRM_VC4_SUBMIT_CL on a BO.
 141  *
 142  * This is useful for cases where multiple processes might be
 143  * rendering to a BO and you want to wait for all rendering to be
 144  * completed.
 145  */
 146 struct drm_vc4_wait_bo {
 147         uint32_t handle;
 148         uint32_t pad;
 149         uint64_t timeout_ns;
 150 };
 151
 152 #endif /* _UAPI_VC4_DRM_H_ */