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24 #ifndef _UAPI_VC4_DRM_H_
25 #define _UAPI_VC4_DRM_H_
29 #define DRM_VC4_SUBMIT_CL 0x00
31 #define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)
34 * struct drm_vc4_submit_cl - ioctl argument for submitting commands to the 3D
37 * Drivers typically use GPU BOs to store batchbuffers / command lists and
38 * their associated state. However, because the VC4 lacks an MMU, we have to
39 * do validation of memory accesses by the GPU commands. If we were to store
40 * our commands in BOs, we'd need to do uncached readback from them to do the
41 * validation process, which is too expensive. Instead, userspace accumulates
42 * commands and associated state in plain memory, then the kernel copies the
43 * data to its own address space, and then validates and stores it in a GPU
46 struct drm_vc4_submit_cl
{
47 /* Pointer to the binner command list.
49 * This is the first set of commands executed, which runs the
50 * coordinate shader to determine where primitives land on the screen,
51 * then writes out the state updates and draw calls necessary per tile
52 * to the tile allocation BO.
56 /* Pointer to the render command list.
58 * The render command list contains a set of packets to load the
59 * current tile's state (reading from memory, or just clearing it)
60 * into the GPU, then call into the tile allocation BO to run the
61 * stored rendering for that tile, then store the tile's state back to
64 void __user
*render_cl
;
66 /* Pointer to the shader records.
68 * Shader records are the structures read by the hardware that contain
69 * pointers to uniforms, shaders, and vertex attributes. The
70 * reference to the shader record has enough information to determine
71 * how many pointers are necessary (fixed number for shaders/uniforms,
72 * and an attribute count), so those BO indices into bo_handles are
73 * just stored as uint32_ts before each shader record passed in.
75 void __user
*shader_rec
;
77 /* Pointer to uniform data and texture handles for the textures
78 * referenced by the shader.
80 * For each shader state record, there is a set of uniform data in the
81 * order referenced by the record (FS, VS, then CS). Each set of
82 * uniform data has a uint32_t index into bo_handles per texture
83 * sample operation, in the order the QPU_W_TMUn_S writes appear in
84 * the program. Following the texture BO handle indices is the actual
87 * The individual uniform state blocks don't have sizes passed in,
88 * because the kernel has to determine the sizes anyway during shader
91 void __user
*uniforms
;
92 void __user
*bo_handles
;
94 /* Size in bytes of the binner command list. */
96 /* Size in bytes of the render command list */
97 uint32_t render_cl_size
;
98 /* Size in bytes of the set of shader records. */
99 uint32_t shader_rec_size
;
100 /* Number of shader records.
102 * This could just be computed from the contents of shader_records and
103 * the address bits of references to them from the bin CL, but it
104 * keeps the kernel from having to resize some allocations it makes.
106 uint32_t shader_rec_count
;
107 /* Size in bytes of the uniform state. */
108 uint32_t uniforms_size
;
110 /* Number of BO handles passed in (size is that times 4). */
111 uint32_t bo_handle_count
;
114 #endif /* _UAPI_VC4_DRM_H_ */