src/gallium/drivers/vc4/vc4_drm.h

   1 /*
   2  * Copyright © 2014-2015 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef _UAPI_VC4_DRM_H_
  25 #define _UAPI_VC4_DRM_H_
  26
  27 #include <drm.h>
  28
  29 #define DRM_VC4_SUBMIT_CL                         0x00
  30 #define DRM_VC4_WAIT_SEQNO                        0x01
  31 #define DRM_VC4_WAIT_BO                           0x02
  32 #define DRM_VC4_CREATE_BO                         0x03
  33 #define DRM_VC4_MMAP_BO                           0x04
  34
  35 #define DRM_IOCTL_VC4_SUBMIT_CL           DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)
  36 #define DRM_IOCTL_VC4_WAIT_SEQNO          DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)
  37 #define DRM_IOCTL_VC4_WAIT_BO             DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo)
  38 #define DRM_IOCTL_VC4_CREATE_BO           DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo)
  39 #define DRM_IOCTL_VC4_MMAP_BO             DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo)
  40
  41 struct drm_vc4_submit_rcl_surface {
  42         uint32_t hindex; /* Handle index, or ~0 if not present. */
  43         uint32_t offset; /* Offset to start of buffer. */
  44         /*
  45          * Bits for either render config (color_ms_write) or load/store packet.
  46          */
  47         uint16_t bits;
  48         uint16_t pad;
  49 };
  50
  51 /**
  52  * struct drm_vc4_submit_cl - ioctl argument for submitting commands to the 3D
  53  * engine.
  54  *
  55  * Drivers typically use GPU BOs to store batchbuffers / command lists and
  56  * their associated state.  However, because the VC4 lacks an MMU, we have to
  57  * do validation of memory accesses by the GPU commands.  If we were to store
  58  * our commands in BOs, we'd need to do uncached readback from them to do the
  59  * validation process, which is too expensive.  Instead, userspace accumulates
  60  * commands and associated state in plain memory, then the kernel copies the
  61  * data to its own address space, and then validates and stores it in a GPU
  62  * BO.
  63  */
  64 struct drm_vc4_submit_cl {
  65         /* Pointer to the binner command list.
  66          *
  67          * This is the first set of commands executed, which runs the
  68          * coordinate shader to determine where primitives land on the screen,
  69          * then writes out the state updates and draw calls necessary per tile
  70          * to the tile allocation BO.
  71          */
  72         uint64_t bin_cl;
  73
  74         /* Pointer to the shader records.
  75          *
  76          * Shader records are the structures read by the hardware that contain
  77          * pointers to uniforms, shaders, and vertex attributes.  The
  78          * reference to the shader record has enough information to determine
  79          * how many pointers are necessary (fixed number for shaders/uniforms,
  80          * and an attribute count), so those BO indices into bo_handles are
  81          * just stored as uint32_ts before each shader record passed in.
  82          */
  83         uint64_t shader_rec;
  84
  85         /* Pointer to uniform data and texture handles for the textures
  86          * referenced by the shader.
  87          *
  88          * For each shader state record, there is a set of uniform data in the
  89          * order referenced by the record (FS, VS, then CS).  Each set of
  90          * uniform data has a uint32_t index into bo_handles per texture
  91          * sample operation, in the order the QPU_W_TMUn_S writes appear in
  92          * the program.  Following the texture BO handle indices is the actual
  93          * uniform data.
  94          *
  95          * The individual uniform state blocks don't have sizes passed in,
  96          * because the kernel has to determine the sizes anyway during shader
  97          * code validation.
  98          */
  99         uint64_t uniforms;
 100         uint64_t bo_handles;
 101
 102         /* Size in bytes of the binner command list. */
 103         uint32_t bin_cl_size;
 104         /* Size in bytes of the set of shader records. */
 105         uint32_t shader_rec_size;
 106         /* Number of shader records.
 107          *
 108          * This could just be computed from the contents of shader_records and
 109          * the address bits of references to them from the bin CL, but it
 110          * keeps the kernel from having to resize some allocations it makes.
 111          */
 112         uint32_t shader_rec_count;
 113         /* Size in bytes of the uniform state. */
 114         uint32_t uniforms_size;
 115
 116         /* Number of BO handles passed in (size is that times 4). */
 117         uint32_t bo_handle_count;
 118
 119         /* RCL setup: */
 120         uint16_t width;
 121         uint16_t height;
 122         uint8_t min_x_tile;
 123         uint8_t min_y_tile;
 124         uint8_t max_x_tile;
 125         uint8_t max_y_tile;
 126         struct drm_vc4_submit_rcl_surface color_read;
 127         struct drm_vc4_submit_rcl_surface color_ms_write;
 128         struct drm_vc4_submit_rcl_surface zs_read;
 129         struct drm_vc4_submit_rcl_surface zs_write;
 130         uint32_t clear_color[2];
 131         uint32_t clear_z;
 132         uint8_t clear_s;
 133
 134         uint32_t pad:24;
 135
 136 #define VC4_SUBMIT_CL_USE_CLEAR_COLOR                   (1 << 0)
 137         uint32_t flags;
 138
 139         /* Returned value of the seqno of this render job (for the
 140          * wait ioctl).
 141          */
 142         uint64_t seqno;
 143 };
 144
 145 /**
 146  * struct drm_vc4_wait_seqno - ioctl argument for waiting for
 147  * DRM_VC4_SUBMIT_CL completion using its returned seqno.
 148  *
 149  * timeout_ns is the timeout in nanoseconds, where "0" means "don't
 150  * block, just return the status."
 151  */
 152 struct drm_vc4_wait_seqno {
 153         uint64_t seqno;
 154         uint64_t timeout_ns;
 155 };
 156
 157 /**
 158  * struct drm_vc4_wait_bo - ioctl argument for waiting for
 159  * completion of the last DRM_VC4_SUBMIT_CL on a BO.
 160  *
 161  * This is useful for cases where multiple processes might be
 162  * rendering to a BO and you want to wait for all rendering to be
 163  * completed.
 164  */
 165 struct drm_vc4_wait_bo {
 166         uint32_t handle;
 167         uint32_t pad;
 168         uint64_t timeout_ns;
 169 };
 170
 171 /**
 172  * struct drm_vc4_create_bo - ioctl argument for creating VC4 BOs.
 173  *
 174  * There are currently no values for the flags argument, but it may be
 175  * used in a future extension.
 176  */
 177 struct drm_vc4_create_bo {
 178         uint32_t size;
 179         uint32_t flags;
 180         /** Returned GEM handle for the BO. */
 181         uint32_t handle;
 182         uint32_t pad;
 183 };
 184
 185 /**
 186  * struct drm_vc4_mmap_bo - ioctl argument for mapping VC4 BOs.
 187  *
 188  * This doesn't actually perform an mmap.  Instead, it returns the
 189  * offset you need to use in an mmap on the DRM device node.  This
 190  * means that tools like valgrind end up knowing about the mapped
 191  * memory.
 192  *
 193  * There are currently no values for the flags argument, but it may be
 194  * used in a future extension.
 195  */
 196 struct drm_vc4_mmap_bo {
 197         /** Handle for the object being mapped. */
 198         uint32_t handle;
 199         uint32_t flags;
 200         /** offset into the drm node to use for subsequent mmap call. */
 201         uint64_t offset;
 202 };
 203
 204 #endif /* _UAPI_VC4_DRM_H_ */