src/gallium/drivers/vc4/vc4_drm.h

   1 /*
   2  * Copyright © 2014-2015 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef _UAPI_VC4_DRM_H_
  25 #define _UAPI_VC4_DRM_H_
  26
  27 #include <drm.h>
  28
  29 #define DRM_VC4_SUBMIT_CL                         0x00
  30 #define DRM_VC4_WAIT_SEQNO                        0x01
  31 #define DRM_VC4_WAIT_BO                           0x02
  32 #define DRM_VC4_CREATE_BO                         0x03
  33 #define DRM_VC4_MMAP_BO                           0x04
  34 #define DRM_VC4_CREATE_SHADER_BO                  0x05
  35
  36 #define DRM_IOCTL_VC4_SUBMIT_CL           DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)
  37 #define DRM_IOCTL_VC4_WAIT_SEQNO          DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)
  38 #define DRM_IOCTL_VC4_WAIT_BO             DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo)
  39 #define DRM_IOCTL_VC4_CREATE_BO           DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo)
  40 #define DRM_IOCTL_VC4_MMAP_BO             DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo)
  41 #define DRM_IOCTL_VC4_CREATE_SHADER_BO    DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo)
  42
  43 struct drm_vc4_submit_rcl_surface {
  44         uint32_t hindex; /* Handle index, or ~0 if not present. */
  45         uint32_t offset; /* Offset to start of buffer. */
  46         /*
  47          * Bits for either render config (color_write) or load/store packet.
  48          * Bits should all be 0 for MSAA load/stores.
  49          */
  50         uint16_t bits;
  51
  52 #define VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES         (1 << 0)
  53         uint16_t flags;
  54 };
  55
  56 /**
  57  * struct drm_vc4_submit_cl - ioctl argument for submitting commands to the 3D
  58  * engine.
  59  *
  60  * Drivers typically use GPU BOs to store batchbuffers / command lists and
  61  * their associated state.  However, because the VC4 lacks an MMU, we have to
  62  * do validation of memory accesses by the GPU commands.  If we were to store
  63  * our commands in BOs, we'd need to do uncached readback from them to do the
  64  * validation process, which is too expensive.  Instead, userspace accumulates
  65  * commands and associated state in plain memory, then the kernel copies the
  66  * data to its own address space, and then validates and stores it in a GPU
  67  * BO.
  68  */
  69 struct drm_vc4_submit_cl {
  70         /* Pointer to the binner command list.
  71          *
  72          * This is the first set of commands executed, which runs the
  73          * coordinate shader to determine where primitives land on the screen,
  74          * then writes out the state updates and draw calls necessary per tile
  75          * to the tile allocation BO.
  76          */
  77         uint64_t bin_cl;
  78
  79         /* Pointer to the shader records.
  80          *
  81          * Shader records are the structures read by the hardware that contain
  82          * pointers to uniforms, shaders, and vertex attributes.  The
  83          * reference to the shader record has enough information to determine
  84          * how many pointers are necessary (fixed number for shaders/uniforms,
  85          * and an attribute count), so those BO indices into bo_handles are
  86          * just stored as uint32_ts before each shader record passed in.
  87          */
  88         uint64_t shader_rec;
  89
  90         /* Pointer to uniform data and texture handles for the textures
  91          * referenced by the shader.
  92          *
  93          * For each shader state record, there is a set of uniform data in the
  94          * order referenced by the record (FS, VS, then CS).  Each set of
  95          * uniform data has a uint32_t index into bo_handles per texture
  96          * sample operation, in the order the QPU_W_TMUn_S writes appear in
  97          * the program.  Following the texture BO handle indices is the actual
  98          * uniform data.
  99          *
 100          * The individual uniform state blocks don't have sizes passed in,
 101          * because the kernel has to determine the sizes anyway during shader
 102          * code validation.
 103          */
 104         uint64_t uniforms;
 105         uint64_t bo_handles;
 106
 107         /* Size in bytes of the binner command list. */
 108         uint32_t bin_cl_size;
 109         /* Size in bytes of the set of shader records. */
 110         uint32_t shader_rec_size;
 111         /* Number of shader records.
 112          *
 113          * This could just be computed from the contents of shader_records and
 114          * the address bits of references to them from the bin CL, but it
 115          * keeps the kernel from having to resize some allocations it makes.
 116          */
 117         uint32_t shader_rec_count;
 118         /* Size in bytes of the uniform state. */
 119         uint32_t uniforms_size;
 120
 121         /* Number of BO handles passed in (size is that times 4). */
 122         uint32_t bo_handle_count;
 123
 124         /* RCL setup: */
 125         uint16_t width;
 126         uint16_t height;
 127         uint8_t min_x_tile;
 128         uint8_t min_y_tile;
 129         uint8_t max_x_tile;
 130         uint8_t max_y_tile;
 131         struct drm_vc4_submit_rcl_surface color_read;
 132         struct drm_vc4_submit_rcl_surface color_write;
 133         struct drm_vc4_submit_rcl_surface zs_read;
 134         struct drm_vc4_submit_rcl_surface zs_write;
 135         struct drm_vc4_submit_rcl_surface msaa_color_write;
 136         struct drm_vc4_submit_rcl_surface msaa_zs_write;
 137         uint32_t clear_color[2];
 138         uint32_t clear_z;
 139         uint8_t clear_s;
 140
 141         uint32_t pad:24;
 142
 143 #define VC4_SUBMIT_CL_USE_CLEAR_COLOR                   (1 << 0)
 144         uint32_t flags;
 145
 146         /* Returned value of the seqno of this render job (for the
 147          * wait ioctl).
 148          */
 149         uint64_t seqno;
 150 };
 151
 152 /**
 153  * struct drm_vc4_wait_seqno - ioctl argument for waiting for
 154  * DRM_VC4_SUBMIT_CL completion using its returned seqno.
 155  *
 156  * timeout_ns is the timeout in nanoseconds, where "0" means "don't
 157  * block, just return the status."
 158  */
 159 struct drm_vc4_wait_seqno {
 160         uint64_t seqno;
 161         uint64_t timeout_ns;
 162 };
 163
 164 /**
 165  * struct drm_vc4_wait_bo - ioctl argument for waiting for
 166  * completion of the last DRM_VC4_SUBMIT_CL on a BO.
 167  *
 168  * This is useful for cases where multiple processes might be
 169  * rendering to a BO and you want to wait for all rendering to be
 170  * completed.
 171  */
 172 struct drm_vc4_wait_bo {
 173         uint32_t handle;
 174         uint32_t pad;
 175         uint64_t timeout_ns;
 176 };
 177
 178 /**
 179  * struct drm_vc4_create_bo - ioctl argument for creating VC4 BOs.
 180  *
 181  * There are currently no values for the flags argument, but it may be
 182  * used in a future extension.
 183  */
 184 struct drm_vc4_create_bo {
 185         uint32_t size;
 186         uint32_t flags;
 187         /** Returned GEM handle for the BO. */
 188         uint32_t handle;
 189         uint32_t pad;
 190 };
 191
 192 /**
 193  * struct drm_vc4_create_shader_bo - ioctl argument for creating VC4
 194  * shader BOs.
 195  *
 196  * Since allowing a shader to be overwritten while it's also being
 197  * executed from would allow privlege escalation, shaders must be
 198  * created using this ioctl, and they can't be mmapped later.
 199  */
 200 struct drm_vc4_create_shader_bo {
 201         /* Size of the data argument. */
 202         uint32_t size;
 203         /* Flags, currently must be 0. */
 204         uint32_t flags;
 205
 206         /* Pointer to the data. */
 207         uint64_t data;
 208
 209         /** Returned GEM handle for the BO. */
 210         uint32_t handle;
 211         /* Pad, must be 0. */
 212         uint32_t pad;
 213 };
 214
 215 /**
 216  * struct drm_vc4_mmap_bo - ioctl argument for mapping VC4 BOs.
 217  *
 218  * This doesn't actually perform an mmap.  Instead, it returns the
 219  * offset you need to use in an mmap on the DRM device node.  This
 220  * means that tools like valgrind end up knowing about the mapped
 221  * memory.
 222  *
 223  * There are currently no values for the flags argument, but it may be
 224  * used in a future extension.
 225  */
 226 struct drm_vc4_mmap_bo {
 227         /** Handle for the object being mapped. */
 228         uint32_t handle;
 229         uint32_t flags;
 230         /** offset into the drm node to use for subsequent mmap call. */
 231         uint64_t offset;
 232 };
 233
 234 #endif /* _UAPI_VC4_DRM_H_ */