2 * Copyright © 2015 Broadcom
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "compiler/nir/nir_builder.h"
26 #include "util/u_format.h"
29 * Walks the NIR generated by TGSI-to-NIR or GLSL-to-NIR to lower its io
30 * intrinsics into something amenable to the VC4 architecture.
32 * Currently, it splits VS inputs and uniforms into scalars, drops any
33 * non-position outputs in coordinate shaders, and fixes up the addressing on
34 * indirect uniform loads. FS input and VS output scalarization is handled by
35 * nir_lower_io_to_scalar().
39 replace_intrinsic_with_vec(nir_builder
*b
, nir_intrinsic_instr
*intr
,
43 /* Batch things back together into a vector. This will get split by
44 * the later ALU scalarization pass.
46 nir_ssa_def
*vec
= nir_vec(b
, comps
, intr
->num_components
);
48 /* Replace the old intrinsic with a reference to our reconstructed
51 nir_ssa_def_rewrite_uses(&intr
->dest
.ssa
, nir_src_for_ssa(vec
));
52 nir_instr_remove(&intr
->instr
);
56 vc4_nir_unpack_8i(nir_builder
*b
, nir_ssa_def
*src
, unsigned chan
)
58 return nir_ubitfield_extract(b
,
60 nir_imm_int(b
, 8 * chan
),
64 /** Returns the 16 bit field as a sign-extended 32-bit value. */
66 vc4_nir_unpack_16i(nir_builder
*b
, nir_ssa_def
*src
, unsigned chan
)
68 return nir_ibitfield_extract(b
,
70 nir_imm_int(b
, 16 * chan
),
74 /** Returns the 16 bit field as an unsigned 32 bit value. */
76 vc4_nir_unpack_16u(nir_builder
*b
, nir_ssa_def
*src
, unsigned chan
)
79 return nir_iand(b
, src
, nir_imm_int(b
, 0xffff));
81 return nir_ushr(b
, src
, nir_imm_int(b
, 16));
86 vc4_nir_unpack_8f(nir_builder
*b
, nir_ssa_def
*src
, unsigned chan
)
88 return nir_channel(b
, nir_unpack_unorm_4x8(b
, src
), chan
);
92 vc4_nir_get_vattr_channel_vpm(struct vc4_compile
*c
,
94 nir_ssa_def
**vpm_reads
,
96 const struct util_format_description
*desc
)
98 const struct util_format_channel_description
*chan
=
102 if (swiz
> PIPE_SWIZZLE_W
) {
103 return vc4_nir_get_swizzled_channel(b
, vpm_reads
, swiz
);
104 } else if (chan
->size
== 32 && chan
->type
== UTIL_FORMAT_TYPE_FLOAT
) {
105 return vc4_nir_get_swizzled_channel(b
, vpm_reads
, swiz
);
106 } else if (chan
->size
== 32 && chan
->type
== UTIL_FORMAT_TYPE_SIGNED
) {
107 if (chan
->normalized
) {
109 nir_i2f32(b
, vpm_reads
[swiz
]),
113 return nir_i2f32(b
, vpm_reads
[swiz
]);
115 } else if (chan
->size
== 8 &&
116 (chan
->type
== UTIL_FORMAT_TYPE_UNSIGNED
||
117 chan
->type
== UTIL_FORMAT_TYPE_SIGNED
)) {
118 nir_ssa_def
*vpm
= vpm_reads
[0];
119 if (chan
->type
== UTIL_FORMAT_TYPE_SIGNED
) {
120 temp
= nir_ixor(b
, vpm
, nir_imm_int(b
, 0x80808080));
121 if (chan
->normalized
) {
122 return nir_fsub(b
, nir_fmul(b
,
123 vc4_nir_unpack_8f(b
, temp
, swiz
),
124 nir_imm_float(b
, 2.0)),
125 nir_imm_float(b
, 1.0));
129 vc4_nir_unpack_8i(b
, temp
,
131 nir_imm_float(b
, -128.0));
134 if (chan
->normalized
) {
135 return vc4_nir_unpack_8f(b
, vpm
, swiz
);
137 return nir_i2f32(b
, vc4_nir_unpack_8i(b
, vpm
, swiz
));
140 } else if (chan
->size
== 16 &&
141 (chan
->type
== UTIL_FORMAT_TYPE_UNSIGNED
||
142 chan
->type
== UTIL_FORMAT_TYPE_SIGNED
)) {
143 nir_ssa_def
*vpm
= vpm_reads
[swiz
/ 2];
145 /* Note that UNPACK_16F eats a half float, not ints, so we use
146 * UNPACK_16_I for all of these.
148 if (chan
->type
== UTIL_FORMAT_TYPE_SIGNED
) {
149 temp
= nir_i2f32(b
, vc4_nir_unpack_16i(b
, vpm
, swiz
& 1));
150 if (chan
->normalized
) {
151 return nir_fmul(b
, temp
,
152 nir_imm_float(b
, 1/32768.0f
));
157 temp
= nir_i2f32(b
, vc4_nir_unpack_16u(b
, vpm
, swiz
& 1));
158 if (chan
->normalized
) {
159 return nir_fmul(b
, temp
,
160 nir_imm_float(b
, 1 / 65535.0));
171 vc4_nir_lower_vertex_attr(struct vc4_compile
*c
, nir_builder
*b
,
172 nir_intrinsic_instr
*intr
)
174 b
->cursor
= nir_before_instr(&intr
->instr
);
176 int attr
= nir_intrinsic_base(intr
);
177 enum pipe_format format
= c
->vs_key
->attr_formats
[attr
];
178 uint32_t attr_size
= util_format_get_blocksize(format
);
180 /* We only accept direct outputs and TGSI only ever gives them to us
181 * with an offset value of 0.
183 assert(nir_src_as_const_value(intr
->src
[0]) &&
184 nir_src_as_const_value(intr
->src
[0])->u32
[0] == 0);
186 /* Generate dword loads for the VPM values (Since these intrinsics may
187 * be reordered, the actual reads will be generated at the top of the
188 * shader by ntq_setup_inputs().
190 nir_ssa_def
*vpm_reads
[4];
191 for (int i
= 0; i
< align(attr_size
, 4) / 4; i
++) {
192 nir_intrinsic_instr
*intr_comp
=
193 nir_intrinsic_instr_create(c
->s
,
194 nir_intrinsic_load_input
);
195 intr_comp
->num_components
= 1;
196 nir_intrinsic_set_base(intr_comp
, nir_intrinsic_base(intr
));
197 nir_intrinsic_set_component(intr_comp
, i
);
198 intr_comp
->src
[0] = nir_src_for_ssa(nir_imm_int(b
, 0));
199 nir_ssa_dest_init(&intr_comp
->instr
, &intr_comp
->dest
, 1, 32, NULL
);
200 nir_builder_instr_insert(b
, &intr_comp
->instr
);
202 vpm_reads
[i
] = &intr_comp
->dest
.ssa
;
205 bool format_warned
= false;
206 const struct util_format_description
*desc
=
207 util_format_description(format
);
209 nir_ssa_def
*dests
[4];
210 for (int i
= 0; i
< intr
->num_components
; i
++) {
211 uint8_t swiz
= desc
->swizzle
[i
];
212 dests
[i
] = vc4_nir_get_vattr_channel_vpm(c
, b
, vpm_reads
, swiz
,
216 if (!format_warned
) {
218 "vtx element %d unsupported type: %s\n",
219 attr
, util_format_name(format
));
220 format_warned
= true;
222 dests
[i
] = nir_imm_float(b
, 0.0);
226 replace_intrinsic_with_vec(b
, intr
, dests
);
230 is_point_sprite(struct vc4_compile
*c
, nir_variable
*var
)
232 if (var
->data
.location
< VARYING_SLOT_VAR0
||
233 var
->data
.location
> VARYING_SLOT_VAR31
)
236 return (c
->fs_key
->point_sprite_mask
&
237 (1 << (var
->data
.location
- VARYING_SLOT_VAR0
)));
241 vc4_nir_lower_fs_input(struct vc4_compile
*c
, nir_builder
*b
,
242 nir_intrinsic_instr
*intr
)
244 b
->cursor
= nir_after_instr(&intr
->instr
);
246 if (nir_intrinsic_base(intr
) >= VC4_NIR_TLB_COLOR_READ_INPUT
&&
247 nir_intrinsic_base(intr
) < (VC4_NIR_TLB_COLOR_READ_INPUT
+
249 /* This doesn't need any lowering. */
253 nir_variable
*input_var
= NULL
;
254 nir_foreach_variable(var
, &c
->s
->inputs
) {
255 if (var
->data
.driver_location
== nir_intrinsic_base(intr
)) {
262 int comp
= nir_intrinsic_component(intr
);
264 /* Lower away point coordinates, and fix up PNTC. */
265 if (is_point_sprite(c
, input_var
) ||
266 input_var
->data
.location
== VARYING_SLOT_PNTC
) {
267 assert(intr
->num_components
== 1);
269 nir_ssa_def
*result
= &intr
->dest
.ssa
;
274 /* If we're not rendering points, we need to set a
275 * defined value for the input that would come from
278 if (!c
->fs_key
->is_points
)
279 result
= nir_imm_float(b
, 0.0);
282 result
= nir_imm_float(b
, 0.0);
285 result
= nir_imm_float(b
, 1.0);
289 if (c
->fs_key
->point_coord_upper_left
&& comp
== 1)
290 result
= nir_fsub(b
, nir_imm_float(b
, 1.0), result
);
292 if (result
!= &intr
->dest
.ssa
) {
293 nir_ssa_def_rewrite_uses_after(&intr
->dest
.ssa
,
294 nir_src_for_ssa(result
),
295 result
->parent_instr
);
301 vc4_nir_lower_output(struct vc4_compile
*c
, nir_builder
*b
,
302 nir_intrinsic_instr
*intr
)
304 nir_variable
*output_var
= NULL
;
305 nir_foreach_variable(var
, &c
->s
->outputs
) {
306 if (var
->data
.driver_location
== nir_intrinsic_base(intr
)) {
313 if (c
->stage
== QSTAGE_COORD
&&
314 output_var
->data
.location
!= VARYING_SLOT_POS
&&
315 output_var
->data
.location
!= VARYING_SLOT_PSIZ
) {
316 nir_instr_remove(&intr
->instr
);
322 vc4_nir_lower_uniform(struct vc4_compile
*c
, nir_builder
*b
,
323 nir_intrinsic_instr
*intr
)
325 b
->cursor
= nir_before_instr(&intr
->instr
);
327 /* Generate scalar loads equivalent to the original vector. */
328 nir_ssa_def
*dests
[4];
329 for (unsigned i
= 0; i
< intr
->num_components
; i
++) {
330 nir_intrinsic_instr
*intr_comp
=
331 nir_intrinsic_instr_create(c
->s
, intr
->intrinsic
);
332 intr_comp
->num_components
= 1;
333 nir_ssa_dest_init(&intr_comp
->instr
, &intr_comp
->dest
, 1,
334 intr
->dest
.ssa
.bit_size
, NULL
);
336 /* Convert the uniform offset to bytes. If it happens
337 * to be a constant, constant-folding will clean up
340 nir_intrinsic_set_base(intr_comp
,
341 nir_intrinsic_base(intr
) * 16 +
345 nir_src_for_ssa(nir_ishl(b
, intr
->src
[0].ssa
,
348 dests
[i
] = &intr_comp
->dest
.ssa
;
350 nir_builder_instr_insert(b
, &intr_comp
->instr
);
353 replace_intrinsic_with_vec(b
, intr
, dests
);
357 vc4_nir_lower_io_instr(struct vc4_compile
*c
, nir_builder
*b
,
358 struct nir_instr
*instr
)
360 if (instr
->type
!= nir_instr_type_intrinsic
)
362 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
364 switch (intr
->intrinsic
) {
365 case nir_intrinsic_load_input
:
366 if (c
->stage
== QSTAGE_FRAG
)
367 vc4_nir_lower_fs_input(c
, b
, intr
);
369 vc4_nir_lower_vertex_attr(c
, b
, intr
);
372 case nir_intrinsic_store_output
:
373 vc4_nir_lower_output(c
, b
, intr
);
376 case nir_intrinsic_load_uniform
:
377 vc4_nir_lower_uniform(c
, b
, intr
);
380 case nir_intrinsic_load_user_clip_plane
:
387 vc4_nir_lower_io_impl(struct vc4_compile
*c
, nir_function_impl
*impl
)
390 nir_builder_init(&b
, impl
);
392 nir_foreach_block(block
, impl
) {
393 nir_foreach_instr_safe(instr
, block
)
394 vc4_nir_lower_io_instr(c
, &b
, instr
);
397 nir_metadata_preserve(impl
, nir_metadata_block_index
|
398 nir_metadata_dominance
);
404 vc4_nir_lower_io(nir_shader
*s
, struct vc4_compile
*c
)
406 nir_foreach_function(function
, s
) {
408 vc4_nir_lower_io_impl(c
, function
->impl
);