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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "kernel/vc4_packet.h"
26 #include "compiler/nir/nir_builder.h"
28 /** @file vc4_nir_lower_txf_ms.c
29 * Walks the NIR generated by TGSI-to-NIR to lower its nir_texop_txf_ms
30 * coordinates to do the math necessary and use a plain nir_texop_txf instead.
32 * MSAA textures are laid out as 32x32-aligned blocks of RGBA8888 or Z24S8.
33 * We can't load them through the normal sampler path because of the lack of
34 * linear support in the hardware. So, we treat MSAA textures as a giant UBO
35 * and do the math in the shader.
39 vc4_nir_lower_txf_ms_instr(nir_builder
*b
, nir_instr
*instr
, void *data
)
41 nir_tex_instr
*txf_ms
= nir_instr_as_tex(instr
);
42 const struct vc4_compile
*c
= data
;
44 nir_tex_instr
*txf
= nir_tex_instr_create(c
->s
, 1);
45 txf
->op
= nir_texop_txf
;
46 txf
->texture_index
= txf_ms
->texture_index
;
47 txf
->coord_components
= txf_ms
->coord_components
;
48 txf
->is_shadow
= txf_ms
->is_shadow
;
49 txf
->is_new_style_shadow
= txf_ms
->is_new_style_shadow
;
51 nir_ssa_def
*coord
= NULL
, *sample_index
= NULL
;
52 for (int i
= 0; i
< txf_ms
->num_srcs
; i
++) {
53 assert(txf_ms
->src
[i
].src
.is_ssa
);
55 switch (txf_ms
->src
[i
].src_type
) {
56 case nir_tex_src_coord
:
57 coord
= txf_ms
->src
[i
].src
.ssa
;
59 case nir_tex_src_ms_index
:
60 sample_index
= txf_ms
->src
[i
].src
.ssa
;
63 unreachable("Unknown txf_ms src\n");
69 nir_ssa_def
*x
= nir_channel(b
, coord
, 0);
70 nir_ssa_def
*y
= nir_channel(b
, coord
, 1);
74 uint32_t tile_w_shift
= 5;
75 uint32_t tile_h_shift
= 5;
76 uint32_t tile_size
= (tile_h
* tile_w
*
77 VC4_MAX_SAMPLES
* sizeof(uint32_t));
78 unsigned unit
= txf_ms
->texture_index
;
79 uint32_t w
= align(c
->key
->tex
[unit
].msaa_width
, tile_w
);
80 uint32_t w_tiles
= w
/ tile_w
;
82 nir_ssa_def
*x_tile
= nir_ushr(b
, x
, nir_imm_int(b
, tile_w_shift
));
83 nir_ssa_def
*y_tile
= nir_ushr(b
, y
, nir_imm_int(b
, tile_h_shift
));
84 nir_ssa_def
*tile_addr
= nir_iadd(b
,
86 nir_imm_int(b
, tile_size
)),
88 nir_imm_int(b
, (w_tiles
*
90 nir_ssa_def
*x_subspan
= nir_iand(b
, x
,
91 nir_imm_int(b
, (tile_w
- 1) & ~1));
92 nir_ssa_def
*y_subspan
= nir_iand(b
, y
,
93 nir_imm_int(b
, (tile_h
- 1) & ~1));
94 nir_ssa_def
*subspan_addr
= nir_iadd(b
,
95 nir_imul(b
, x_subspan
,
96 nir_imm_int(b
, 2 * VC4_MAX_SAMPLES
* sizeof(uint32_t))),
97 nir_imul(b
, y_subspan
,
103 nir_ssa_def
*pixel_addr
= nir_ior(b
,
107 nir_imm_int(b
, (1 << 2))),
111 nir_imm_int(b
, (1 << 3))));
113 nir_ssa_def
*sample_addr
= nir_ishl(b
, sample_index
, nir_imm_int(b
, 4));
115 nir_ssa_def
*addr
= nir_iadd(b
,
116 nir_ior(b
, sample_addr
, pixel_addr
),
117 nir_iadd(b
, subspan_addr
, tile_addr
));
119 txf
->src
[0].src_type
= nir_tex_src_coord
;
120 txf
->src
[0].src
= nir_src_for_ssa(nir_vec2(b
, addr
, nir_imm_int(b
, 0)));
121 nir_ssa_dest_init(&txf
->instr
, &txf
->dest
, 4, 32, NULL
);
122 nir_builder_instr_insert(b
, &txf
->instr
);
124 return &txf
->dest
.ssa
;
128 vc4_nir_lower_txf_ms_filter(const nir_instr
*instr
, const void *data
)
130 return (instr
->type
== nir_instr_type_tex
&&
131 nir_instr_as_tex(instr
)->op
== nir_texop_txf_ms
);
135 vc4_nir_lower_txf_ms(nir_shader
*s
, struct vc4_compile
*c
)
137 nir_shader_lower_instructions(s
,
138 vc4_nir_lower_txf_ms_filter
,
139 vc4_nir_lower_txf_ms_instr
,