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0a231b2f6e8be80a52038d7430b0933887727a8b
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "util/u_format.h"
27 #include "util/u_hash.h"
28 #include "util/u_math.h"
29 #include "util/u_memory.h"
30 #include "util/ralloc.h"
31 #include "util/hash_table.h"
32 #include "tgsi/tgsi_dump.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "compiler/nir/nir.h"
35 #include "compiler/nir/nir_builder.h"
36 #include "nir/tgsi_to_nir.h"
37 #include "vc4_context.h"
38 #include "vc4_qpu.h"
39 #include "vc4_qir.h"
40 #ifdef USE_VC4_SIMULATOR
41 #include "simpenrose/simpenrose.h"
42 #endif
43
44 static struct qreg
45 ntq_get_src(struct vc4_compile *c, nir_src src, int i);
46
47 static void
48 resize_qreg_array(struct vc4_compile *c,
49 struct qreg **regs,
50 uint32_t *size,
51 uint32_t decl_size)
52 {
53 if (*size >= decl_size)
54 return;
55
56 uint32_t old_size = *size;
57 *size = MAX2(*size * 2, decl_size);
58 *regs = reralloc(c, *regs, struct qreg, *size);
59 if (!*regs) {
60 fprintf(stderr, "Malloc failure\n");
61 abort();
62 }
63
64 for (uint32_t i = old_size; i < *size; i++)
65 (*regs)[i] = c->undef;
66 }
67
68 static struct qreg
69 indirect_uniform_load(struct vc4_compile *c, nir_intrinsic_instr *intr)
70 {
71 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0);
72 uint32_t offset = intr->const_index[0];
73 struct vc4_compiler_ubo_range *range = NULL;
74 unsigned i;
75 for (i = 0; i < c->num_uniform_ranges; i++) {
76 range = &c->ubo_ranges[i];
77 if (offset >= range->src_offset &&
78 offset < range->src_offset + range->size) {
79 break;
80 }
81 }
82 /* The driver-location-based offset always has to be within a declared
83 * uniform range.
84 */
85 assert(range);
86 if (!range->used) {
87 range->used = true;
88 range->dst_offset = c->next_ubo_dst_offset;
89 c->next_ubo_dst_offset += range->size;
90 c->num_ubo_ranges++;
91 }
92
93 offset -= range->src_offset;
94
95 /* Adjust for where we stored the TGSI register base. */
96 indirect_offset = qir_ADD(c, indirect_offset,
97 qir_uniform_ui(c, (range->dst_offset +
98 offset)));
99
100 /* Clamp to [0, array size). Note that MIN/MAX are signed. */
101 indirect_offset = qir_MAX(c, indirect_offset, qir_uniform_ui(c, 0));
102 indirect_offset = qir_MIN(c, indirect_offset,
103 qir_uniform_ui(c, (range->dst_offset +
104 range->size - 4)));
105
106 qir_TEX_DIRECT(c, indirect_offset, qir_uniform(c, QUNIFORM_UBO_ADDR, 0));
107 c->num_texture_samples++;
108 return qir_TEX_RESULT(c);
109 }
110
111 nir_ssa_def *vc4_nir_get_state_uniform(struct nir_builder *b,
112 enum quniform_contents contents)
113 {
114 nir_intrinsic_instr *intr =
115 nir_intrinsic_instr_create(b->shader,
116 nir_intrinsic_load_uniform);
117 intr->const_index[0] = (VC4_NIR_STATE_UNIFORM_OFFSET + contents) * 4;
118 intr->num_components = 1;
119 intr->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
120 nir_ssa_dest_init(&intr->instr, &intr->dest, 1, 32, NULL);
121 nir_builder_instr_insert(b, &intr->instr);
122 return &intr->dest.ssa;
123 }
124
125 nir_ssa_def *
126 vc4_nir_get_swizzled_channel(nir_builder *b, nir_ssa_def **srcs, int swiz)
127 {
128 switch (swiz) {
129 default:
130 case PIPE_SWIZZLE_NONE:
131 fprintf(stderr, "warning: unknown swizzle\n");
132 /* FALLTHROUGH */
133 case PIPE_SWIZZLE_0:
134 return nir_imm_float(b, 0.0);
135 case PIPE_SWIZZLE_1:
136 return nir_imm_float(b, 1.0);
137 case PIPE_SWIZZLE_X:
138 case PIPE_SWIZZLE_Y:
139 case PIPE_SWIZZLE_Z:
140 case PIPE_SWIZZLE_W:
141 return srcs[swiz];
142 }
143 }
144
145 static struct qreg *
146 ntq_init_ssa_def(struct vc4_compile *c, nir_ssa_def *def)
147 {
148 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
149 def->num_components);
150 _mesa_hash_table_insert(c->def_ht, def, qregs);
151 return qregs;
152 }
153
154 static struct qreg *
155 ntq_get_dest(struct vc4_compile *c, nir_dest *dest)
156 {
157 if (dest->is_ssa) {
158 struct qreg *qregs = ntq_init_ssa_def(c, &dest->ssa);
159 for (int i = 0; i < dest->ssa.num_components; i++)
160 qregs[i] = c->undef;
161 return qregs;
162 } else {
163 nir_register *reg = dest->reg.reg;
164 assert(dest->reg.base_offset == 0);
165 assert(reg->num_array_elems == 0);
166 struct hash_entry *entry =
167 _mesa_hash_table_search(c->def_ht, reg);
168 return entry->data;
169 }
170 }
171
172 static struct qreg
173 ntq_get_src(struct vc4_compile *c, nir_src src, int i)
174 {
175 struct hash_entry *entry;
176 if (src.is_ssa) {
177 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
178 assert(i < src.ssa->num_components);
179 } else {
180 nir_register *reg = src.reg.reg;
181 entry = _mesa_hash_table_search(c->def_ht, reg);
182 assert(reg->num_array_elems == 0);
183 assert(src.reg.base_offset == 0);
184 assert(i < reg->num_components);
185 }
186
187 struct qreg *qregs = entry->data;
188 return qregs[i];
189 }
190
191 static struct qreg
192 ntq_get_alu_src(struct vc4_compile *c, nir_alu_instr *instr,
193 unsigned src)
194 {
195 assert(util_is_power_of_two(instr->dest.write_mask));
196 unsigned chan = ffs(instr->dest.write_mask) - 1;
197 struct qreg r = ntq_get_src(c, instr->src[src].src,
198 instr->src[src].swizzle[chan]);
199
200 assert(!instr->src[src].abs);
201 assert(!instr->src[src].negate);
202
203 return r;
204 };
205
206 static inline struct qreg
207 qir_SAT(struct vc4_compile *c, struct qreg val)
208 {
209 return qir_FMAX(c,
210 qir_FMIN(c, val, qir_uniform_f(c, 1.0)),
211 qir_uniform_f(c, 0.0));
212 }
213
214 static struct qreg
215 ntq_rcp(struct vc4_compile *c, struct qreg x)
216 {
217 struct qreg r = qir_RCP(c, x);
218
219 /* Apply a Newton-Raphson step to improve the accuracy. */
220 r = qir_FMUL(c, r, qir_FSUB(c,
221 qir_uniform_f(c, 2.0),
222 qir_FMUL(c, x, r)));
223
224 return r;
225 }
226
227 static struct qreg
228 ntq_rsq(struct vc4_compile *c, struct qreg x)
229 {
230 struct qreg r = qir_RSQ(c, x);
231
232 /* Apply a Newton-Raphson step to improve the accuracy. */
233 r = qir_FMUL(c, r, qir_FSUB(c,
234 qir_uniform_f(c, 1.5),
235 qir_FMUL(c,
236 qir_uniform_f(c, 0.5),
237 qir_FMUL(c, x,
238 qir_FMUL(c, r, r)))));
239
240 return r;
241 }
242
243 static struct qreg
244 ntq_umul(struct vc4_compile *c, struct qreg src0, struct qreg src1)
245 {
246 struct qreg src0_hi = qir_SHR(c, src0,
247 qir_uniform_ui(c, 24));
248 struct qreg src1_hi = qir_SHR(c, src1,
249 qir_uniform_ui(c, 24));
250
251 struct qreg hilo = qir_MUL24(c, src0_hi, src1);
252 struct qreg lohi = qir_MUL24(c, src0, src1_hi);
253 struct qreg lolo = qir_MUL24(c, src0, src1);
254
255 return qir_ADD(c, lolo, qir_SHL(c,
256 qir_ADD(c, hilo, lohi),
257 qir_uniform_ui(c, 24)));
258 }
259
260 static struct qreg
261 ntq_scale_depth_texture(struct vc4_compile *c, struct qreg src)
262 {
263 struct qreg depthf = qir_ITOF(c, qir_SHR(c, src,
264 qir_uniform_ui(c, 8)));
265 return qir_FMUL(c, depthf, qir_uniform_f(c, 1.0f/0xffffff));
266 }
267
268 /**
269 * Emits a lowered TXF_MS from an MSAA texture.
270 *
271 * The addressing math has been lowered in NIR, and now we just need to read
272 * it like a UBO.
273 */
274 static void
275 ntq_emit_txf(struct vc4_compile *c, nir_tex_instr *instr)
276 {
277 uint32_t tile_width = 32;
278 uint32_t tile_height = 32;
279 uint32_t tile_size = (tile_height * tile_width *
280 VC4_MAX_SAMPLES * sizeof(uint32_t));
281
282 unsigned unit = instr->texture_index;
283 uint32_t w = align(c->key->tex[unit].msaa_width, tile_width);
284 uint32_t w_tiles = w / tile_width;
285 uint32_t h = align(c->key->tex[unit].msaa_height, tile_height);
286 uint32_t h_tiles = h / tile_height;
287 uint32_t size = w_tiles * h_tiles * tile_size;
288
289 struct qreg addr;
290 assert(instr->num_srcs == 1);
291 assert(instr->src[0].src_type == nir_tex_src_coord);
292 addr = ntq_get_src(c, instr->src[0].src, 0);
293
294 /* Perform the clamping required by kernel validation. */
295 addr = qir_MAX(c, addr, qir_uniform_ui(c, 0));
296 addr = qir_MIN(c, addr, qir_uniform_ui(c, size - 4));
297
298 qir_TEX_DIRECT(c, addr, qir_uniform(c, QUNIFORM_TEXTURE_MSAA_ADDR, unit));
299
300 struct qreg tex = qir_TEX_RESULT(c);
301 c->num_texture_samples++;
302
303 struct qreg *dest = ntq_get_dest(c, &instr->dest);
304 enum pipe_format format = c->key->tex[unit].format;
305 if (util_format_is_depth_or_stencil(format)) {
306 struct qreg scaled = ntq_scale_depth_texture(c, tex);
307 for (int i = 0; i < 4; i++)
308 dest[i] = scaled;
309 } else {
310 for (int i = 0; i < 4; i++)
311 dest[i] = qir_UNPACK_8_F(c, tex, i);
312 }
313 }
314
315 static void
316 ntq_emit_tex(struct vc4_compile *c, nir_tex_instr *instr)
317 {
318 struct qreg s, t, r, lod, compare;
319 bool is_txb = false, is_txl = false;
320 unsigned unit = instr->texture_index;
321
322 if (instr->op == nir_texop_txf) {
323 ntq_emit_txf(c, instr);
324 return;
325 }
326
327 for (unsigned i = 0; i < instr->num_srcs; i++) {
328 switch (instr->src[i].src_type) {
329 case nir_tex_src_coord:
330 s = ntq_get_src(c, instr->src[i].src, 0);
331 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D)
332 t = qir_uniform_f(c, 0.5);
333 else
334 t = ntq_get_src(c, instr->src[i].src, 1);
335 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
336 r = ntq_get_src(c, instr->src[i].src, 2);
337 break;
338 case nir_tex_src_bias:
339 lod = ntq_get_src(c, instr->src[i].src, 0);
340 is_txb = true;
341 break;
342 case nir_tex_src_lod:
343 lod = ntq_get_src(c, instr->src[i].src, 0);
344 is_txl = true;
345 break;
346 case nir_tex_src_comparitor:
347 compare = ntq_get_src(c, instr->src[i].src, 0);
348 break;
349 default:
350 unreachable("unknown texture source");
351 }
352 }
353
354 struct qreg texture_u[] = {
355 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit),
356 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
357 qir_uniform(c, QUNIFORM_CONSTANT, 0),
358 qir_uniform(c, QUNIFORM_CONSTANT, 0),
359 };
360 uint32_t next_texture_u = 0;
361
362 /* There is no native support for GL texture rectangle coordinates, so
363 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
364 * 1]).
365 */
366 if (instr->sampler_dim == GLSL_SAMPLER_DIM_RECT) {
367 s = qir_FMUL(c, s,
368 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_X, unit));
369 t = qir_FMUL(c, t,
370 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_Y, unit));
371 }
372
373 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE || is_txl) {
374 texture_u[2] = qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P2,
375 unit | (is_txl << 16));
376 }
377
378 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
379 qir_TEX_R(c, r, texture_u[next_texture_u++]);
380 } else if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
381 c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP ||
382 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
383 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
384 qir_TEX_R(c, qir_uniform(c, QUNIFORM_TEXTURE_BORDER_COLOR, unit),
385 texture_u[next_texture_u++]);
386 }
387
388 if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP) {
389 s = qir_SAT(c, s);
390 }
391
392 if (c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
393 t = qir_SAT(c, t);
394 }
395
396 qir_TEX_T(c, t, texture_u[next_texture_u++]);
397
398 if (is_txl || is_txb)
399 qir_TEX_B(c, lod, texture_u[next_texture_u++]);
400
401 qir_TEX_S(c, s, texture_u[next_texture_u++]);
402
403 c->num_texture_samples++;
404 struct qreg tex = qir_TEX_RESULT(c);
405
406 enum pipe_format format = c->key->tex[unit].format;
407
408 struct qreg *dest = ntq_get_dest(c, &instr->dest);
409 if (util_format_is_depth_or_stencil(format)) {
410 struct qreg normalized = ntq_scale_depth_texture(c, tex);
411 struct qreg depth_output;
412
413 struct qreg u0 = qir_uniform_f(c, 0.0f);
414 struct qreg u1 = qir_uniform_f(c, 1.0f);
415 if (c->key->tex[unit].compare_mode) {
416 switch (c->key->tex[unit].compare_func) {
417 case PIPE_FUNC_NEVER:
418 depth_output = qir_uniform_f(c, 0.0f);
419 break;
420 case PIPE_FUNC_ALWAYS:
421 depth_output = u1;
422 break;
423 case PIPE_FUNC_EQUAL:
424 qir_SF(c, qir_FSUB(c, compare, normalized));
425 depth_output = qir_SEL(c, QPU_COND_ZS, u1, u0);
426 break;
427 case PIPE_FUNC_NOTEQUAL:
428 qir_SF(c, qir_FSUB(c, compare, normalized));
429 depth_output = qir_SEL(c, QPU_COND_ZC, u1, u0);
430 break;
431 case PIPE_FUNC_GREATER:
432 qir_SF(c, qir_FSUB(c, compare, normalized));
433 depth_output = qir_SEL(c, QPU_COND_NC, u1, u0);
434 break;
435 case PIPE_FUNC_GEQUAL:
436 qir_SF(c, qir_FSUB(c, normalized, compare));
437 depth_output = qir_SEL(c, QPU_COND_NS, u1, u0);
438 break;
439 case PIPE_FUNC_LESS:
440 qir_SF(c, qir_FSUB(c, compare, normalized));
441 depth_output = qir_SEL(c, QPU_COND_NS, u1, u0);
442 break;
443 case PIPE_FUNC_LEQUAL:
444 qir_SF(c, qir_FSUB(c, normalized, compare));
445 depth_output = qir_SEL(c, QPU_COND_NC, u1, u0);
446 break;
447 }
448 } else {
449 depth_output = normalized;
450 }
451
452 for (int i = 0; i < 4; i++)
453 dest[i] = depth_output;
454 } else {
455 for (int i = 0; i < 4; i++)
456 dest[i] = qir_UNPACK_8_F(c, tex, i);
457 }
458 }
459
460 /**
461 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
462 * to zero).
463 */
464 static struct qreg
465 ntq_ffract(struct vc4_compile *c, struct qreg src)
466 {
467 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
468 struct qreg diff = qir_FSUB(c, src, trunc);
469 qir_SF(c, diff);
470 return qir_SEL(c, QPU_COND_NS,
471 qir_FADD(c, diff, qir_uniform_f(c, 1.0)), diff);
472 }
473
474 /**
475 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
476 * zero).
477 */
478 static struct qreg
479 ntq_ffloor(struct vc4_compile *c, struct qreg src)
480 {
481 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
482
483 /* This will be < 0 if we truncated and the truncation was of a value
484 * that was < 0 in the first place.
485 */
486 qir_SF(c, qir_FSUB(c, src, trunc));
487
488 return qir_SEL(c, QPU_COND_NS,
489 qir_FSUB(c, trunc, qir_uniform_f(c, 1.0)), trunc);
490 }
491
492 /**
493 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
494 * zero).
495 */
496 static struct qreg
497 ntq_fceil(struct vc4_compile *c, struct qreg src)
498 {
499 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
500
501 /* This will be < 0 if we truncated and the truncation was of a value
502 * that was > 0 in the first place.
503 */
504 qir_SF(c, qir_FSUB(c, trunc, src));
505
506 return qir_SEL(c, QPU_COND_NS,
507 qir_FADD(c, trunc, qir_uniform_f(c, 1.0)), trunc);
508 }
509
510 static struct qreg
511 ntq_fsin(struct vc4_compile *c, struct qreg src)
512 {
513 float coeff[] = {
514 -2.0 * M_PI,
515 pow(2.0 * M_PI, 3) / (3 * 2 * 1),
516 -pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
517 pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
518 -pow(2.0 * M_PI, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
519 };
520
521 struct qreg scaled_x =
522 qir_FMUL(c,
523 src,
524 qir_uniform_f(c, 1.0 / (M_PI * 2.0)));
525
526 struct qreg x = qir_FADD(c,
527 ntq_ffract(c, scaled_x),
528 qir_uniform_f(c, -0.5));
529 struct qreg x2 = qir_FMUL(c, x, x);
530 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
531 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
532 x = qir_FMUL(c, x, x2);
533 sum = qir_FADD(c,
534 sum,
535 qir_FMUL(c,
536 x,
537 qir_uniform_f(c, coeff[i])));
538 }
539 return sum;
540 }
541
542 static struct qreg
543 ntq_fcos(struct vc4_compile *c, struct qreg src)
544 {
545 float coeff[] = {
546 -1.0f,
547 pow(2.0 * M_PI, 2) / (2 * 1),
548 -pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
549 pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
550 -pow(2.0 * M_PI, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
551 pow(2.0 * M_PI, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
552 };
553
554 struct qreg scaled_x =
555 qir_FMUL(c, src,
556 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
557 struct qreg x_frac = qir_FADD(c,
558 ntq_ffract(c, scaled_x),
559 qir_uniform_f(c, -0.5));
560
561 struct qreg sum = qir_uniform_f(c, coeff[0]);
562 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
563 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
564 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
565 if (i != 1)
566 x = qir_FMUL(c, x, x2);
567
568 struct qreg mul = qir_FMUL(c,
569 x,
570 qir_uniform_f(c, coeff[i]));
571 if (i == 0)
572 sum = mul;
573 else
574 sum = qir_FADD(c, sum, mul);
575 }
576 return sum;
577 }
578
579 static struct qreg
580 ntq_fsign(struct vc4_compile *c, struct qreg src)
581 {
582 struct qreg t = qir_get_temp(c);
583
584 qir_SF(c, src);
585 qir_MOV_dest(c, t, qir_uniform_f(c, 0.0));
586 qir_MOV_dest(c, t, qir_uniform_f(c, 1.0))->cond = QPU_COND_ZC;
587 qir_MOV_dest(c, t, qir_uniform_f(c, -1.0))->cond = QPU_COND_NS;
588 return t;
589 }
590
591 static void
592 emit_vertex_input(struct vc4_compile *c, int attr)
593 {
594 enum pipe_format format = c->vs_key->attr_formats[attr];
595 uint32_t attr_size = util_format_get_blocksize(format);
596
597 c->vattr_sizes[attr] = align(attr_size, 4);
598 for (int i = 0; i < align(attr_size, 4) / 4; i++) {
599 c->inputs[attr * 4 + i] =
600 qir_MOV(c, qir_reg(QFILE_VPM, attr * 4 + i));
601 c->num_inputs++;
602 }
603 }
604
605 static void
606 emit_fragcoord_input(struct vc4_compile *c, int attr)
607 {
608 c->inputs[attr * 4 + 0] = qir_ITOF(c, qir_reg(QFILE_FRAG_X, 0));
609 c->inputs[attr * 4 + 1] = qir_ITOF(c, qir_reg(QFILE_FRAG_Y, 0));
610 c->inputs[attr * 4 + 2] =
611 qir_FMUL(c,
612 qir_ITOF(c, qir_FRAG_Z(c)),
613 qir_uniform_f(c, 1.0 / 0xffffff));
614 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
615 }
616
617 static struct qreg
618 emit_fragment_varying(struct vc4_compile *c, gl_varying_slot slot,
619 uint8_t swizzle)
620 {
621 uint32_t i = c->num_input_slots++;
622 struct qreg vary = {
623 QFILE_VARY,
624 i
625 };
626
627 if (c->num_input_slots >= c->input_slots_array_size) {
628 c->input_slots_array_size =
629 MAX2(4, c->input_slots_array_size * 2);
630
631 c->input_slots = reralloc(c, c->input_slots,
632 struct vc4_varying_slot,
633 c->input_slots_array_size);
634 }
635
636 c->input_slots[i].slot = slot;
637 c->input_slots[i].swizzle = swizzle;
638
639 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
640 }
641
642 static void
643 emit_fragment_input(struct vc4_compile *c, int attr, gl_varying_slot slot)
644 {
645 for (int i = 0; i < 4; i++) {
646 c->inputs[attr * 4 + i] =
647 emit_fragment_varying(c, slot, i);
648 c->num_inputs++;
649 }
650 }
651
652 static void
653 add_output(struct vc4_compile *c,
654 uint32_t decl_offset,
655 uint8_t slot,
656 uint8_t swizzle)
657 {
658 uint32_t old_array_size = c->outputs_array_size;
659 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
660 decl_offset + 1);
661
662 if (old_array_size != c->outputs_array_size) {
663 c->output_slots = reralloc(c,
664 c->output_slots,
665 struct vc4_varying_slot,
666 c->outputs_array_size);
667 }
668
669 c->output_slots[decl_offset].slot = slot;
670 c->output_slots[decl_offset].swizzle = swizzle;
671 }
672
673 static void
674 declare_uniform_range(struct vc4_compile *c, uint32_t start, uint32_t size)
675 {
676 unsigned array_id = c->num_uniform_ranges++;
677 if (array_id >= c->ubo_ranges_array_size) {
678 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
679 array_id + 1);
680 c->ubo_ranges = reralloc(c, c->ubo_ranges,
681 struct vc4_compiler_ubo_range,
682 c->ubo_ranges_array_size);
683 }
684
685 c->ubo_ranges[array_id].dst_offset = 0;
686 c->ubo_ranges[array_id].src_offset = start;
687 c->ubo_ranges[array_id].size = size;
688 c->ubo_ranges[array_id].used = false;
689 }
690
691 static bool
692 ntq_src_is_only_ssa_def_user(nir_src *src)
693 {
694 if (!src->is_ssa)
695 return false;
696
697 if (!list_empty(&src->ssa->if_uses))
698 return false;
699
700 return (src->ssa->uses.next == &src->use_link &&
701 src->ssa->uses.next->next == &src->ssa->uses);
702 }
703
704 /**
705 * In general, emits a nir_pack_unorm_4x8 as a series of MOVs with the pack
706 * bit set.
707 *
708 * However, as an optimization, it tries to find the instructions generating
709 * the sources to be packed and just emit the pack flag there, if possible.
710 */
711 static void
712 ntq_emit_pack_unorm_4x8(struct vc4_compile *c, nir_alu_instr *instr)
713 {
714 struct qreg result = qir_get_temp(c);
715 struct nir_alu_instr *vec4 = NULL;
716
717 /* If packing from a vec4 op (as expected), identify it so that we can
718 * peek back at what generated its sources.
719 */
720 if (instr->src[0].src.is_ssa &&
721 instr->src[0].src.ssa->parent_instr->type == nir_instr_type_alu &&
722 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr)->op ==
723 nir_op_vec4) {
724 vec4 = nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
725 }
726
727 /* If the pack is replicating the same channel 4 times, use the 8888
728 * pack flag. This is common for blending using the alpha
729 * channel.
730 */
731 if (instr->src[0].swizzle[0] == instr->src[0].swizzle[1] &&
732 instr->src[0].swizzle[0] == instr->src[0].swizzle[2] &&
733 instr->src[0].swizzle[0] == instr->src[0].swizzle[3]) {
734 struct qreg *dest = ntq_get_dest(c, &instr->dest.dest);
735 *dest = qir_PACK_8888_F(c,
736 ntq_get_src(c, instr->src[0].src,
737 instr->src[0].swizzle[0]));
738 return;
739 }
740
741 for (int i = 0; i < 4; i++) {
742 int swiz = instr->src[0].swizzle[i];
743 struct qreg src;
744 if (vec4) {
745 src = ntq_get_src(c, vec4->src[swiz].src,
746 vec4->src[swiz].swizzle[0]);
747 } else {
748 src = ntq_get_src(c, instr->src[0].src, swiz);
749 }
750
751 if (vec4 &&
752 ntq_src_is_only_ssa_def_user(&vec4->src[swiz].src) &&
753 src.file == QFILE_TEMP &&
754 c->defs[src.index] &&
755 qir_is_mul(c->defs[src.index]) &&
756 !c->defs[src.index]->dst.pack) {
757 struct qinst *rewrite = c->defs[src.index];
758 c->defs[src.index] = NULL;
759 rewrite->dst = result;
760 rewrite->dst.pack = QPU_PACK_MUL_8A + i;
761 continue;
762 }
763
764 qir_PACK_8_F(c, result, src, i);
765 }
766
767 struct qreg *dest = ntq_get_dest(c, &instr->dest.dest);
768 *dest = result;
769 }
770
771 /** Handles sign-extended bitfield extracts for 16 bits. */
772 static struct qreg
773 ntq_emit_ibfe(struct vc4_compile *c, struct qreg base, struct qreg offset,
774 struct qreg bits)
775 {
776 assert(bits.file == QFILE_UNIF &&
777 c->uniform_contents[bits.index] == QUNIFORM_CONSTANT &&
778 c->uniform_data[bits.index] == 16);
779
780 assert(offset.file == QFILE_UNIF &&
781 c->uniform_contents[offset.index] == QUNIFORM_CONSTANT);
782 int offset_bit = c->uniform_data[offset.index];
783 assert(offset_bit % 16 == 0);
784
785 return qir_UNPACK_16_I(c, base, offset_bit / 16);
786 }
787
788 /** Handles unsigned bitfield extracts for 8 bits. */
789 static struct qreg
790 ntq_emit_ubfe(struct vc4_compile *c, struct qreg base, struct qreg offset,
791 struct qreg bits)
792 {
793 assert(bits.file == QFILE_UNIF &&
794 c->uniform_contents[bits.index] == QUNIFORM_CONSTANT &&
795 c->uniform_data[bits.index] == 8);
796
797 assert(offset.file == QFILE_UNIF &&
798 c->uniform_contents[offset.index] == QUNIFORM_CONSTANT);
799 int offset_bit = c->uniform_data[offset.index];
800 assert(offset_bit % 8 == 0);
801
802 return qir_UNPACK_8_I(c, base, offset_bit / 8);
803 }
804
805 /**
806 * If compare_instr is a valid comparison instruction, emits the
807 * compare_instr's comparison and returns the sel_instr's return value based
808 * on the compare_instr's result.
809 */
810 static bool
811 ntq_emit_comparison(struct vc4_compile *c, struct qreg *dest,
812 nir_alu_instr *compare_instr,
813 nir_alu_instr *sel_instr)
814 {
815 enum qpu_cond cond;
816
817 switch (compare_instr->op) {
818 case nir_op_feq:
819 case nir_op_ieq:
820 case nir_op_seq:
821 cond = QPU_COND_ZS;
822 break;
823 case nir_op_fne:
824 case nir_op_ine:
825 case nir_op_sne:
826 cond = QPU_COND_ZC;
827 break;
828 case nir_op_fge:
829 case nir_op_ige:
830 case nir_op_uge:
831 case nir_op_sge:
832 cond = QPU_COND_NC;
833 break;
834 case nir_op_flt:
835 case nir_op_ilt:
836 case nir_op_slt:
837 cond = QPU_COND_NS;
838 break;
839 default:
840 return false;
841 }
842
843 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
844 struct qreg src1 = ntq_get_alu_src(c, compare_instr, 1);
845
846 unsigned unsized_type =
847 nir_alu_type_get_base_type(nir_op_infos[compare_instr->op].input_types[0]);
848 if (unsized_type == nir_type_float)
849 qir_SF(c, qir_FSUB(c, src0, src1));
850 else
851 qir_SF(c, qir_SUB(c, src0, src1));
852
853 switch (sel_instr->op) {
854 case nir_op_seq:
855 case nir_op_sne:
856 case nir_op_sge:
857 case nir_op_slt:
858 *dest = qir_SEL(c, cond,
859 qir_uniform_f(c, 1.0), qir_uniform_f(c, 0.0));
860 break;
861
862 case nir_op_bcsel:
863 *dest = qir_SEL(c, cond,
864 ntq_get_alu_src(c, sel_instr, 1),
865 ntq_get_alu_src(c, sel_instr, 2));
866 break;
867
868 default:
869 *dest = qir_SEL(c, cond,
870 qir_uniform_ui(c, ~0), qir_uniform_ui(c, 0));
871 break;
872 }
873
874 return true;
875 }
876
877 /**
878 * Attempts to fold a comparison generating a boolean result into the
879 * condition code for selecting between two values, instead of comparing the
880 * boolean result against 0 to generate the condition code.
881 */
882 static struct qreg ntq_emit_bcsel(struct vc4_compile *c, nir_alu_instr *instr,
883 struct qreg *src)
884 {
885 if (!instr->src[0].src.is_ssa)
886 goto out;
887 nir_alu_instr *compare =
888 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
889 if (!compare)
890 goto out;
891
892 struct qreg dest;
893 if (ntq_emit_comparison(c, &dest, compare, instr))
894 return dest;
895
896 out:
897 qir_SF(c, src[0]);
898 return qir_SEL(c, QPU_COND_NS, src[1], src[2]);
899 }
900
901 static void
902 ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr)
903 {
904 /* Vectors are special in that they have non-scalarized writemasks,
905 * and just take the first swizzle channel for each argument in order
906 * into each writemask channel.
907 */
908 if (instr->op == nir_op_vec2 ||
909 instr->op == nir_op_vec3 ||
910 instr->op == nir_op_vec4) {
911 struct qreg srcs[4];
912 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
913 srcs[i] = ntq_get_src(c, instr->src[i].src,
914 instr->src[i].swizzle[0]);
915 struct qreg *dest = ntq_get_dest(c, &instr->dest.dest);
916 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
917 dest[i] = srcs[i];
918 return;
919 }
920
921 if (instr->op == nir_op_pack_unorm_4x8) {
922 ntq_emit_pack_unorm_4x8(c, instr);
923 return;
924 }
925
926 if (instr->op == nir_op_unpack_unorm_4x8) {
927 struct qreg src = ntq_get_src(c, instr->src[0].src,
928 instr->src[0].swizzle[0]);
929 struct qreg *dest = ntq_get_dest(c, &instr->dest.dest);
930 for (int i = 0; i < 4; i++) {
931 if (instr->dest.write_mask & (1 << i))
932 dest[i] = qir_UNPACK_8_F(c, src, i);
933 }
934 return;
935 }
936
937 /* General case: We can just grab the one used channel per src. */
938 struct qreg src[nir_op_infos[instr->op].num_inputs];
939 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
940 src[i] = ntq_get_alu_src(c, instr, i);
941 }
942
943 /* Pick the channel to store the output in. */
944 assert(!instr->dest.saturate);
945 struct qreg *dest = ntq_get_dest(c, &instr->dest.dest);
946 assert(util_is_power_of_two(instr->dest.write_mask));
947 dest += ffs(instr->dest.write_mask) - 1;
948
949 switch (instr->op) {
950 case nir_op_fmov:
951 case nir_op_imov:
952 *dest = qir_MOV(c, src[0]);
953 break;
954 case nir_op_fmul:
955 *dest = qir_FMUL(c, src[0], src[1]);
956 break;
957 case nir_op_fadd:
958 *dest = qir_FADD(c, src[0], src[1]);
959 break;
960 case nir_op_fsub:
961 *dest = qir_FSUB(c, src[0], src[1]);
962 break;
963 case nir_op_fmin:
964 *dest = qir_FMIN(c, src[0], src[1]);
965 break;
966 case nir_op_fmax:
967 *dest = qir_FMAX(c, src[0], src[1]);
968 break;
969
970 case nir_op_f2i:
971 case nir_op_f2u:
972 *dest = qir_FTOI(c, src[0]);
973 break;
974 case nir_op_i2f:
975 case nir_op_u2f:
976 *dest = qir_ITOF(c, src[0]);
977 break;
978 case nir_op_b2f:
979 *dest = qir_AND(c, src[0], qir_uniform_f(c, 1.0));
980 break;
981 case nir_op_b2i:
982 *dest = qir_AND(c, src[0], qir_uniform_ui(c, 1));
983 break;
984 case nir_op_i2b:
985 case nir_op_f2b:
986 qir_SF(c, src[0]);
987 *dest = qir_SEL(c, QPU_COND_ZC,
988 qir_uniform_ui(c, ~0),
989 qir_uniform_ui(c, 0));
990 break;
991
992 case nir_op_iadd:
993 *dest = qir_ADD(c, src[0], src[1]);
994 break;
995 case nir_op_ushr:
996 *dest = qir_SHR(c, src[0], src[1]);
997 break;
998 case nir_op_isub:
999 *dest = qir_SUB(c, src[0], src[1]);
1000 break;
1001 case nir_op_ishr:
1002 *dest = qir_ASR(c, src[0], src[1]);
1003 break;
1004 case nir_op_ishl:
1005 *dest = qir_SHL(c, src[0], src[1]);
1006 break;
1007 case nir_op_imin:
1008 *dest = qir_MIN(c, src[0], src[1]);
1009 break;
1010 case nir_op_imax:
1011 *dest = qir_MAX(c, src[0], src[1]);
1012 break;
1013 case nir_op_iand:
1014 *dest = qir_AND(c, src[0], src[1]);
1015 break;
1016 case nir_op_ior:
1017 *dest = qir_OR(c, src[0], src[1]);
1018 break;
1019 case nir_op_ixor:
1020 *dest = qir_XOR(c, src[0], src[1]);
1021 break;
1022 case nir_op_inot:
1023 *dest = qir_NOT(c, src[0]);
1024 break;
1025
1026 case nir_op_imul:
1027 *dest = ntq_umul(c, src[0], src[1]);
1028 break;
1029
1030 case nir_op_seq:
1031 case nir_op_sne:
1032 case nir_op_sge:
1033 case nir_op_slt:
1034 case nir_op_feq:
1035 case nir_op_fne:
1036 case nir_op_fge:
1037 case nir_op_flt:
1038 case nir_op_ieq:
1039 case nir_op_ine:
1040 case nir_op_ige:
1041 case nir_op_uge:
1042 case nir_op_ilt:
1043 if (!ntq_emit_comparison(c, dest, instr, instr)) {
1044 fprintf(stderr, "Bad comparison instruction\n");
1045 }
1046 break;
1047
1048 case nir_op_bcsel:
1049 *dest = ntq_emit_bcsel(c, instr, src);
1050 break;
1051 case nir_op_fcsel:
1052 qir_SF(c, src[0]);
1053 *dest = qir_SEL(c, QPU_COND_ZC, src[1], src[2]);
1054 break;
1055
1056 case nir_op_frcp:
1057 *dest = ntq_rcp(c, src[0]);
1058 break;
1059 case nir_op_frsq:
1060 *dest = ntq_rsq(c, src[0]);
1061 break;
1062 case nir_op_fexp2:
1063 *dest = qir_EXP2(c, src[0]);
1064 break;
1065 case nir_op_flog2:
1066 *dest = qir_LOG2(c, src[0]);
1067 break;
1068
1069 case nir_op_ftrunc:
1070 *dest = qir_ITOF(c, qir_FTOI(c, src[0]));
1071 break;
1072 case nir_op_fceil:
1073 *dest = ntq_fceil(c, src[0]);
1074 break;
1075 case nir_op_ffract:
1076 *dest = ntq_ffract(c, src[0]);
1077 break;
1078 case nir_op_ffloor:
1079 *dest = ntq_ffloor(c, src[0]);
1080 break;
1081
1082 case nir_op_fsin:
1083 *dest = ntq_fsin(c, src[0]);
1084 break;
1085 case nir_op_fcos:
1086 *dest = ntq_fcos(c, src[0]);
1087 break;
1088
1089 case nir_op_fsign:
1090 *dest = ntq_fsign(c, src[0]);
1091 break;
1092
1093 case nir_op_fabs:
1094 *dest = qir_FMAXABS(c, src[0], src[0]);
1095 break;
1096 case nir_op_iabs:
1097 *dest = qir_MAX(c, src[0],
1098 qir_SUB(c, qir_uniform_ui(c, 0), src[0]));
1099 break;
1100
1101 case nir_op_ibitfield_extract:
1102 *dest = ntq_emit_ibfe(c, src[0], src[1], src[2]);
1103 break;
1104
1105 case nir_op_ubitfield_extract:
1106 *dest = ntq_emit_ubfe(c, src[0], src[1], src[2]);
1107 break;
1108
1109 case nir_op_usadd_4x8:
1110 *dest = qir_V8ADDS(c, src[0], src[1]);
1111 break;
1112
1113 case nir_op_ussub_4x8:
1114 *dest = qir_V8SUBS(c, src[0], src[1]);
1115 break;
1116
1117 case nir_op_umin_4x8:
1118 *dest = qir_V8MIN(c, src[0], src[1]);
1119 break;
1120
1121 case nir_op_umax_4x8:
1122 *dest = qir_V8MAX(c, src[0], src[1]);
1123 break;
1124
1125 case nir_op_umul_unorm_4x8:
1126 *dest = qir_V8MULD(c, src[0], src[1]);
1127 break;
1128
1129 default:
1130 fprintf(stderr, "unknown NIR ALU inst: ");
1131 nir_print_instr(&instr->instr, stderr);
1132 fprintf(stderr, "\n");
1133 abort();
1134 }
1135 }
1136
1137 static void
1138 emit_frag_end(struct vc4_compile *c)
1139 {
1140 struct qreg color;
1141 if (c->output_color_index != -1) {
1142 color = c->outputs[c->output_color_index];
1143 } else {
1144 color = qir_uniform_ui(c, 0);
1145 }
1146
1147 uint32_t discard_cond = QPU_COND_ALWAYS;
1148 if (c->discard.file != QFILE_NULL) {
1149 qir_SF(c, c->discard);
1150 discard_cond = QPU_COND_ZS;
1151 }
1152
1153 if (c->fs_key->stencil_enabled) {
1154 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1155 qir_uniform(c, QUNIFORM_STENCIL, 0));
1156 if (c->fs_key->stencil_twoside) {
1157 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1158 qir_uniform(c, QUNIFORM_STENCIL, 1));
1159 }
1160 if (c->fs_key->stencil_full_writemasks) {
1161 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1162 qir_uniform(c, QUNIFORM_STENCIL, 2));
1163 }
1164 }
1165
1166 if (c->output_sample_mask_index != -1) {
1167 qir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1168 }
1169
1170 if (c->fs_key->depth_enabled) {
1171 if (c->output_position_index != -1) {
1172 qir_FTOI_dest(c, qir_reg(QFILE_TLB_Z_WRITE, 0),
1173 qir_FMUL(c,
1174 c->outputs[c->output_position_index + 2],
1175 qir_uniform_f(c, 0xffffff)))->cond = discard_cond;
1176 } else {
1177 qir_MOV_dest(c, qir_reg(QFILE_TLB_Z_WRITE, 0),
1178 qir_FRAG_Z(c))->cond = discard_cond;
1179 }
1180 }
1181
1182 if (!c->msaa_per_sample_output) {
1183 qir_MOV_dest(c, qir_reg(QFILE_TLB_COLOR_WRITE, 0),
1184 color)->cond = discard_cond;
1185 } else {
1186 for (int i = 0; i < VC4_MAX_SAMPLES; i++) {
1187 qir_MOV_dest(c, qir_reg(QFILE_TLB_COLOR_WRITE_MS, 0),
1188 c->sample_colors[i])->cond = discard_cond;
1189 }
1190 }
1191 }
1192
1193 static void
1194 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1195 {
1196 struct qreg packed = qir_get_temp(c);
1197
1198 for (int i = 0; i < 2; i++) {
1199 struct qreg scale =
1200 qir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1201
1202 struct qreg packed_chan = packed;
1203 packed_chan.pack = QPU_PACK_A_16A + i;
1204
1205 qir_FTOI_dest(c, packed_chan,
1206 qir_FMUL(c,
1207 qir_FMUL(c,
1208 c->outputs[c->output_position_index + i],
1209 scale),
1210 rcp_w));
1211 }
1212
1213 qir_VPM_WRITE(c, packed);
1214 }
1215
1216 static void
1217 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1218 {
1219 struct qreg zscale = qir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1220 struct qreg zoffset = qir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1221
1222 qir_VPM_WRITE(c, qir_FADD(c, qir_FMUL(c, qir_FMUL(c,
1223 c->outputs[c->output_position_index + 2],
1224 zscale),
1225 rcp_w),
1226 zoffset));
1227 }
1228
1229 static void
1230 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1231 {
1232 qir_VPM_WRITE(c, rcp_w);
1233 }
1234
1235 static void
1236 emit_point_size_write(struct vc4_compile *c)
1237 {
1238 struct qreg point_size;
1239
1240 if (c->output_point_size_index != -1)
1241 point_size = c->outputs[c->output_point_size_index];
1242 else
1243 point_size = qir_uniform_f(c, 1.0);
1244
1245 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1246 * BCM21553).
1247 */
1248 point_size = qir_FMAX(c, point_size, qir_uniform_f(c, .125));
1249
1250 qir_VPM_WRITE(c, point_size);
1251 }
1252
1253 /**
1254 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1255 *
1256 * The simulator insists that there be at least one vertex attribute, so
1257 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also
1258 * insists that all vertex attributes loaded get read by the VS/CS, so we have
1259 * to consume it here.
1260 */
1261 static void
1262 emit_stub_vpm_read(struct vc4_compile *c)
1263 {
1264 if (c->num_inputs)
1265 return;
1266
1267 c->vattr_sizes[0] = 4;
1268 (void)qir_MOV(c, qir_reg(QFILE_VPM, 0));
1269 c->num_inputs++;
1270 }
1271
1272 static void
1273 emit_vert_end(struct vc4_compile *c,
1274 struct vc4_varying_slot *fs_inputs,
1275 uint32_t num_fs_inputs)
1276 {
1277 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1278
1279 emit_stub_vpm_read(c);
1280
1281 emit_scaled_viewport_write(c, rcp_w);
1282 emit_zs_write(c, rcp_w);
1283 emit_rcp_wc_write(c, rcp_w);
1284 if (c->vs_key->per_vertex_point_size)
1285 emit_point_size_write(c);
1286
1287 for (int i = 0; i < num_fs_inputs; i++) {
1288 struct vc4_varying_slot *input = &fs_inputs[i];
1289 int j;
1290
1291 for (j = 0; j < c->num_outputs; j++) {
1292 struct vc4_varying_slot *output =
1293 &c->output_slots[j];
1294
1295 if (input->slot == output->slot &&
1296 input->swizzle == output->swizzle) {
1297 qir_VPM_WRITE(c, c->outputs[j]);
1298 break;
1299 }
1300 }
1301 /* Emit padding if we didn't find a declared VS output for
1302 * this FS input.
1303 */
1304 if (j == c->num_outputs)
1305 qir_VPM_WRITE(c, qir_uniform_f(c, 0.0));
1306 }
1307 }
1308
1309 static void
1310 emit_coord_end(struct vc4_compile *c)
1311 {
1312 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1313
1314 emit_stub_vpm_read(c);
1315
1316 for (int i = 0; i < 4; i++)
1317 qir_VPM_WRITE(c, c->outputs[c->output_position_index + i]);
1318
1319 emit_scaled_viewport_write(c, rcp_w);
1320 emit_zs_write(c, rcp_w);
1321 emit_rcp_wc_write(c, rcp_w);
1322 if (c->vs_key->per_vertex_point_size)
1323 emit_point_size_write(c);
1324 }
1325
1326 static void
1327 vc4_optimize_nir(struct nir_shader *s)
1328 {
1329 bool progress;
1330
1331 do {
1332 progress = false;
1333
1334 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1335 NIR_PASS_V(s, nir_lower_alu_to_scalar);
1336 NIR_PASS_V(s, nir_lower_phis_to_scalar);
1337
1338 NIR_PASS(progress, s, nir_copy_prop);
1339 NIR_PASS(progress, s, nir_opt_remove_phis);
1340 NIR_PASS(progress, s, nir_opt_dce);
1341 NIR_PASS(progress, s, nir_opt_dead_cf);
1342 NIR_PASS(progress, s, nir_opt_cse);
1343 NIR_PASS(progress, s, nir_opt_peephole_select);
1344 NIR_PASS(progress, s, nir_opt_algebraic);
1345 NIR_PASS(progress, s, nir_opt_constant_folding);
1346 NIR_PASS(progress, s, nir_opt_undef);
1347 } while (progress);
1348 }
1349
1350 static int
1351 driver_location_compare(const void *in_a, const void *in_b)
1352 {
1353 const nir_variable *const *a = in_a;
1354 const nir_variable *const *b = in_b;
1355
1356 return (*a)->data.driver_location - (*b)->data.driver_location;
1357 }
1358
1359 static void
1360 ntq_setup_inputs(struct vc4_compile *c)
1361 {
1362 unsigned num_entries = 0;
1363 nir_foreach_variable(var, &c->s->inputs)
1364 num_entries++;
1365
1366 nir_variable *vars[num_entries];
1367
1368 unsigned i = 0;
1369 nir_foreach_variable(var, &c->s->inputs)
1370 vars[i++] = var;
1371
1372 /* Sort the variables so that we emit the input setup in
1373 * driver_location order. This is required for VPM reads, whose data
1374 * is fetched into the VPM in driver_location (TGSI register index)
1375 * order.
1376 */
1377 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1378
1379 for (unsigned i = 0; i < num_entries; i++) {
1380 nir_variable *var = vars[i];
1381 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1382 unsigned loc = var->data.driver_location;
1383
1384 assert(array_len == 1);
1385 (void)array_len;
1386 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1387 (loc + 1) * 4);
1388
1389 if (c->stage == QSTAGE_FRAG) {
1390 if (var->data.location == VARYING_SLOT_POS) {
1391 emit_fragcoord_input(c, loc);
1392 } else if (var->data.location >= VARYING_SLOT_VAR0 &&
1393 (c->fs_key->point_sprite_mask &
1394 (1 << (var->data.location -
1395 VARYING_SLOT_VAR0)))) {
1396 c->inputs[loc * 4 + 0] = c->point_x;
1397 c->inputs[loc * 4 + 1] = c->point_y;
1398 } else {
1399 emit_fragment_input(c, loc, var->data.location);
1400 }
1401 } else {
1402 emit_vertex_input(c, loc);
1403 }
1404 }
1405 }
1406
1407 static void
1408 ntq_setup_outputs(struct vc4_compile *c)
1409 {
1410 nir_foreach_variable(var, &c->s->outputs) {
1411 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1412 unsigned loc = var->data.driver_location * 4;
1413
1414 assert(array_len == 1);
1415 (void)array_len;
1416
1417 for (int i = 0; i < 4; i++)
1418 add_output(c, loc + i, var->data.location, i);
1419
1420 if (c->stage == QSTAGE_FRAG) {
1421 switch (var->data.location) {
1422 case FRAG_RESULT_COLOR:
1423 case FRAG_RESULT_DATA0:
1424 c->output_color_index = loc;
1425 break;
1426 case FRAG_RESULT_DEPTH:
1427 c->output_position_index = loc;
1428 break;
1429 case FRAG_RESULT_SAMPLE_MASK:
1430 c->output_sample_mask_index = loc;
1431 break;
1432 }
1433 } else {
1434 switch (var->data.location) {
1435 case VARYING_SLOT_POS:
1436 c->output_position_index = loc;
1437 break;
1438 case VARYING_SLOT_PSIZ:
1439 c->output_point_size_index = loc;
1440 break;
1441 }
1442 }
1443 }
1444 }
1445
1446 static void
1447 ntq_setup_uniforms(struct vc4_compile *c)
1448 {
1449 nir_foreach_variable(var, &c->s->uniforms) {
1450 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1451 unsigned array_elem_size = 4 * sizeof(float);
1452
1453 declare_uniform_range(c, var->data.driver_location * array_elem_size,
1454 array_len * array_elem_size);
1455
1456 }
1457 }
1458
1459 /**
1460 * Sets up the mapping from nir_register to struct qreg *.
1461 *
1462 * Each nir_register gets a struct qreg per 32-bit component being stored.
1463 */
1464 static void
1465 ntq_setup_registers(struct vc4_compile *c, struct exec_list *list)
1466 {
1467 foreach_list_typed(nir_register, nir_reg, node, list) {
1468 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1469 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1470 array_len *
1471 nir_reg->num_components);
1472
1473 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1474
1475 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1476 qregs[i] = qir_uniform_ui(c, 0);
1477 }
1478 }
1479
1480 static void
1481 ntq_emit_load_const(struct vc4_compile *c, nir_load_const_instr *instr)
1482 {
1483 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1484 for (int i = 0; i < instr->def.num_components; i++)
1485 qregs[i] = qir_uniform_ui(c, instr->value.u32[i]);
1486
1487 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1488 }
1489
1490 static void
1491 ntq_emit_ssa_undef(struct vc4_compile *c, nir_ssa_undef_instr *instr)
1492 {
1493 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1494
1495 /* QIR needs there to be *some* value, so pick 0 (same as for
1496 * ntq_setup_registers().
1497 */
1498 for (int i = 0; i < instr->def.num_components; i++)
1499 qregs[i] = qir_uniform_ui(c, 0);
1500 }
1501
1502 static void
1503 ntq_emit_intrinsic(struct vc4_compile *c, nir_intrinsic_instr *instr)
1504 {
1505 const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
1506 nir_const_value *const_offset;
1507 unsigned offset;
1508 struct qreg *dest = NULL;
1509
1510 if (info->has_dest) {
1511 dest = ntq_get_dest(c, &instr->dest);
1512 }
1513
1514 switch (instr->intrinsic) {
1515 case nir_intrinsic_load_uniform:
1516 assert(instr->num_components == 1);
1517 const_offset = nir_src_as_const_value(instr->src[0]);
1518 if (const_offset) {
1519 offset = instr->const_index[0] + const_offset->u32[0];
1520 assert(offset % 4 == 0);
1521 /* We need dwords */
1522 offset = offset / 4;
1523 if (offset < VC4_NIR_STATE_UNIFORM_OFFSET) {
1524 *dest = qir_uniform(c, QUNIFORM_UNIFORM,
1525 offset);
1526 } else {
1527 *dest = qir_uniform(c, offset -
1528 VC4_NIR_STATE_UNIFORM_OFFSET,
1529 0);
1530 }
1531 } else {
1532 *dest = indirect_uniform_load(c, instr);
1533 }
1534 break;
1535
1536 case nir_intrinsic_load_user_clip_plane:
1537 for (int i = 0; i < instr->num_components; i++) {
1538 dest[i] = qir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1539 instr->const_index[0] * 4 + i);
1540 }
1541 break;
1542
1543 case nir_intrinsic_load_sample_mask_in:
1544 *dest = qir_uniform(c, QUNIFORM_SAMPLE_MASK, 0);
1545 break;
1546
1547 case nir_intrinsic_load_front_face:
1548 /* The register contains 0 (front) or 1 (back), and we need to
1549 * turn it into a NIR bool where true means front.
1550 */
1551 *dest = qir_ADD(c,
1552 qir_uniform_ui(c, -1),
1553 qir_reg(QFILE_FRAG_REV_FLAG, 0));
1554 break;
1555
1556 case nir_intrinsic_load_input:
1557 assert(instr->num_components == 1);
1558 const_offset = nir_src_as_const_value(instr->src[0]);
1559 assert(const_offset && "vc4 doesn't support indirect inputs");
1560 if (instr->const_index[0] >= VC4_NIR_TLB_COLOR_READ_INPUT) {
1561 assert(const_offset->u32[0] == 0);
1562 /* Reads of the per-sample color need to be done in
1563 * order.
1564 */
1565 int sample_index = (instr->const_index[0] -
1566 VC4_NIR_TLB_COLOR_READ_INPUT);
1567 for (int i = 0; i <= sample_index; i++) {
1568 if (c->color_reads[i].file == QFILE_NULL) {
1569 c->color_reads[i] =
1570 qir_TLB_COLOR_READ(c);
1571 }
1572 }
1573 *dest = c->color_reads[sample_index];
1574 } else {
1575 offset = instr->const_index[0] + const_offset->u32[0];
1576 *dest = c->inputs[offset];
1577 }
1578 break;
1579
1580 case nir_intrinsic_store_output:
1581 const_offset = nir_src_as_const_value(instr->src[1]);
1582 assert(const_offset && "vc4 doesn't support indirect outputs");
1583 offset = instr->const_index[0] + const_offset->u32[0];
1584
1585 /* MSAA color outputs are the only case where we have an
1586 * output that's not lowered to being a store of a single 32
1587 * bit value.
1588 */
1589 if (c->stage == QSTAGE_FRAG && instr->num_components == 4) {
1590 assert(offset == c->output_color_index);
1591 for (int i = 0; i < 4; i++) {
1592 c->sample_colors[i] =
1593 qir_MOV(c, ntq_get_src(c, instr->src[0],
1594 i));
1595 }
1596 } else {
1597 assert(instr->num_components == 1);
1598 c->outputs[offset] =
1599 qir_MOV(c, ntq_get_src(c, instr->src[0], 0));
1600 c->num_outputs = MAX2(c->num_outputs, offset + 1);
1601 }
1602 break;
1603
1604 case nir_intrinsic_discard:
1605 c->discard = qir_uniform_ui(c, ~0);
1606 break;
1607
1608 case nir_intrinsic_discard_if:
1609 if (c->discard.file == QFILE_NULL)
1610 c->discard = qir_uniform_ui(c, 0);
1611 c->discard = qir_OR(c, c->discard,
1612 ntq_get_src(c, instr->src[0], 0));
1613 break;
1614
1615 default:
1616 fprintf(stderr, "Unknown intrinsic: ");
1617 nir_print_instr(&instr->instr, stderr);
1618 fprintf(stderr, "\n");
1619 break;
1620 }
1621 }
1622
1623 static void
1624 ntq_emit_if(struct vc4_compile *c, nir_if *if_stmt)
1625 {
1626 fprintf(stderr, "general IF statements not handled.\n");
1627 }
1628
1629 static void
1630 ntq_emit_instr(struct vc4_compile *c, nir_instr *instr)
1631 {
1632 switch (instr->type) {
1633 case nir_instr_type_alu:
1634 ntq_emit_alu(c, nir_instr_as_alu(instr));
1635 break;
1636
1637 case nir_instr_type_intrinsic:
1638 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
1639 break;
1640
1641 case nir_instr_type_load_const:
1642 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
1643 break;
1644
1645 case nir_instr_type_ssa_undef:
1646 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
1647 break;
1648
1649 case nir_instr_type_tex:
1650 ntq_emit_tex(c, nir_instr_as_tex(instr));
1651 break;
1652
1653 default:
1654 fprintf(stderr, "Unknown NIR instr type: ");
1655 nir_print_instr(instr, stderr);
1656 fprintf(stderr, "\n");
1657 abort();
1658 }
1659 }
1660
1661 static void
1662 ntq_emit_block(struct vc4_compile *c, nir_block *block)
1663 {
1664 nir_foreach_instr(instr, block) {
1665 ntq_emit_instr(c, instr);
1666 }
1667 }
1668
1669 static void ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list);
1670
1671 static void
1672 ntq_emit_loop(struct vc4_compile *c, nir_loop *nloop)
1673 {
1674 fprintf(stderr, "LOOPS not fully handled. Rendering errors likely.\n");
1675 ntq_emit_cf_list(c, &nloop->body);
1676 }
1677
1678 static void
1679 ntq_emit_function(struct vc4_compile *c, nir_function_impl *func)
1680 {
1681 fprintf(stderr, "FUNCTIONS not handled.\n");
1682 abort();
1683 }
1684
1685 static void
1686 ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list)
1687 {
1688 foreach_list_typed(nir_cf_node, node, node, list) {
1689 switch (node->type) {
1690 case nir_cf_node_block:
1691 ntq_emit_block(c, nir_cf_node_as_block(node));
1692 break;
1693
1694 case nir_cf_node_if:
1695 ntq_emit_if(c, nir_cf_node_as_if(node));
1696 break;
1697
1698 case nir_cf_node_loop:
1699 ntq_emit_loop(c, nir_cf_node_as_loop(node));
1700 break;
1701
1702 case nir_cf_node_function:
1703 ntq_emit_function(c, nir_cf_node_as_function(node));
1704 break;
1705
1706 default:
1707 fprintf(stderr, "Unknown NIR node type\n");
1708 abort();
1709 }
1710 }
1711 }
1712
1713 static void
1714 ntq_emit_impl(struct vc4_compile *c, nir_function_impl *impl)
1715 {
1716 ntq_setup_registers(c, &impl->registers);
1717 ntq_emit_cf_list(c, &impl->body);
1718 }
1719
1720 static void
1721 nir_to_qir(struct vc4_compile *c)
1722 {
1723 ntq_setup_inputs(c);
1724 ntq_setup_outputs(c);
1725 ntq_setup_uniforms(c);
1726 ntq_setup_registers(c, &c->s->registers);
1727
1728 /* Find the main function and emit the body. */
1729 nir_foreach_function(function, c->s) {
1730 assert(strcmp(function->name, "main") == 0);
1731 assert(function->impl);
1732 ntq_emit_impl(c, function->impl);
1733 }
1734 }
1735
1736 static const nir_shader_compiler_options nir_options = {
1737 .lower_extract_byte = true,
1738 .lower_extract_word = true,
1739 .lower_ffma = true,
1740 .lower_flrp32 = true,
1741 .lower_fpow = true,
1742 .lower_fsat = true,
1743 .lower_fsqrt = true,
1744 .lower_negate = true,
1745 };
1746
1747 static int
1748 count_nir_instrs(nir_shader *nir)
1749 {
1750 int count = 0;
1751 nir_foreach_function(function, nir) {
1752 if (!function->impl)
1753 continue;
1754 nir_foreach_block(block, function->impl) {
1755 nir_foreach_instr(instr, block)
1756 count++;
1757 }
1758 }
1759 return count;
1760 }
1761
1762 static struct vc4_compile *
1763 vc4_shader_ntq(struct vc4_context *vc4, enum qstage stage,
1764 struct vc4_key *key)
1765 {
1766 struct vc4_compile *c = qir_compile_init();
1767
1768 c->stage = stage;
1769 c->shader_state = &key->shader_state->base;
1770 c->program_id = key->shader_state->program_id;
1771 c->variant_id =
1772 p_atomic_inc_return(&key->shader_state->compiled_variant_count);
1773
1774 c->key = key;
1775 switch (stage) {
1776 case QSTAGE_FRAG:
1777 c->fs_key = (struct vc4_fs_key *)key;
1778 if (c->fs_key->is_points) {
1779 c->point_x = emit_fragment_varying(c, ~0, 0);
1780 c->point_y = emit_fragment_varying(c, ~0, 0);
1781 } else if (c->fs_key->is_lines) {
1782 c->line_x = emit_fragment_varying(c, ~0, 0);
1783 }
1784 break;
1785 case QSTAGE_VERT:
1786 c->vs_key = (struct vc4_vs_key *)key;
1787 break;
1788 case QSTAGE_COORD:
1789 c->vs_key = (struct vc4_vs_key *)key;
1790 break;
1791 }
1792
1793 c->s = nir_shader_clone(c, key->shader_state->base.ir.nir);
1794 NIR_PASS_V(c->s, nir_opt_global_to_local);
1795 NIR_PASS_V(c->s, nir_convert_to_ssa);
1796
1797 if (stage == QSTAGE_FRAG)
1798 NIR_PASS_V(c->s, vc4_nir_lower_blend, c);
1799
1800 struct nir_lower_tex_options tex_options = {
1801 /* We would need to implement txs, but we don't want the
1802 * int/float conversions
1803 */
1804 .lower_rect = false,
1805
1806 .lower_txp = ~0,
1807
1808 /* Apply swizzles to all samplers. */
1809 .swizzle_result = ~0,
1810 };
1811
1812 /* Lower the format swizzle and ARB_texture_swizzle-style swizzle.
1813 * The format swizzling applies before sRGB decode, and
1814 * ARB_texture_swizzle is the last thing before returning the sample.
1815 */
1816 for (int i = 0; i < ARRAY_SIZE(key->tex); i++) {
1817 enum pipe_format format = c->key->tex[i].format;
1818
1819 if (!format)
1820 continue;
1821
1822 const uint8_t *format_swizzle = vc4_get_format_swizzle(format);
1823
1824 for (int j = 0; j < 4; j++) {
1825 uint8_t arb_swiz = c->key->tex[i].swizzle[j];
1826
1827 if (arb_swiz <= 3) {
1828 tex_options.swizzles[i][j] =
1829 format_swizzle[arb_swiz];
1830 } else {
1831 tex_options.swizzles[i][j] = arb_swiz;
1832 }
1833 }
1834
1835 if (util_format_is_srgb(format))
1836 tex_options.lower_srgb |= (1 << i);
1837 }
1838
1839 NIR_PASS_V(c->s, nir_normalize_cubemap_coords);
1840 NIR_PASS_V(c->s, nir_lower_tex, &tex_options);
1841
1842 if (c->fs_key && c->fs_key->light_twoside)
1843 NIR_PASS_V(c->s, nir_lower_two_sided_color);
1844
1845 if (c->vs_key && c->vs_key->clamp_color)
1846 NIR_PASS_V(c->s, nir_lower_clamp_color_outputs);
1847
1848 if (stage == QSTAGE_FRAG)
1849 NIR_PASS_V(c->s, nir_lower_clip_fs, c->key->ucp_enables);
1850 else
1851 NIR_PASS_V(c->s, nir_lower_clip_vs, c->key->ucp_enables);
1852
1853 NIR_PASS_V(c->s, vc4_nir_lower_io, c);
1854 NIR_PASS_V(c->s, vc4_nir_lower_txf_ms, c);
1855 NIR_PASS_V(c->s, nir_lower_idiv);
1856 NIR_PASS_V(c->s, nir_lower_load_const_to_scalar);
1857
1858 vc4_optimize_nir(c->s);
1859
1860 NIR_PASS_V(c->s, nir_remove_dead_variables, nir_var_local);
1861 NIR_PASS_V(c->s, nir_convert_from_ssa, true);
1862
1863 if (vc4_debug & VC4_DEBUG_SHADERDB) {
1864 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d NIR instructions\n",
1865 qir_get_stage_name(c->stage),
1866 c->program_id, c->variant_id,
1867 count_nir_instrs(c->s));
1868 }
1869
1870 if (vc4_debug & VC4_DEBUG_NIR) {
1871 fprintf(stderr, "%s prog %d/%d NIR:\n",
1872 qir_get_stage_name(c->stage),
1873 c->program_id, c->variant_id);
1874 nir_print_shader(c->s, stderr);
1875 }
1876
1877 nir_to_qir(c);
1878
1879 switch (stage) {
1880 case QSTAGE_FRAG:
1881 emit_frag_end(c);
1882 break;
1883 case QSTAGE_VERT:
1884 emit_vert_end(c,
1885 vc4->prog.fs->input_slots,
1886 vc4->prog.fs->num_inputs);
1887 break;
1888 case QSTAGE_COORD:
1889 emit_coord_end(c);
1890 break;
1891 }
1892
1893 if (vc4_debug & VC4_DEBUG_QIR) {
1894 fprintf(stderr, "%s prog %d/%d pre-opt QIR:\n",
1895 qir_get_stage_name(c->stage),
1896 c->program_id, c->variant_id);
1897 qir_dump(c);
1898 fprintf(stderr, "\n");
1899 }
1900
1901 qir_optimize(c);
1902 qir_lower_uniforms(c);
1903
1904 qir_schedule_instructions(c);
1905
1906 if (vc4_debug & VC4_DEBUG_QIR) {
1907 fprintf(stderr, "%s prog %d/%d QIR:\n",
1908 qir_get_stage_name(c->stage),
1909 c->program_id, c->variant_id);
1910 qir_dump(c);
1911 fprintf(stderr, "\n");
1912 }
1913
1914 qir_reorder_uniforms(c);
1915 vc4_generate_code(vc4, c);
1916
1917 if (vc4_debug & VC4_DEBUG_SHADERDB) {
1918 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d instructions\n",
1919 qir_get_stage_name(c->stage),
1920 c->program_id, c->variant_id,
1921 c->qpu_inst_count);
1922 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d uniforms\n",
1923 qir_get_stage_name(c->stage),
1924 c->program_id, c->variant_id,
1925 c->num_uniforms);
1926 }
1927
1928 ralloc_free(c->s);
1929
1930 return c;
1931 }
1932
1933 static void *
1934 vc4_shader_state_create(struct pipe_context *pctx,
1935 const struct pipe_shader_state *cso)
1936 {
1937 struct vc4_context *vc4 = vc4_context(pctx);
1938 struct vc4_uncompiled_shader *so = CALLOC_STRUCT(vc4_uncompiled_shader);
1939 if (!so)
1940 return NULL;
1941
1942 so->program_id = vc4->next_uncompiled_program_id++;
1943
1944 nir_shader *s = tgsi_to_nir(cso->tokens, &nir_options);
1945
1946 if (vc4_debug & VC4_DEBUG_TGSI) {
1947 fprintf(stderr, "%s prog %d TGSI:\n",
1948 gl_shader_stage_name(s->stage),
1949 so->program_id);
1950 tgsi_dump(cso->tokens, 0);
1951 fprintf(stderr, "\n");
1952 }
1953
1954 so->base.type = PIPE_SHADER_IR_NIR;
1955 so->base.ir.nir = s;
1956
1957 return so;
1958 }
1959
1960 static void
1961 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
1962 struct vc4_compile *c)
1963 {
1964 int count = c->num_uniforms;
1965 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
1966
1967 uinfo->count = count;
1968 uinfo->data = ralloc_array(shader, uint32_t, count);
1969 memcpy(uinfo->data, c->uniform_data,
1970 count * sizeof(*uinfo->data));
1971 uinfo->contents = ralloc_array(shader, enum quniform_contents, count);
1972 memcpy(uinfo->contents, c->uniform_contents,
1973 count * sizeof(*uinfo->contents));
1974 uinfo->num_texture_samples = c->num_texture_samples;
1975
1976 vc4_set_shader_uniform_dirty_flags(shader);
1977 }
1978
1979 static struct vc4_compiled_shader *
1980 vc4_get_compiled_shader(struct vc4_context *vc4, enum qstage stage,
1981 struct vc4_key *key)
1982 {
1983 struct hash_table *ht;
1984 uint32_t key_size;
1985 if (stage == QSTAGE_FRAG) {
1986 ht = vc4->fs_cache;
1987 key_size = sizeof(struct vc4_fs_key);
1988 } else {
1989 ht = vc4->vs_cache;
1990 key_size = sizeof(struct vc4_vs_key);
1991 }
1992
1993 struct vc4_compiled_shader *shader;
1994 struct hash_entry *entry = _mesa_hash_table_search(ht, key);
1995 if (entry)
1996 return entry->data;
1997
1998 struct vc4_compile *c = vc4_shader_ntq(vc4, stage, key);
1999 shader = rzalloc(NULL, struct vc4_compiled_shader);
2000
2001 shader->program_id = vc4->next_compiled_program_id++;
2002 if (stage == QSTAGE_FRAG) {
2003 bool input_live[c->num_input_slots];
2004
2005 memset(input_live, 0, sizeof(input_live));
2006 qir_for_each_inst_inorder(inst, c) {
2007 for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) {
2008 if (inst->src[i].file == QFILE_VARY)
2009 input_live[inst->src[i].index] = true;
2010 }
2011 }
2012
2013 shader->input_slots = ralloc_array(shader,
2014 struct vc4_varying_slot,
2015 c->num_input_slots);
2016
2017 for (int i = 0; i < c->num_input_slots; i++) {
2018 struct vc4_varying_slot *slot = &c->input_slots[i];
2019
2020 if (!input_live[i])
2021 continue;
2022
2023 /* Skip non-VS-output inputs. */
2024 if (slot->slot == (uint8_t)~0)
2025 continue;
2026
2027 if (slot->slot == VARYING_SLOT_COL0 ||
2028 slot->slot == VARYING_SLOT_COL1 ||
2029 slot->slot == VARYING_SLOT_BFC0 ||
2030 slot->slot == VARYING_SLOT_BFC1) {
2031 shader->color_inputs |= (1 << shader->num_inputs);
2032 }
2033
2034 shader->input_slots[shader->num_inputs] = *slot;
2035 shader->num_inputs++;
2036 }
2037 } else {
2038 shader->num_inputs = c->num_inputs;
2039
2040 shader->vattr_offsets[0] = 0;
2041 for (int i = 0; i < 8; i++) {
2042 shader->vattr_offsets[i + 1] =
2043 shader->vattr_offsets[i] + c->vattr_sizes[i];
2044
2045 if (c->vattr_sizes[i])
2046 shader->vattrs_live |= (1 << i);
2047 }
2048 }
2049
2050 copy_uniform_state_to_shader(shader, c);
2051 shader->bo = vc4_bo_alloc_shader(vc4->screen, c->qpu_insts,
2052 c->qpu_inst_count * sizeof(uint64_t));
2053
2054 /* Copy the compiler UBO range state to the compiled shader, dropping
2055 * out arrays that were never referenced by an indirect load.
2056 *
2057 * (Note that QIR dead code elimination of an array access still
2058 * leaves that array alive, though)
2059 */
2060 if (c->num_ubo_ranges) {
2061 shader->num_ubo_ranges = c->num_ubo_ranges;
2062 shader->ubo_ranges = ralloc_array(shader, struct vc4_ubo_range,
2063 c->num_ubo_ranges);
2064 uint32_t j = 0;
2065 for (int i = 0; i < c->num_uniform_ranges; i++) {
2066 struct vc4_compiler_ubo_range *range =
2067 &c->ubo_ranges[i];
2068 if (!range->used)
2069 continue;
2070
2071 shader->ubo_ranges[j].dst_offset = range->dst_offset;
2072 shader->ubo_ranges[j].src_offset = range->src_offset;
2073 shader->ubo_ranges[j].size = range->size;
2074 shader->ubo_size += c->ubo_ranges[i].size;
2075 j++;
2076 }
2077 }
2078 if (shader->ubo_size) {
2079 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2080 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d UBO uniforms\n",
2081 qir_get_stage_name(c->stage),
2082 c->program_id, c->variant_id,
2083 shader->ubo_size / 4);
2084 }
2085 }
2086
2087 qir_compile_destroy(c);
2088
2089 struct vc4_key *dup_key;
2090 dup_key = ralloc_size(shader, key_size);
2091 memcpy(dup_key, key, key_size);
2092 _mesa_hash_table_insert(ht, dup_key, shader);
2093
2094 return shader;
2095 }
2096
2097 static void
2098 vc4_setup_shared_key(struct vc4_context *vc4, struct vc4_key *key,
2099 struct vc4_texture_stateobj *texstate)
2100 {
2101 for (int i = 0; i < texstate->num_textures; i++) {
2102 struct pipe_sampler_view *sampler = texstate->textures[i];
2103 struct pipe_sampler_state *sampler_state =
2104 texstate->samplers[i];
2105
2106 if (!sampler)
2107 continue;
2108
2109 key->tex[i].format = sampler->format;
2110 key->tex[i].swizzle[0] = sampler->swizzle_r;
2111 key->tex[i].swizzle[1] = sampler->swizzle_g;
2112 key->tex[i].swizzle[2] = sampler->swizzle_b;
2113 key->tex[i].swizzle[3] = sampler->swizzle_a;
2114
2115 if (sampler->texture->nr_samples > 1) {
2116 key->tex[i].msaa_width = sampler->texture->width0;
2117 key->tex[i].msaa_height = sampler->texture->height0;
2118 } else if (sampler){
2119 key->tex[i].compare_mode = sampler_state->compare_mode;
2120 key->tex[i].compare_func = sampler_state->compare_func;
2121 key->tex[i].wrap_s = sampler_state->wrap_s;
2122 key->tex[i].wrap_t = sampler_state->wrap_t;
2123 }
2124 }
2125
2126 key->ucp_enables = vc4->rasterizer->base.clip_plane_enable;
2127 }
2128
2129 static void
2130 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
2131 {
2132 struct vc4_fs_key local_key;
2133 struct vc4_fs_key *key = &local_key;
2134
2135 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2136 VC4_DIRTY_BLEND |
2137 VC4_DIRTY_FRAMEBUFFER |
2138 VC4_DIRTY_ZSA |
2139 VC4_DIRTY_RASTERIZER |
2140 VC4_DIRTY_SAMPLE_MASK |
2141 VC4_DIRTY_FRAGTEX |
2142 VC4_DIRTY_TEXSTATE |
2143 VC4_DIRTY_UNCOMPILED_FS))) {
2144 return;
2145 }
2146
2147 memset(key, 0, sizeof(*key));
2148 vc4_setup_shared_key(vc4, &key->base, &vc4->fragtex);
2149 key->base.shader_state = vc4->prog.bind_fs;
2150 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
2151 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
2152 prim_mode <= PIPE_PRIM_LINE_STRIP);
2153 key->blend = vc4->blend->rt[0];
2154 if (vc4->blend->logicop_enable) {
2155 key->logicop_func = vc4->blend->logicop_func;
2156 } else {
2157 key->logicop_func = PIPE_LOGICOP_COPY;
2158 }
2159 if (vc4->msaa) {
2160 key->msaa = vc4->rasterizer->base.multisample;
2161 key->sample_coverage = (vc4->rasterizer->base.multisample &&
2162 vc4->sample_mask != (1 << VC4_MAX_SAMPLES) - 1);
2163 key->sample_alpha_to_coverage = vc4->blend->alpha_to_coverage;
2164 key->sample_alpha_to_one = vc4->blend->alpha_to_one;
2165 }
2166
2167 if (vc4->framebuffer.cbufs[0])
2168 key->color_format = vc4->framebuffer.cbufs[0]->format;
2169
2170 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
2171 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
2172 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
2173 key->depth_enabled = (vc4->zsa->base.depth.enabled ||
2174 key->stencil_enabled);
2175 if (vc4->zsa->base.alpha.enabled) {
2176 key->alpha_test = true;
2177 key->alpha_test_func = vc4->zsa->base.alpha.func;
2178 }
2179
2180 if (key->is_points) {
2181 key->point_sprite_mask =
2182 vc4->rasterizer->base.sprite_coord_enable;
2183 key->point_coord_upper_left =
2184 (vc4->rasterizer->base.sprite_coord_mode ==
2185 PIPE_SPRITE_COORD_UPPER_LEFT);
2186 }
2187
2188 key->light_twoside = vc4->rasterizer->base.light_twoside;
2189
2190 struct vc4_compiled_shader *old_fs = vc4->prog.fs;
2191 vc4->prog.fs = vc4_get_compiled_shader(vc4, QSTAGE_FRAG, &key->base);
2192 if (vc4->prog.fs == old_fs)
2193 return;
2194
2195 vc4->dirty |= VC4_DIRTY_COMPILED_FS;
2196 if (vc4->rasterizer->base.flatshade &&
2197 old_fs && vc4->prog.fs->color_inputs != old_fs->color_inputs) {
2198 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
2199 }
2200 }
2201
2202 static void
2203 vc4_update_compiled_vs(struct vc4_context *vc4, uint8_t prim_mode)
2204 {
2205 struct vc4_vs_key local_key;
2206 struct vc4_vs_key *key = &local_key;
2207
2208 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2209 VC4_DIRTY_RASTERIZER |
2210 VC4_DIRTY_VERTTEX |
2211 VC4_DIRTY_TEXSTATE |
2212 VC4_DIRTY_VTXSTATE |
2213 VC4_DIRTY_UNCOMPILED_VS |
2214 VC4_DIRTY_COMPILED_FS))) {
2215 return;
2216 }
2217
2218 memset(key, 0, sizeof(*key));
2219 vc4_setup_shared_key(vc4, &key->base, &vc4->verttex);
2220 key->base.shader_state = vc4->prog.bind_vs;
2221 key->compiled_fs_id = vc4->prog.fs->program_id;
2222 key->clamp_color = vc4->rasterizer->base.clamp_vertex_color;
2223
2224 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
2225 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
2226
2227 key->per_vertex_point_size =
2228 (prim_mode == PIPE_PRIM_POINTS &&
2229 vc4->rasterizer->base.point_size_per_vertex);
2230
2231 struct vc4_compiled_shader *vs =
2232 vc4_get_compiled_shader(vc4, QSTAGE_VERT, &key->base);
2233 if (vs != vc4->prog.vs) {
2234 vc4->prog.vs = vs;
2235 vc4->dirty |= VC4_DIRTY_COMPILED_VS;
2236 }
2237
2238 key->is_coord = true;
2239 struct vc4_compiled_shader *cs =
2240 vc4_get_compiled_shader(vc4, QSTAGE_COORD, &key->base);
2241 if (cs != vc4->prog.cs) {
2242 vc4->prog.cs = cs;
2243 vc4->dirty |= VC4_DIRTY_COMPILED_CS;
2244 }
2245 }
2246
2247 void
2248 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
2249 {
2250 vc4_update_compiled_fs(vc4, prim_mode);
2251 vc4_update_compiled_vs(vc4, prim_mode);
2252 }
2253
2254 static uint32_t
2255 fs_cache_hash(const void *key)
2256 {
2257 return _mesa_hash_data(key, sizeof(struct vc4_fs_key));
2258 }
2259
2260 static uint32_t
2261 vs_cache_hash(const void *key)
2262 {
2263 return _mesa_hash_data(key, sizeof(struct vc4_vs_key));
2264 }
2265
2266 static bool
2267 fs_cache_compare(const void *key1, const void *key2)
2268 {
2269 return memcmp(key1, key2, sizeof(struct vc4_fs_key)) == 0;
2270 }
2271
2272 static bool
2273 vs_cache_compare(const void *key1, const void *key2)
2274 {
2275 return memcmp(key1, key2, sizeof(struct vc4_vs_key)) == 0;
2276 }
2277
2278 static void
2279 delete_from_cache_if_matches(struct hash_table *ht,
2280 struct hash_entry *entry,
2281 struct vc4_uncompiled_shader *so)
2282 {
2283 const struct vc4_key *key = entry->key;
2284
2285 if (key->shader_state == so) {
2286 struct vc4_compiled_shader *shader = entry->data;
2287 _mesa_hash_table_remove(ht, entry);
2288 vc4_bo_unreference(&shader->bo);
2289 ralloc_free(shader);
2290 }
2291 }
2292
2293 static void
2294 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
2295 {
2296 struct vc4_context *vc4 = vc4_context(pctx);
2297 struct vc4_uncompiled_shader *so = hwcso;
2298
2299 struct hash_entry *entry;
2300 hash_table_foreach(vc4->fs_cache, entry)
2301 delete_from_cache_if_matches(vc4->fs_cache, entry, so);
2302 hash_table_foreach(vc4->vs_cache, entry)
2303 delete_from_cache_if_matches(vc4->vs_cache, entry, so);
2304
2305 ralloc_free(so->base.ir.nir);
2306 free(so);
2307 }
2308
2309 static void
2310 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
2311 {
2312 struct vc4_context *vc4 = vc4_context(pctx);
2313 vc4->prog.bind_fs = hwcso;
2314 vc4->dirty |= VC4_DIRTY_UNCOMPILED_FS;
2315 }
2316
2317 static void
2318 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
2319 {
2320 struct vc4_context *vc4 = vc4_context(pctx);
2321 vc4->prog.bind_vs = hwcso;
2322 vc4->dirty |= VC4_DIRTY_UNCOMPILED_VS;
2323 }
2324
2325 void
2326 vc4_program_init(struct pipe_context *pctx)
2327 {
2328 struct vc4_context *vc4 = vc4_context(pctx);
2329
2330 pctx->create_vs_state = vc4_shader_state_create;
2331 pctx->delete_vs_state = vc4_shader_state_delete;
2332
2333 pctx->create_fs_state = vc4_shader_state_create;
2334 pctx->delete_fs_state = vc4_shader_state_delete;
2335
2336 pctx->bind_fs_state = vc4_fp_state_bind;
2337 pctx->bind_vs_state = vc4_vp_state_bind;
2338
2339 vc4->fs_cache = _mesa_hash_table_create(pctx, fs_cache_hash,
2340 fs_cache_compare);
2341 vc4->vs_cache = _mesa_hash_table_create(pctx, vs_cache_hash,
2342 vs_cache_compare);
2343 }
2344
2345 void
2346 vc4_program_fini(struct pipe_context *pctx)
2347 {
2348 struct vc4_context *vc4 = vc4_context(pctx);
2349
2350 struct hash_entry *entry;
2351 hash_table_foreach(vc4->fs_cache, entry) {
2352 struct vc4_compiled_shader *shader = entry->data;
2353 vc4_bo_unreference(&shader->bo);
2354 ralloc_free(shader);
2355 _mesa_hash_table_remove(vc4->fs_cache, entry);
2356 }
2357
2358 hash_table_foreach(vc4->vs_cache, entry) {
2359 struct vc4_compiled_shader *shader = entry->data;
2360 vc4_bo_unreference(&shader->bo);
2361 ralloc_free(shader);
2362 _mesa_hash_table_remove(vc4->vs_cache, entry);
2363 }
2364 }