2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "util/u_format.h"
27 #include "util/u_hash.h"
28 #include "util/u_math.h"
29 #include "util/u_memory.h"
30 #include "util/ralloc.h"
31 #include "util/hash_table.h"
32 #include "tgsi/tgsi_dump.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "compiler/nir/nir.h"
35 #include "compiler/nir/nir_builder.h"
36 #include "nir/tgsi_to_nir.h"
37 #include "vc4_context.h"
40 #include "mesa/state_tracker/st_glsl_types.h"
43 ntq_get_src(struct vc4_compile
*c
, nir_src src
, int i
);
45 ntq_emit_cf_list(struct vc4_compile
*c
, struct exec_list
*list
);
48 resize_qreg_array(struct vc4_compile
*c
,
53 if (*size
>= decl_size
)
56 uint32_t old_size
= *size
;
57 *size
= MAX2(*size
* 2, decl_size
);
58 *regs
= reralloc(c
, *regs
, struct qreg
, *size
);
60 fprintf(stderr
, "Malloc failure\n");
64 for (uint32_t i
= old_size
; i
< *size
; i
++)
65 (*regs
)[i
] = c
->undef
;
69 ntq_emit_thrsw(struct vc4_compile
*c
)
74 /* Always thread switch after each texture operation for now.
76 * We could do better by batching a bunch of texture fetches up and
77 * then doing one thread switch and collecting all their results
80 qir_emit_nondef(c
, qir_inst(QOP_THRSW
, c
->undef
,
82 c
->last_thrsw_at_top_level
= (c
->execute
.file
== QFILE_NULL
);
86 indirect_uniform_load(struct vc4_compile
*c
, nir_intrinsic_instr
*intr
)
88 struct qreg indirect_offset
= ntq_get_src(c
, intr
->src
[0], 0);
89 uint32_t offset
= nir_intrinsic_base(intr
);
90 struct vc4_compiler_ubo_range
*range
= NULL
;
92 for (i
= 0; i
< c
->num_uniform_ranges
; i
++) {
93 range
= &c
->ubo_ranges
[i
];
94 if (offset
>= range
->src_offset
&&
95 offset
< range
->src_offset
+ range
->size
) {
99 /* The driver-location-based offset always has to be within a declared
105 range
->dst_offset
= c
->next_ubo_dst_offset
;
106 c
->next_ubo_dst_offset
+= range
->size
;
110 offset
-= range
->src_offset
;
112 /* Adjust for where we stored the TGSI register base. */
113 indirect_offset
= qir_ADD(c
, indirect_offset
,
114 qir_uniform_ui(c
, (range
->dst_offset
+
117 /* Clamp to [0, array size). Note that MIN/MAX are signed. */
118 indirect_offset
= qir_MAX(c
, indirect_offset
, qir_uniform_ui(c
, 0));
119 indirect_offset
= qir_MIN(c
, indirect_offset
,
120 qir_uniform_ui(c
, (range
->dst_offset
+
123 qir_TEX_DIRECT(c
, indirect_offset
, qir_uniform(c
, QUNIFORM_UBO_ADDR
, 0));
124 c
->num_texture_samples
++;
128 return qir_TEX_RESULT(c
);
132 vc4_nir_get_swizzled_channel(nir_builder
*b
, nir_ssa_def
**srcs
, int swiz
)
136 case PIPE_SWIZZLE_NONE
:
137 fprintf(stderr
, "warning: unknown swizzle\n");
140 return nir_imm_float(b
, 0.0);
142 return nir_imm_float(b
, 1.0);
152 ntq_init_ssa_def(struct vc4_compile
*c
, nir_ssa_def
*def
)
154 struct qreg
*qregs
= ralloc_array(c
->def_ht
, struct qreg
,
155 def
->num_components
);
156 _mesa_hash_table_insert(c
->def_ht
, def
, qregs
);
161 * This function is responsible for getting QIR results into the associated
162 * storage for a NIR instruction.
164 * If it's a NIR SSA def, then we just set the associated hash table entry to
167 * If it's a NIR reg, then we need to update the existing qreg assigned to the
168 * NIR destination with the incoming value. To do that without introducing
169 * new MOVs, we require that the incoming qreg either be a uniform, or be
170 * SSA-defined by the previous QIR instruction in the block and rewritable by
171 * this function. That lets us sneak ahead and insert the SF flag beforehand
172 * (knowing that the previous instruction doesn't depend on flags) and rewrite
173 * its destination to be the NIR reg's destination
176 ntq_store_dest(struct vc4_compile
*c
, nir_dest
*dest
, int chan
,
179 struct qinst
*last_inst
= NULL
;
180 if (!list_empty(&c
->cur_block
->instructions
))
181 last_inst
= (struct qinst
*)c
->cur_block
->instructions
.prev
;
183 assert(result
.file
== QFILE_UNIF
||
184 (result
.file
== QFILE_TEMP
&&
185 last_inst
&& last_inst
== c
->defs
[result
.index
]));
188 assert(chan
< dest
->ssa
.num_components
);
191 struct hash_entry
*entry
=
192 _mesa_hash_table_search(c
->def_ht
, &dest
->ssa
);
197 qregs
= ntq_init_ssa_def(c
, &dest
->ssa
);
199 qregs
[chan
] = result
;
201 nir_register
*reg
= dest
->reg
.reg
;
202 assert(dest
->reg
.base_offset
== 0);
203 assert(reg
->num_array_elems
== 0);
204 struct hash_entry
*entry
=
205 _mesa_hash_table_search(c
->def_ht
, reg
);
206 struct qreg
*qregs
= entry
->data
;
208 /* Insert a MOV if the source wasn't an SSA def in the
209 * previous instruction.
211 if (result
.file
== QFILE_UNIF
) {
212 result
= qir_MOV(c
, result
);
213 last_inst
= c
->defs
[result
.index
];
216 /* We know they're both temps, so just rewrite index. */
217 c
->defs
[last_inst
->dst
.index
] = NULL
;
218 last_inst
->dst
.index
= qregs
[chan
].index
;
220 /* If we're in control flow, then make this update of the reg
221 * conditional on the execution mask.
223 if (c
->execute
.file
!= QFILE_NULL
) {
224 last_inst
->dst
.index
= qregs
[chan
].index
;
226 /* Set the flags to the current exec mask. To insert
227 * the SF, we temporarily remove our SSA instruction.
229 list_del(&last_inst
->link
);
230 qir_SF(c
, c
->execute
);
231 list_addtail(&last_inst
->link
,
232 &c
->cur_block
->instructions
);
234 last_inst
->cond
= QPU_COND_ZS
;
235 last_inst
->cond_is_exec_mask
= true;
241 ntq_get_dest(struct vc4_compile
*c
, nir_dest
*dest
)
244 struct qreg
*qregs
= ntq_init_ssa_def(c
, &dest
->ssa
);
245 for (int i
= 0; i
< dest
->ssa
.num_components
; i
++)
249 nir_register
*reg
= dest
->reg
.reg
;
250 assert(dest
->reg
.base_offset
== 0);
251 assert(reg
->num_array_elems
== 0);
252 struct hash_entry
*entry
=
253 _mesa_hash_table_search(c
->def_ht
, reg
);
259 ntq_get_src(struct vc4_compile
*c
, nir_src src
, int i
)
261 struct hash_entry
*entry
;
263 entry
= _mesa_hash_table_search(c
->def_ht
, src
.ssa
);
264 assert(i
< src
.ssa
->num_components
);
266 nir_register
*reg
= src
.reg
.reg
;
267 entry
= _mesa_hash_table_search(c
->def_ht
, reg
);
268 assert(reg
->num_array_elems
== 0);
269 assert(src
.reg
.base_offset
== 0);
270 assert(i
< reg
->num_components
);
273 struct qreg
*qregs
= entry
->data
;
278 ntq_get_alu_src(struct vc4_compile
*c
, nir_alu_instr
*instr
,
281 assert(util_is_power_of_two(instr
->dest
.write_mask
));
282 unsigned chan
= ffs(instr
->dest
.write_mask
) - 1;
283 struct qreg r
= ntq_get_src(c
, instr
->src
[src
].src
,
284 instr
->src
[src
].swizzle
[chan
]);
286 assert(!instr
->src
[src
].abs
);
287 assert(!instr
->src
[src
].negate
);
292 static inline struct qreg
293 qir_SAT(struct vc4_compile
*c
, struct qreg val
)
296 qir_FMIN(c
, val
, qir_uniform_f(c
, 1.0)),
297 qir_uniform_f(c
, 0.0));
301 ntq_rcp(struct vc4_compile
*c
, struct qreg x
)
303 struct qreg r
= qir_RCP(c
, x
);
305 /* Apply a Newton-Raphson step to improve the accuracy. */
306 r
= qir_FMUL(c
, r
, qir_FSUB(c
,
307 qir_uniform_f(c
, 2.0),
314 ntq_rsq(struct vc4_compile
*c
, struct qreg x
)
316 struct qreg r
= qir_RSQ(c
, x
);
318 /* Apply a Newton-Raphson step to improve the accuracy. */
319 r
= qir_FMUL(c
, r
, qir_FSUB(c
,
320 qir_uniform_f(c
, 1.5),
322 qir_uniform_f(c
, 0.5),
324 qir_FMUL(c
, r
, r
)))));
330 ntq_umul(struct vc4_compile
*c
, struct qreg src0
, struct qreg src1
)
332 struct qreg src0_hi
= qir_SHR(c
, src0
,
333 qir_uniform_ui(c
, 24));
334 struct qreg src1_hi
= qir_SHR(c
, src1
,
335 qir_uniform_ui(c
, 24));
337 struct qreg hilo
= qir_MUL24(c
, src0_hi
, src1
);
338 struct qreg lohi
= qir_MUL24(c
, src0
, src1_hi
);
339 struct qreg lolo
= qir_MUL24(c
, src0
, src1
);
341 return qir_ADD(c
, lolo
, qir_SHL(c
,
342 qir_ADD(c
, hilo
, lohi
),
343 qir_uniform_ui(c
, 24)));
347 ntq_scale_depth_texture(struct vc4_compile
*c
, struct qreg src
)
349 struct qreg depthf
= qir_ITOF(c
, qir_SHR(c
, src
,
350 qir_uniform_ui(c
, 8)));
351 return qir_FMUL(c
, depthf
, qir_uniform_f(c
, 1.0f
/0xffffff));
355 * Emits a lowered TXF_MS from an MSAA texture.
357 * The addressing math has been lowered in NIR, and now we just need to read
361 ntq_emit_txf(struct vc4_compile
*c
, nir_tex_instr
*instr
)
363 uint32_t tile_width
= 32;
364 uint32_t tile_height
= 32;
365 uint32_t tile_size
= (tile_height
* tile_width
*
366 VC4_MAX_SAMPLES
* sizeof(uint32_t));
368 unsigned unit
= instr
->texture_index
;
369 uint32_t w
= align(c
->key
->tex
[unit
].msaa_width
, tile_width
);
370 uint32_t w_tiles
= w
/ tile_width
;
371 uint32_t h
= align(c
->key
->tex
[unit
].msaa_height
, tile_height
);
372 uint32_t h_tiles
= h
/ tile_height
;
373 uint32_t size
= w_tiles
* h_tiles
* tile_size
;
376 assert(instr
->num_srcs
== 1);
377 assert(instr
->src
[0].src_type
== nir_tex_src_coord
);
378 addr
= ntq_get_src(c
, instr
->src
[0].src
, 0);
380 /* Perform the clamping required by kernel validation. */
381 addr
= qir_MAX(c
, addr
, qir_uniform_ui(c
, 0));
382 addr
= qir_MIN(c
, addr
, qir_uniform_ui(c
, size
- 4));
384 qir_TEX_DIRECT(c
, addr
, qir_uniform(c
, QUNIFORM_TEXTURE_MSAA_ADDR
, unit
));
388 struct qreg tex
= qir_TEX_RESULT(c
);
389 c
->num_texture_samples
++;
391 enum pipe_format format
= c
->key
->tex
[unit
].format
;
392 if (util_format_is_depth_or_stencil(format
)) {
393 struct qreg scaled
= ntq_scale_depth_texture(c
, tex
);
394 for (int i
= 0; i
< 4; i
++)
395 ntq_store_dest(c
, &instr
->dest
, i
, qir_MOV(c
, scaled
));
397 for (int i
= 0; i
< 4; i
++)
398 ntq_store_dest(c
, &instr
->dest
, i
,
399 qir_UNPACK_8_F(c
, tex
, i
));
404 ntq_emit_tex(struct vc4_compile
*c
, nir_tex_instr
*instr
)
406 struct qreg s
, t
, r
, lod
, compare
;
407 bool is_txb
= false, is_txl
= false;
408 unsigned unit
= instr
->texture_index
;
410 if (instr
->op
== nir_texop_txf
) {
411 ntq_emit_txf(c
, instr
);
415 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
416 switch (instr
->src
[i
].src_type
) {
417 case nir_tex_src_coord
:
418 s
= ntq_get_src(c
, instr
->src
[i
].src
, 0);
419 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
)
420 t
= qir_uniform_f(c
, 0.5);
422 t
= ntq_get_src(c
, instr
->src
[i
].src
, 1);
423 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
424 r
= ntq_get_src(c
, instr
->src
[i
].src
, 2);
426 case nir_tex_src_bias
:
427 lod
= ntq_get_src(c
, instr
->src
[i
].src
, 0);
430 case nir_tex_src_lod
:
431 lod
= ntq_get_src(c
, instr
->src
[i
].src
, 0);
434 case nir_tex_src_comparitor
:
435 compare
= ntq_get_src(c
, instr
->src
[i
].src
, 0);
438 unreachable("unknown texture source");
442 if (c
->stage
!= QSTAGE_FRAG
&& !is_txl
) {
443 /* From the GLSL 1.20 spec:
445 * "If it is mip-mapped and running on the vertex shader,
446 * then the base texture is used."
449 lod
= qir_uniform_ui(c
, 0);
452 if (c
->key
->tex
[unit
].force_first_level
) {
453 lod
= qir_uniform(c
, QUNIFORM_TEXTURE_FIRST_LEVEL
, unit
);
458 struct qreg texture_u
[] = {
459 qir_uniform(c
, QUNIFORM_TEXTURE_CONFIG_P0
, unit
),
460 qir_uniform(c
, QUNIFORM_TEXTURE_CONFIG_P1
, unit
),
461 qir_uniform(c
, QUNIFORM_CONSTANT
, 0),
462 qir_uniform(c
, QUNIFORM_CONSTANT
, 0),
464 uint32_t next_texture_u
= 0;
466 /* There is no native support for GL texture rectangle coordinates, so
467 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
470 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_RECT
) {
472 qir_uniform(c
, QUNIFORM_TEXRECT_SCALE_X
, unit
));
474 qir_uniform(c
, QUNIFORM_TEXRECT_SCALE_Y
, unit
));
477 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
|| is_txl
) {
478 texture_u
[2] = qir_uniform(c
, QUNIFORM_TEXTURE_CONFIG_P2
,
479 unit
| (is_txl
<< 16));
482 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
483 qir_TEX_R(c
, r
, texture_u
[next_texture_u
++]);
484 } else if (c
->key
->tex
[unit
].wrap_s
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
485 c
->key
->tex
[unit
].wrap_s
== PIPE_TEX_WRAP_CLAMP
||
486 c
->key
->tex
[unit
].wrap_t
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
487 c
->key
->tex
[unit
].wrap_t
== PIPE_TEX_WRAP_CLAMP
) {
488 qir_TEX_R(c
, qir_uniform(c
, QUNIFORM_TEXTURE_BORDER_COLOR
, unit
),
489 texture_u
[next_texture_u
++]);
492 if (c
->key
->tex
[unit
].wrap_s
== PIPE_TEX_WRAP_CLAMP
) {
496 if (c
->key
->tex
[unit
].wrap_t
== PIPE_TEX_WRAP_CLAMP
) {
500 qir_TEX_T(c
, t
, texture_u
[next_texture_u
++]);
502 if (is_txl
|| is_txb
)
503 qir_TEX_B(c
, lod
, texture_u
[next_texture_u
++]);
505 qir_TEX_S(c
, s
, texture_u
[next_texture_u
++]);
507 c
->num_texture_samples
++;
511 struct qreg tex
= qir_TEX_RESULT(c
);
513 enum pipe_format format
= c
->key
->tex
[unit
].format
;
515 struct qreg
*dest
= ntq_get_dest(c
, &instr
->dest
);
516 if (util_format_is_depth_or_stencil(format
)) {
517 struct qreg normalized
= ntq_scale_depth_texture(c
, tex
);
518 struct qreg depth_output
;
520 struct qreg u0
= qir_uniform_f(c
, 0.0f
);
521 struct qreg u1
= qir_uniform_f(c
, 1.0f
);
522 if (c
->key
->tex
[unit
].compare_mode
) {
523 /* From the GL_ARB_shadow spec:
525 * "Let Dt (D subscript t) be the depth texture
526 * value, in the range [0, 1]. Let R be the
527 * interpolated texture coordinate clamped to the
530 compare
= qir_SAT(c
, compare
);
532 switch (c
->key
->tex
[unit
].compare_func
) {
533 case PIPE_FUNC_NEVER
:
534 depth_output
= qir_uniform_f(c
, 0.0f
);
536 case PIPE_FUNC_ALWAYS
:
539 case PIPE_FUNC_EQUAL
:
540 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
541 depth_output
= qir_SEL(c
, QPU_COND_ZS
, u1
, u0
);
543 case PIPE_FUNC_NOTEQUAL
:
544 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
545 depth_output
= qir_SEL(c
, QPU_COND_ZC
, u1
, u0
);
547 case PIPE_FUNC_GREATER
:
548 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
549 depth_output
= qir_SEL(c
, QPU_COND_NC
, u1
, u0
);
551 case PIPE_FUNC_GEQUAL
:
552 qir_SF(c
, qir_FSUB(c
, normalized
, compare
));
553 depth_output
= qir_SEL(c
, QPU_COND_NS
, u1
, u0
);
556 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
557 depth_output
= qir_SEL(c
, QPU_COND_NS
, u1
, u0
);
559 case PIPE_FUNC_LEQUAL
:
560 qir_SF(c
, qir_FSUB(c
, normalized
, compare
));
561 depth_output
= qir_SEL(c
, QPU_COND_NC
, u1
, u0
);
565 depth_output
= normalized
;
568 for (int i
= 0; i
< 4; i
++)
569 dest
[i
] = depth_output
;
571 for (int i
= 0; i
< 4; i
++)
572 dest
[i
] = qir_UNPACK_8_F(c
, tex
, i
);
577 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
581 ntq_ffract(struct vc4_compile
*c
, struct qreg src
)
583 struct qreg trunc
= qir_ITOF(c
, qir_FTOI(c
, src
));
584 struct qreg diff
= qir_FSUB(c
, src
, trunc
);
586 return qir_MOV(c
, qir_SEL(c
, QPU_COND_NS
,
587 qir_FADD(c
, diff
, qir_uniform_f(c
, 1.0)),
592 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
596 ntq_ffloor(struct vc4_compile
*c
, struct qreg src
)
598 struct qreg trunc
= qir_ITOF(c
, qir_FTOI(c
, src
));
600 /* This will be < 0 if we truncated and the truncation was of a value
601 * that was < 0 in the first place.
603 qir_SF(c
, qir_FSUB(c
, src
, trunc
));
605 return qir_MOV(c
, qir_SEL(c
, QPU_COND_NS
,
606 qir_FSUB(c
, trunc
, qir_uniform_f(c
, 1.0)),
611 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
615 ntq_fceil(struct vc4_compile
*c
, struct qreg src
)
617 struct qreg trunc
= qir_ITOF(c
, qir_FTOI(c
, src
));
619 /* This will be < 0 if we truncated and the truncation was of a value
620 * that was > 0 in the first place.
622 qir_SF(c
, qir_FSUB(c
, trunc
, src
));
624 return qir_MOV(c
, qir_SEL(c
, QPU_COND_NS
,
625 qir_FADD(c
, trunc
, qir_uniform_f(c
, 1.0)),
630 ntq_fsin(struct vc4_compile
*c
, struct qreg src
)
634 pow(2.0 * M_PI
, 3) / (3 * 2 * 1),
635 -pow(2.0 * M_PI
, 5) / (5 * 4 * 3 * 2 * 1),
636 pow(2.0 * M_PI
, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
637 -pow(2.0 * M_PI
, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
640 struct qreg scaled_x
=
643 qir_uniform_f(c
, 1.0 / (M_PI
* 2.0)));
645 struct qreg x
= qir_FADD(c
,
646 ntq_ffract(c
, scaled_x
),
647 qir_uniform_f(c
, -0.5));
648 struct qreg x2
= qir_FMUL(c
, x
, x
);
649 struct qreg sum
= qir_FMUL(c
, x
, qir_uniform_f(c
, coeff
[0]));
650 for (int i
= 1; i
< ARRAY_SIZE(coeff
); i
++) {
651 x
= qir_FMUL(c
, x
, x2
);
656 qir_uniform_f(c
, coeff
[i
])));
662 ntq_fcos(struct vc4_compile
*c
, struct qreg src
)
666 pow(2.0 * M_PI
, 2) / (2 * 1),
667 -pow(2.0 * M_PI
, 4) / (4 * 3 * 2 * 1),
668 pow(2.0 * M_PI
, 6) / (6 * 5 * 4 * 3 * 2 * 1),
669 -pow(2.0 * M_PI
, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
670 pow(2.0 * M_PI
, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
673 struct qreg scaled_x
=
675 qir_uniform_f(c
, 1.0f
/ (M_PI
* 2.0f
)));
676 struct qreg x_frac
= qir_FADD(c
,
677 ntq_ffract(c
, scaled_x
),
678 qir_uniform_f(c
, -0.5));
680 struct qreg sum
= qir_uniform_f(c
, coeff
[0]);
681 struct qreg x2
= qir_FMUL(c
, x_frac
, x_frac
);
682 struct qreg x
= x2
; /* Current x^2, x^4, or x^6 */
683 for (int i
= 1; i
< ARRAY_SIZE(coeff
); i
++) {
685 x
= qir_FMUL(c
, x
, x2
);
687 struct qreg mul
= qir_FMUL(c
,
689 qir_uniform_f(c
, coeff
[i
]));
693 sum
= qir_FADD(c
, sum
, mul
);
699 ntq_fsign(struct vc4_compile
*c
, struct qreg src
)
701 struct qreg t
= qir_get_temp(c
);
704 qir_MOV_dest(c
, t
, qir_uniform_f(c
, 0.0));
705 qir_MOV_dest(c
, t
, qir_uniform_f(c
, 1.0))->cond
= QPU_COND_ZC
;
706 qir_MOV_dest(c
, t
, qir_uniform_f(c
, -1.0))->cond
= QPU_COND_NS
;
707 return qir_MOV(c
, t
);
711 emit_vertex_input(struct vc4_compile
*c
, int attr
)
713 enum pipe_format format
= c
->vs_key
->attr_formats
[attr
];
714 uint32_t attr_size
= util_format_get_blocksize(format
);
716 c
->vattr_sizes
[attr
] = align(attr_size
, 4);
717 for (int i
= 0; i
< align(attr_size
, 4) / 4; i
++) {
718 c
->inputs
[attr
* 4 + i
] =
719 qir_MOV(c
, qir_reg(QFILE_VPM
, attr
* 4 + i
));
725 emit_fragcoord_input(struct vc4_compile
*c
, int attr
)
727 c
->inputs
[attr
* 4 + 0] = qir_ITOF(c
, qir_reg(QFILE_FRAG_X
, 0));
728 c
->inputs
[attr
* 4 + 1] = qir_ITOF(c
, qir_reg(QFILE_FRAG_Y
, 0));
729 c
->inputs
[attr
* 4 + 2] =
731 qir_ITOF(c
, qir_FRAG_Z(c
)),
732 qir_uniform_f(c
, 1.0 / 0xffffff));
733 c
->inputs
[attr
* 4 + 3] = qir_RCP(c
, qir_FRAG_W(c
));
737 emit_fragment_varying(struct vc4_compile
*c
, gl_varying_slot slot
,
740 uint32_t i
= c
->num_input_slots
++;
746 if (c
->num_input_slots
>= c
->input_slots_array_size
) {
747 c
->input_slots_array_size
=
748 MAX2(4, c
->input_slots_array_size
* 2);
750 c
->input_slots
= reralloc(c
, c
->input_slots
,
751 struct vc4_varying_slot
,
752 c
->input_slots_array_size
);
755 c
->input_slots
[i
].slot
= slot
;
756 c
->input_slots
[i
].swizzle
= swizzle
;
758 return qir_VARY_ADD_C(c
, qir_FMUL(c
, vary
, qir_FRAG_W(c
)));
762 emit_fragment_input(struct vc4_compile
*c
, int attr
, gl_varying_slot slot
)
764 for (int i
= 0; i
< 4; i
++) {
765 c
->inputs
[attr
* 4 + i
] =
766 emit_fragment_varying(c
, slot
, i
);
772 add_output(struct vc4_compile
*c
,
773 uint32_t decl_offset
,
777 uint32_t old_array_size
= c
->outputs_array_size
;
778 resize_qreg_array(c
, &c
->outputs
, &c
->outputs_array_size
,
781 if (old_array_size
!= c
->outputs_array_size
) {
782 c
->output_slots
= reralloc(c
,
784 struct vc4_varying_slot
,
785 c
->outputs_array_size
);
788 c
->output_slots
[decl_offset
].slot
= slot
;
789 c
->output_slots
[decl_offset
].swizzle
= swizzle
;
793 declare_uniform_range(struct vc4_compile
*c
, uint32_t start
, uint32_t size
)
795 unsigned array_id
= c
->num_uniform_ranges
++;
796 if (array_id
>= c
->ubo_ranges_array_size
) {
797 c
->ubo_ranges_array_size
= MAX2(c
->ubo_ranges_array_size
* 2,
799 c
->ubo_ranges
= reralloc(c
, c
->ubo_ranges
,
800 struct vc4_compiler_ubo_range
,
801 c
->ubo_ranges_array_size
);
804 c
->ubo_ranges
[array_id
].dst_offset
= 0;
805 c
->ubo_ranges
[array_id
].src_offset
= start
;
806 c
->ubo_ranges
[array_id
].size
= size
;
807 c
->ubo_ranges
[array_id
].used
= false;
811 ntq_src_is_only_ssa_def_user(nir_src
*src
)
816 if (!list_empty(&src
->ssa
->if_uses
))
819 return (src
->ssa
->uses
.next
== &src
->use_link
&&
820 src
->ssa
->uses
.next
->next
== &src
->ssa
->uses
);
824 * In general, emits a nir_pack_unorm_4x8 as a series of MOVs with the pack
827 * However, as an optimization, it tries to find the instructions generating
828 * the sources to be packed and just emit the pack flag there, if possible.
831 ntq_emit_pack_unorm_4x8(struct vc4_compile
*c
, nir_alu_instr
*instr
)
833 struct qreg result
= qir_get_temp(c
);
834 struct nir_alu_instr
*vec4
= NULL
;
836 /* If packing from a vec4 op (as expected), identify it so that we can
837 * peek back at what generated its sources.
839 if (instr
->src
[0].src
.is_ssa
&&
840 instr
->src
[0].src
.ssa
->parent_instr
->type
== nir_instr_type_alu
&&
841 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
)->op
==
843 vec4
= nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
846 /* If the pack is replicating the same channel 4 times, use the 8888
847 * pack flag. This is common for blending using the alpha
850 if (instr
->src
[0].swizzle
[0] == instr
->src
[0].swizzle
[1] &&
851 instr
->src
[0].swizzle
[0] == instr
->src
[0].swizzle
[2] &&
852 instr
->src
[0].swizzle
[0] == instr
->src
[0].swizzle
[3]) {
853 struct qreg rep
= ntq_get_src(c
,
855 instr
->src
[0].swizzle
[0]);
856 ntq_store_dest(c
, &instr
->dest
.dest
, 0, qir_PACK_8888_F(c
, rep
));
860 for (int i
= 0; i
< 4; i
++) {
861 int swiz
= instr
->src
[0].swizzle
[i
];
864 src
= ntq_get_src(c
, vec4
->src
[swiz
].src
,
865 vec4
->src
[swiz
].swizzle
[0]);
867 src
= ntq_get_src(c
, instr
->src
[0].src
, swiz
);
871 ntq_src_is_only_ssa_def_user(&vec4
->src
[swiz
].src
) &&
872 src
.file
== QFILE_TEMP
&&
873 c
->defs
[src
.index
] &&
874 qir_is_mul(c
->defs
[src
.index
]) &&
875 !c
->defs
[src
.index
]->dst
.pack
) {
876 struct qinst
*rewrite
= c
->defs
[src
.index
];
877 c
->defs
[src
.index
] = NULL
;
878 rewrite
->dst
= result
;
879 rewrite
->dst
.pack
= QPU_PACK_MUL_8A
+ i
;
883 qir_PACK_8_F(c
, result
, src
, i
);
886 ntq_store_dest(c
, &instr
->dest
.dest
, 0, qir_MOV(c
, result
));
889 /** Handles sign-extended bitfield extracts for 16 bits. */
891 ntq_emit_ibfe(struct vc4_compile
*c
, struct qreg base
, struct qreg offset
,
894 assert(bits
.file
== QFILE_UNIF
&&
895 c
->uniform_contents
[bits
.index
] == QUNIFORM_CONSTANT
&&
896 c
->uniform_data
[bits
.index
] == 16);
898 assert(offset
.file
== QFILE_UNIF
&&
899 c
->uniform_contents
[offset
.index
] == QUNIFORM_CONSTANT
);
900 int offset_bit
= c
->uniform_data
[offset
.index
];
901 assert(offset_bit
% 16 == 0);
903 return qir_UNPACK_16_I(c
, base
, offset_bit
/ 16);
906 /** Handles unsigned bitfield extracts for 8 bits. */
908 ntq_emit_ubfe(struct vc4_compile
*c
, struct qreg base
, struct qreg offset
,
911 assert(bits
.file
== QFILE_UNIF
&&
912 c
->uniform_contents
[bits
.index
] == QUNIFORM_CONSTANT
&&
913 c
->uniform_data
[bits
.index
] == 8);
915 assert(offset
.file
== QFILE_UNIF
&&
916 c
->uniform_contents
[offset
.index
] == QUNIFORM_CONSTANT
);
917 int offset_bit
= c
->uniform_data
[offset
.index
];
918 assert(offset_bit
% 8 == 0);
920 return qir_UNPACK_8_I(c
, base
, offset_bit
/ 8);
924 * If compare_instr is a valid comparison instruction, emits the
925 * compare_instr's comparison and returns the sel_instr's return value based
926 * on the compare_instr's result.
929 ntq_emit_comparison(struct vc4_compile
*c
, struct qreg
*dest
,
930 nir_alu_instr
*compare_instr
,
931 nir_alu_instr
*sel_instr
)
935 switch (compare_instr
->op
) {
961 struct qreg src0
= ntq_get_alu_src(c
, compare_instr
, 0);
962 struct qreg src1
= ntq_get_alu_src(c
, compare_instr
, 1);
964 unsigned unsized_type
=
965 nir_alu_type_get_base_type(nir_op_infos
[compare_instr
->op
].input_types
[0]);
966 if (unsized_type
== nir_type_float
)
967 qir_SF(c
, qir_FSUB(c
, src0
, src1
));
969 qir_SF(c
, qir_SUB(c
, src0
, src1
));
971 switch (sel_instr
->op
) {
976 *dest
= qir_SEL(c
, cond
,
977 qir_uniform_f(c
, 1.0), qir_uniform_f(c
, 0.0));
981 *dest
= qir_SEL(c
, cond
,
982 ntq_get_alu_src(c
, sel_instr
, 1),
983 ntq_get_alu_src(c
, sel_instr
, 2));
987 *dest
= qir_SEL(c
, cond
,
988 qir_uniform_ui(c
, ~0), qir_uniform_ui(c
, 0));
992 /* Make the temporary for nir_store_dest(). */
993 *dest
= qir_MOV(c
, *dest
);
999 * Attempts to fold a comparison generating a boolean result into the
1000 * condition code for selecting between two values, instead of comparing the
1001 * boolean result against 0 to generate the condition code.
1003 static struct qreg
ntq_emit_bcsel(struct vc4_compile
*c
, nir_alu_instr
*instr
,
1006 if (!instr
->src
[0].src
.is_ssa
)
1008 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
1010 nir_alu_instr
*compare
=
1011 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
1016 if (ntq_emit_comparison(c
, &dest
, compare
, instr
))
1021 return qir_MOV(c
, qir_SEL(c
, QPU_COND_NS
, src
[1], src
[2]));
1025 ntq_fddx(struct vc4_compile
*c
, struct qreg src
)
1027 /* Make sure that we have a bare temp to use for MUL rotation, so it
1028 * can be allocated to an accumulator.
1030 if (src
.pack
|| src
.file
!= QFILE_TEMP
)
1031 src
= qir_MOV(c
, src
);
1033 struct qreg from_left
= qir_ROT_MUL(c
, src
, 1);
1034 struct qreg from_right
= qir_ROT_MUL(c
, src
, 15);
1036 /* Distinguish left/right pixels of the quad. */
1037 qir_SF(c
, qir_AND(c
, qir_reg(QFILE_QPU_ELEMENT
, 0),
1038 qir_uniform_ui(c
, 1)));
1040 return qir_MOV(c
, qir_SEL(c
, QPU_COND_ZS
,
1041 qir_FSUB(c
, from_right
, src
),
1042 qir_FSUB(c
, src
, from_left
)));
1046 ntq_fddy(struct vc4_compile
*c
, struct qreg src
)
1048 if (src
.pack
|| src
.file
!= QFILE_TEMP
)
1049 src
= qir_MOV(c
, src
);
1051 struct qreg from_bottom
= qir_ROT_MUL(c
, src
, 2);
1052 struct qreg from_top
= qir_ROT_MUL(c
, src
, 14);
1054 /* Distinguish top/bottom pixels of the quad. */
1055 qir_SF(c
, qir_AND(c
,
1056 qir_reg(QFILE_QPU_ELEMENT
, 0),
1057 qir_uniform_ui(c
, 2)));
1059 return qir_MOV(c
, qir_SEL(c
, QPU_COND_ZS
,
1060 qir_FSUB(c
, from_top
, src
),
1061 qir_FSUB(c
, src
, from_bottom
)));
1065 ntq_emit_alu(struct vc4_compile
*c
, nir_alu_instr
*instr
)
1067 /* This should always be lowered to ALU operations for VC4. */
1068 assert(!instr
->dest
.saturate
);
1070 /* Vectors are special in that they have non-scalarized writemasks,
1071 * and just take the first swizzle channel for each argument in order
1072 * into each writemask channel.
1074 if (instr
->op
== nir_op_vec2
||
1075 instr
->op
== nir_op_vec3
||
1076 instr
->op
== nir_op_vec4
) {
1077 struct qreg srcs
[4];
1078 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
1079 srcs
[i
] = ntq_get_src(c
, instr
->src
[i
].src
,
1080 instr
->src
[i
].swizzle
[0]);
1081 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
1082 ntq_store_dest(c
, &instr
->dest
.dest
, i
,
1083 qir_MOV(c
, srcs
[i
]));
1087 if (instr
->op
== nir_op_pack_unorm_4x8
) {
1088 ntq_emit_pack_unorm_4x8(c
, instr
);
1092 if (instr
->op
== nir_op_unpack_unorm_4x8
) {
1093 struct qreg src
= ntq_get_src(c
, instr
->src
[0].src
,
1094 instr
->src
[0].swizzle
[0]);
1095 for (int i
= 0; i
< 4; i
++) {
1096 if (instr
->dest
.write_mask
& (1 << i
))
1097 ntq_store_dest(c
, &instr
->dest
.dest
, i
,
1098 qir_UNPACK_8_F(c
, src
, i
));
1103 /* General case: We can just grab the one used channel per src. */
1104 struct qreg src
[nir_op_infos
[instr
->op
].num_inputs
];
1105 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
1106 src
[i
] = ntq_get_alu_src(c
, instr
, i
);
1111 switch (instr
->op
) {
1114 result
= qir_MOV(c
, src
[0]);
1117 result
= qir_FMUL(c
, src
[0], src
[1]);
1120 result
= qir_FADD(c
, src
[0], src
[1]);
1123 result
= qir_FSUB(c
, src
[0], src
[1]);
1126 result
= qir_FMIN(c
, src
[0], src
[1]);
1129 result
= qir_FMAX(c
, src
[0], src
[1]);
1134 result
= qir_FTOI(c
, src
[0]);
1138 result
= qir_ITOF(c
, src
[0]);
1141 result
= qir_AND(c
, src
[0], qir_uniform_f(c
, 1.0));
1144 result
= qir_AND(c
, src
[0], qir_uniform_ui(c
, 1));
1149 result
= qir_MOV(c
, qir_SEL(c
, QPU_COND_ZC
,
1150 qir_uniform_ui(c
, ~0),
1151 qir_uniform_ui(c
, 0)));
1155 result
= qir_ADD(c
, src
[0], src
[1]);
1158 result
= qir_SHR(c
, src
[0], src
[1]);
1161 result
= qir_SUB(c
, src
[0], src
[1]);
1164 result
= qir_ASR(c
, src
[0], src
[1]);
1167 result
= qir_SHL(c
, src
[0], src
[1]);
1170 result
= qir_MIN(c
, src
[0], src
[1]);
1173 result
= qir_MAX(c
, src
[0], src
[1]);
1176 result
= qir_AND(c
, src
[0], src
[1]);
1179 result
= qir_OR(c
, src
[0], src
[1]);
1182 result
= qir_XOR(c
, src
[0], src
[1]);
1185 result
= qir_NOT(c
, src
[0]);
1189 result
= ntq_umul(c
, src
[0], src
[1]);
1205 if (!ntq_emit_comparison(c
, &result
, instr
, instr
)) {
1206 fprintf(stderr
, "Bad comparison instruction\n");
1211 result
= ntq_emit_bcsel(c
, instr
, src
);
1215 result
= qir_MOV(c
, qir_SEL(c
, QPU_COND_ZC
, src
[1], src
[2]));
1219 result
= ntq_rcp(c
, src
[0]);
1222 result
= ntq_rsq(c
, src
[0]);
1225 result
= qir_EXP2(c
, src
[0]);
1228 result
= qir_LOG2(c
, src
[0]);
1232 result
= qir_ITOF(c
, qir_FTOI(c
, src
[0]));
1235 result
= ntq_fceil(c
, src
[0]);
1238 result
= ntq_ffract(c
, src
[0]);
1241 result
= ntq_ffloor(c
, src
[0]);
1245 result
= ntq_fsin(c
, src
[0]);
1248 result
= ntq_fcos(c
, src
[0]);
1252 result
= ntq_fsign(c
, src
[0]);
1256 result
= qir_FMAXABS(c
, src
[0], src
[0]);
1259 result
= qir_MAX(c
, src
[0],
1260 qir_SUB(c
, qir_uniform_ui(c
, 0), src
[0]));
1263 case nir_op_ibitfield_extract
:
1264 result
= ntq_emit_ibfe(c
, src
[0], src
[1], src
[2]);
1267 case nir_op_ubitfield_extract
:
1268 result
= ntq_emit_ubfe(c
, src
[0], src
[1], src
[2]);
1271 case nir_op_usadd_4x8
:
1272 result
= qir_V8ADDS(c
, src
[0], src
[1]);
1275 case nir_op_ussub_4x8
:
1276 result
= qir_V8SUBS(c
, src
[0], src
[1]);
1279 case nir_op_umin_4x8
:
1280 result
= qir_V8MIN(c
, src
[0], src
[1]);
1283 case nir_op_umax_4x8
:
1284 result
= qir_V8MAX(c
, src
[0], src
[1]);
1287 case nir_op_umul_unorm_4x8
:
1288 result
= qir_V8MULD(c
, src
[0], src
[1]);
1292 case nir_op_fddx_coarse
:
1293 case nir_op_fddx_fine
:
1294 result
= ntq_fddx(c
, src
[0]);
1298 case nir_op_fddy_coarse
:
1299 case nir_op_fddy_fine
:
1300 result
= ntq_fddy(c
, src
[0]);
1304 fprintf(stderr
, "unknown NIR ALU inst: ");
1305 nir_print_instr(&instr
->instr
, stderr
);
1306 fprintf(stderr
, "\n");
1310 /* We have a scalar result, so the instruction should only have a
1311 * single channel written to.
1313 assert(util_is_power_of_two(instr
->dest
.write_mask
));
1314 ntq_store_dest(c
, &instr
->dest
.dest
,
1315 ffs(instr
->dest
.write_mask
) - 1, result
);
1319 emit_frag_end(struct vc4_compile
*c
)
1322 if (c
->output_color_index
!= -1) {
1323 color
= c
->outputs
[c
->output_color_index
];
1325 color
= qir_uniform_ui(c
, 0);
1328 uint32_t discard_cond
= QPU_COND_ALWAYS
;
1329 if (c
->s
->info
->fs
.uses_discard
) {
1330 qir_SF(c
, c
->discard
);
1331 discard_cond
= QPU_COND_ZS
;
1334 if (c
->fs_key
->stencil_enabled
) {
1335 qir_MOV_dest(c
, qir_reg(QFILE_TLB_STENCIL_SETUP
, 0),
1336 qir_uniform(c
, QUNIFORM_STENCIL
, 0));
1337 if (c
->fs_key
->stencil_twoside
) {
1338 qir_MOV_dest(c
, qir_reg(QFILE_TLB_STENCIL_SETUP
, 0),
1339 qir_uniform(c
, QUNIFORM_STENCIL
, 1));
1341 if (c
->fs_key
->stencil_full_writemasks
) {
1342 qir_MOV_dest(c
, qir_reg(QFILE_TLB_STENCIL_SETUP
, 0),
1343 qir_uniform(c
, QUNIFORM_STENCIL
, 2));
1347 if (c
->output_sample_mask_index
!= -1) {
1348 qir_MS_MASK(c
, c
->outputs
[c
->output_sample_mask_index
]);
1351 if (c
->fs_key
->depth_enabled
) {
1352 if (c
->output_position_index
!= -1) {
1353 qir_FTOI_dest(c
, qir_reg(QFILE_TLB_Z_WRITE
, 0),
1355 c
->outputs
[c
->output_position_index
],
1356 qir_uniform_f(c
, 0xffffff)))->cond
= discard_cond
;
1358 qir_MOV_dest(c
, qir_reg(QFILE_TLB_Z_WRITE
, 0),
1359 qir_FRAG_Z(c
))->cond
= discard_cond
;
1363 if (!c
->msaa_per_sample_output
) {
1364 qir_MOV_dest(c
, qir_reg(QFILE_TLB_COLOR_WRITE
, 0),
1365 color
)->cond
= discard_cond
;
1367 for (int i
= 0; i
< VC4_MAX_SAMPLES
; i
++) {
1368 qir_MOV_dest(c
, qir_reg(QFILE_TLB_COLOR_WRITE_MS
, 0),
1369 c
->sample_colors
[i
])->cond
= discard_cond
;
1375 emit_scaled_viewport_write(struct vc4_compile
*c
, struct qreg rcp_w
)
1377 struct qreg packed
= qir_get_temp(c
);
1379 for (int i
= 0; i
< 2; i
++) {
1381 qir_uniform(c
, QUNIFORM_VIEWPORT_X_SCALE
+ i
, 0);
1383 struct qreg packed_chan
= packed
;
1384 packed_chan
.pack
= QPU_PACK_A_16A
+ i
;
1386 qir_FTOI_dest(c
, packed_chan
,
1389 c
->outputs
[c
->output_position_index
+ i
],
1394 qir_VPM_WRITE(c
, packed
);
1398 emit_zs_write(struct vc4_compile
*c
, struct qreg rcp_w
)
1400 struct qreg zscale
= qir_uniform(c
, QUNIFORM_VIEWPORT_Z_SCALE
, 0);
1401 struct qreg zoffset
= qir_uniform(c
, QUNIFORM_VIEWPORT_Z_OFFSET
, 0);
1403 qir_VPM_WRITE(c
, qir_FADD(c
, qir_FMUL(c
, qir_FMUL(c
,
1404 c
->outputs
[c
->output_position_index
+ 2],
1411 emit_rcp_wc_write(struct vc4_compile
*c
, struct qreg rcp_w
)
1413 qir_VPM_WRITE(c
, rcp_w
);
1417 emit_point_size_write(struct vc4_compile
*c
)
1419 struct qreg point_size
;
1421 if (c
->output_point_size_index
!= -1)
1422 point_size
= c
->outputs
[c
->output_point_size_index
];
1424 point_size
= qir_uniform_f(c
, 1.0);
1426 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1429 point_size
= qir_FMAX(c
, point_size
, qir_uniform_f(c
, .125));
1431 qir_VPM_WRITE(c
, point_size
);
1435 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1437 * The simulator insists that there be at least one vertex attribute, so
1438 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also
1439 * insists that all vertex attributes loaded get read by the VS/CS, so we have
1440 * to consume it here.
1443 emit_stub_vpm_read(struct vc4_compile
*c
)
1448 c
->vattr_sizes
[0] = 4;
1449 (void)qir_MOV(c
, qir_reg(QFILE_VPM
, 0));
1454 emit_vert_end(struct vc4_compile
*c
,
1455 struct vc4_varying_slot
*fs_inputs
,
1456 uint32_t num_fs_inputs
)
1458 struct qreg rcp_w
= ntq_rcp(c
, c
->outputs
[c
->output_position_index
+ 3]);
1460 emit_stub_vpm_read(c
);
1462 emit_scaled_viewport_write(c
, rcp_w
);
1463 emit_zs_write(c
, rcp_w
);
1464 emit_rcp_wc_write(c
, rcp_w
);
1465 if (c
->vs_key
->per_vertex_point_size
)
1466 emit_point_size_write(c
);
1468 for (int i
= 0; i
< num_fs_inputs
; i
++) {
1469 struct vc4_varying_slot
*input
= &fs_inputs
[i
];
1472 for (j
= 0; j
< c
->num_outputs
; j
++) {
1473 struct vc4_varying_slot
*output
=
1474 &c
->output_slots
[j
];
1476 if (input
->slot
== output
->slot
&&
1477 input
->swizzle
== output
->swizzle
) {
1478 qir_VPM_WRITE(c
, c
->outputs
[j
]);
1482 /* Emit padding if we didn't find a declared VS output for
1485 if (j
== c
->num_outputs
)
1486 qir_VPM_WRITE(c
, qir_uniform_f(c
, 0.0));
1491 emit_coord_end(struct vc4_compile
*c
)
1493 struct qreg rcp_w
= qir_RCP(c
, c
->outputs
[c
->output_position_index
+ 3]);
1495 emit_stub_vpm_read(c
);
1497 for (int i
= 0; i
< 4; i
++)
1498 qir_VPM_WRITE(c
, c
->outputs
[c
->output_position_index
+ i
]);
1500 emit_scaled_viewport_write(c
, rcp_w
);
1501 emit_zs_write(c
, rcp_w
);
1502 emit_rcp_wc_write(c
, rcp_w
);
1503 if (c
->vs_key
->per_vertex_point_size
)
1504 emit_point_size_write(c
);
1508 vc4_optimize_nir(struct nir_shader
*s
)
1515 NIR_PASS_V(s
, nir_lower_vars_to_ssa
);
1516 NIR_PASS(progress
, s
, nir_lower_alu_to_scalar
);
1517 NIR_PASS(progress
, s
, nir_lower_phis_to_scalar
);
1518 NIR_PASS(progress
, s
, nir_copy_prop
);
1519 NIR_PASS(progress
, s
, nir_opt_remove_phis
);
1520 NIR_PASS(progress
, s
, nir_opt_dce
);
1521 NIR_PASS(progress
, s
, nir_opt_dead_cf
);
1522 NIR_PASS(progress
, s
, nir_opt_cse
);
1523 NIR_PASS(progress
, s
, nir_opt_peephole_select
, 8);
1524 NIR_PASS(progress
, s
, nir_opt_algebraic
);
1525 NIR_PASS(progress
, s
, nir_opt_constant_folding
);
1526 NIR_PASS(progress
, s
, nir_opt_undef
);
1531 driver_location_compare(const void *in_a
, const void *in_b
)
1533 const nir_variable
*const *a
= in_a
;
1534 const nir_variable
*const *b
= in_b
;
1536 return (*a
)->data
.driver_location
- (*b
)->data
.driver_location
;
1540 ntq_setup_inputs(struct vc4_compile
*c
)
1542 unsigned num_entries
= 0;
1543 nir_foreach_variable(var
, &c
->s
->inputs
)
1546 nir_variable
*vars
[num_entries
];
1549 nir_foreach_variable(var
, &c
->s
->inputs
)
1552 /* Sort the variables so that we emit the input setup in
1553 * driver_location order. This is required for VPM reads, whose data
1554 * is fetched into the VPM in driver_location (TGSI register index)
1557 qsort(&vars
, num_entries
, sizeof(*vars
), driver_location_compare
);
1559 for (unsigned i
= 0; i
< num_entries
; i
++) {
1560 nir_variable
*var
= vars
[i
];
1561 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1562 unsigned loc
= var
->data
.driver_location
;
1564 assert(array_len
== 1);
1566 resize_qreg_array(c
, &c
->inputs
, &c
->inputs_array_size
,
1569 if (c
->stage
== QSTAGE_FRAG
) {
1570 if (var
->data
.location
== VARYING_SLOT_POS
) {
1571 emit_fragcoord_input(c
, loc
);
1572 } else if (var
->data
.location
== VARYING_SLOT_PNTC
||
1573 (var
->data
.location
>= VARYING_SLOT_VAR0
&&
1574 (c
->fs_key
->point_sprite_mask
&
1575 (1 << (var
->data
.location
-
1576 VARYING_SLOT_VAR0
))))) {
1577 c
->inputs
[loc
* 4 + 0] = c
->point_x
;
1578 c
->inputs
[loc
* 4 + 1] = c
->point_y
;
1580 emit_fragment_input(c
, loc
, var
->data
.location
);
1583 emit_vertex_input(c
, loc
);
1589 ntq_setup_outputs(struct vc4_compile
*c
)
1591 nir_foreach_variable(var
, &c
->s
->outputs
) {
1592 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1593 unsigned loc
= var
->data
.driver_location
* 4;
1595 assert(array_len
== 1);
1598 for (int i
= 0; i
< 4; i
++)
1599 add_output(c
, loc
+ i
, var
->data
.location
, i
);
1601 if (c
->stage
== QSTAGE_FRAG
) {
1602 switch (var
->data
.location
) {
1603 case FRAG_RESULT_COLOR
:
1604 case FRAG_RESULT_DATA0
:
1605 c
->output_color_index
= loc
;
1607 case FRAG_RESULT_DEPTH
:
1608 c
->output_position_index
= loc
;
1610 case FRAG_RESULT_SAMPLE_MASK
:
1611 c
->output_sample_mask_index
= loc
;
1615 switch (var
->data
.location
) {
1616 case VARYING_SLOT_POS
:
1617 c
->output_position_index
= loc
;
1619 case VARYING_SLOT_PSIZ
:
1620 c
->output_point_size_index
= loc
;
1628 ntq_setup_uniforms(struct vc4_compile
*c
)
1630 nir_foreach_variable(var
, &c
->s
->uniforms
) {
1631 uint32_t vec4_count
= st_glsl_type_size(var
->type
);
1632 unsigned vec4_size
= 4 * sizeof(float);
1634 declare_uniform_range(c
, var
->data
.driver_location
* vec4_size
,
1635 vec4_count
* vec4_size
);
1641 * Sets up the mapping from nir_register to struct qreg *.
1643 * Each nir_register gets a struct qreg per 32-bit component being stored.
1646 ntq_setup_registers(struct vc4_compile
*c
, struct exec_list
*list
)
1648 foreach_list_typed(nir_register
, nir_reg
, node
, list
) {
1649 unsigned array_len
= MAX2(nir_reg
->num_array_elems
, 1);
1650 struct qreg
*qregs
= ralloc_array(c
->def_ht
, struct qreg
,
1652 nir_reg
->num_components
);
1654 _mesa_hash_table_insert(c
->def_ht
, nir_reg
, qregs
);
1656 for (int i
= 0; i
< array_len
* nir_reg
->num_components
; i
++)
1657 qregs
[i
] = qir_get_temp(c
);
1662 ntq_emit_load_const(struct vc4_compile
*c
, nir_load_const_instr
*instr
)
1664 struct qreg
*qregs
= ntq_init_ssa_def(c
, &instr
->def
);
1665 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1666 qregs
[i
] = qir_uniform_ui(c
, instr
->value
.u32
[i
]);
1668 _mesa_hash_table_insert(c
->def_ht
, &instr
->def
, qregs
);
1672 ntq_emit_ssa_undef(struct vc4_compile
*c
, nir_ssa_undef_instr
*instr
)
1674 struct qreg
*qregs
= ntq_init_ssa_def(c
, &instr
->def
);
1676 /* QIR needs there to be *some* value, so pick 0 (same as for
1677 * ntq_setup_registers().
1679 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1680 qregs
[i
] = qir_uniform_ui(c
, 0);
1684 ntq_emit_intrinsic(struct vc4_compile
*c
, nir_intrinsic_instr
*instr
)
1686 nir_const_value
*const_offset
;
1689 switch (instr
->intrinsic
) {
1690 case nir_intrinsic_load_uniform
:
1691 assert(instr
->num_components
== 1);
1692 const_offset
= nir_src_as_const_value(instr
->src
[0]);
1694 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1695 assert(offset
% 4 == 0);
1696 /* We need dwords */
1697 offset
= offset
/ 4;
1698 ntq_store_dest(c
, &instr
->dest
, 0,
1699 qir_uniform(c
, QUNIFORM_UNIFORM
,
1702 ntq_store_dest(c
, &instr
->dest
, 0,
1703 indirect_uniform_load(c
, instr
));
1707 case nir_intrinsic_load_user_clip_plane
:
1708 for (int i
= 0; i
< instr
->num_components
; i
++) {
1709 ntq_store_dest(c
, &instr
->dest
, i
,
1710 qir_uniform(c
, QUNIFORM_USER_CLIP_PLANE
,
1711 nir_intrinsic_ucp_id(instr
) *
1716 case nir_intrinsic_load_blend_const_color_r_float
:
1717 case nir_intrinsic_load_blend_const_color_g_float
:
1718 case nir_intrinsic_load_blend_const_color_b_float
:
1719 case nir_intrinsic_load_blend_const_color_a_float
:
1720 ntq_store_dest(c
, &instr
->dest
, 0,
1721 qir_uniform(c
, QUNIFORM_BLEND_CONST_COLOR_X
+
1723 nir_intrinsic_load_blend_const_color_r_float
),
1727 case nir_intrinsic_load_blend_const_color_rgba8888_unorm
:
1728 ntq_store_dest(c
, &instr
->dest
, 0,
1729 qir_uniform(c
, QUNIFORM_BLEND_CONST_COLOR_RGBA
,
1733 case nir_intrinsic_load_blend_const_color_aaaa8888_unorm
:
1734 ntq_store_dest(c
, &instr
->dest
, 0,
1735 qir_uniform(c
, QUNIFORM_BLEND_CONST_COLOR_AAAA
,
1739 case nir_intrinsic_load_alpha_ref_float
:
1740 ntq_store_dest(c
, &instr
->dest
, 0,
1741 qir_uniform(c
, QUNIFORM_ALPHA_REF
, 0));
1744 case nir_intrinsic_load_sample_mask_in
:
1745 ntq_store_dest(c
, &instr
->dest
, 0,
1746 qir_uniform(c
, QUNIFORM_SAMPLE_MASK
, 0));
1749 case nir_intrinsic_load_front_face
:
1750 /* The register contains 0 (front) or 1 (back), and we need to
1751 * turn it into a NIR bool where true means front.
1753 ntq_store_dest(c
, &instr
->dest
, 0,
1755 qir_uniform_ui(c
, -1),
1756 qir_reg(QFILE_FRAG_REV_FLAG
, 0)));
1759 case nir_intrinsic_load_input
:
1760 assert(instr
->num_components
== 1);
1761 const_offset
= nir_src_as_const_value(instr
->src
[0]);
1762 assert(const_offset
&& "vc4 doesn't support indirect inputs");
1763 if (c
->stage
== QSTAGE_FRAG
&&
1764 nir_intrinsic_base(instr
) >= VC4_NIR_TLB_COLOR_READ_INPUT
) {
1765 assert(const_offset
->u32
[0] == 0);
1766 /* Reads of the per-sample color need to be done in
1769 int sample_index
= (nir_intrinsic_base(instr
) -
1770 VC4_NIR_TLB_COLOR_READ_INPUT
);
1771 for (int i
= 0; i
<= sample_index
; i
++) {
1772 if (c
->color_reads
[i
].file
== QFILE_NULL
) {
1774 qir_TLB_COLOR_READ(c
);
1777 ntq_store_dest(c
, &instr
->dest
, 0,
1778 qir_MOV(c
, c
->color_reads
[sample_index
]));
1780 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1781 int comp
= nir_intrinsic_component(instr
);
1782 ntq_store_dest(c
, &instr
->dest
, 0,
1783 qir_MOV(c
, c
->inputs
[offset
* 4 + comp
]));
1787 case nir_intrinsic_store_output
:
1788 const_offset
= nir_src_as_const_value(instr
->src
[1]);
1789 assert(const_offset
&& "vc4 doesn't support indirect outputs");
1790 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1792 /* MSAA color outputs are the only case where we have an
1793 * output that's not lowered to being a store of a single 32
1796 if (c
->stage
== QSTAGE_FRAG
&& instr
->num_components
== 4) {
1797 assert(offset
== c
->output_color_index
);
1798 for (int i
= 0; i
< 4; i
++) {
1799 c
->sample_colors
[i
] =
1800 qir_MOV(c
, ntq_get_src(c
, instr
->src
[0],
1804 offset
= offset
* 4 + nir_intrinsic_component(instr
);
1805 assert(instr
->num_components
== 1);
1806 c
->outputs
[offset
] =
1807 qir_MOV(c
, ntq_get_src(c
, instr
->src
[0], 0));
1808 c
->num_outputs
= MAX2(c
->num_outputs
, offset
+ 1);
1812 case nir_intrinsic_discard
:
1813 if (c
->execute
.file
!= QFILE_NULL
) {
1814 qir_SF(c
, c
->execute
);
1815 qir_MOV_cond(c
, QPU_COND_ZS
, c
->discard
,
1816 qir_uniform_ui(c
, ~0));
1818 qir_MOV_dest(c
, c
->discard
, qir_uniform_ui(c
, ~0));
1822 case nir_intrinsic_discard_if
: {
1823 /* true (~0) if we're discarding */
1824 struct qreg cond
= ntq_get_src(c
, instr
->src
[0], 0);
1826 if (c
->execute
.file
!= QFILE_NULL
) {
1827 /* execute == 0 means the channel is active. Invert
1828 * the condition so that we can use zero as "executing
1831 qir_SF(c
, qir_AND(c
, c
->execute
, qir_NOT(c
, cond
)));
1832 qir_MOV_cond(c
, QPU_COND_ZS
, c
->discard
, cond
);
1834 qir_OR_dest(c
, c
->discard
, c
->discard
,
1835 ntq_get_src(c
, instr
->src
[0], 0));
1842 fprintf(stderr
, "Unknown intrinsic: ");
1843 nir_print_instr(&instr
->instr
, stderr
);
1844 fprintf(stderr
, "\n");
1849 /* Clears (activates) the execute flags for any channels whose jump target
1850 * matches this block.
1853 ntq_activate_execute_for_block(struct vc4_compile
*c
)
1855 qir_SF(c
, qir_SUB(c
,
1857 qir_uniform_ui(c
, c
->cur_block
->index
)));
1858 qir_MOV_cond(c
, QPU_COND_ZS
, c
->execute
, qir_uniform_ui(c
, 0));
1862 ntq_emit_if(struct vc4_compile
*c
, nir_if
*if_stmt
)
1864 if (!c
->vc4
->screen
->has_control_flow
) {
1866 "IF statement support requires updated kernel.\n");
1870 nir_block
*nir_else_block
= nir_if_first_else_block(if_stmt
);
1871 bool empty_else_block
=
1872 (nir_else_block
== nir_if_last_else_block(if_stmt
) &&
1873 exec_list_is_empty(&nir_else_block
->instr_list
));
1875 struct qblock
*then_block
= qir_new_block(c
);
1876 struct qblock
*after_block
= qir_new_block(c
);
1877 struct qblock
*else_block
;
1878 if (empty_else_block
)
1879 else_block
= after_block
;
1881 else_block
= qir_new_block(c
);
1883 bool was_top_level
= false;
1884 if (c
->execute
.file
== QFILE_NULL
) {
1885 c
->execute
= qir_MOV(c
, qir_uniform_ui(c
, 0));
1886 was_top_level
= true;
1889 /* Set ZS for executing (execute == 0) and jumping (if->condition ==
1890 * 0) channels, and then update execute flags for those to point to
1895 ntq_get_src(c
, if_stmt
->condition
, 0)));
1896 qir_MOV_cond(c
, QPU_COND_ZS
, c
->execute
,
1897 qir_uniform_ui(c
, else_block
->index
));
1899 /* Jump to ELSE if nothing is active for THEN, otherwise fall
1902 qir_SF(c
, c
->execute
);
1903 qir_BRANCH(c
, QPU_COND_BRANCH_ALL_ZC
);
1904 qir_link_blocks(c
->cur_block
, else_block
);
1905 qir_link_blocks(c
->cur_block
, then_block
);
1907 /* Process the THEN block. */
1908 qir_set_emit_block(c
, then_block
);
1909 ntq_emit_cf_list(c
, &if_stmt
->then_list
);
1911 if (!empty_else_block
) {
1912 /* Handle the end of the THEN block. First, all currently
1913 * active channels update their execute flags to point to
1916 qir_SF(c
, c
->execute
);
1917 qir_MOV_cond(c
, QPU_COND_ZS
, c
->execute
,
1918 qir_uniform_ui(c
, after_block
->index
));
1920 /* If everything points at ENDIF, then jump there immediately. */
1921 qir_SF(c
, qir_SUB(c
, c
->execute
, qir_uniform_ui(c
, after_block
->index
)));
1922 qir_BRANCH(c
, QPU_COND_BRANCH_ALL_ZS
);
1923 qir_link_blocks(c
->cur_block
, after_block
);
1924 qir_link_blocks(c
->cur_block
, else_block
);
1926 qir_set_emit_block(c
, else_block
);
1927 ntq_activate_execute_for_block(c
);
1928 ntq_emit_cf_list(c
, &if_stmt
->else_list
);
1931 qir_link_blocks(c
->cur_block
, after_block
);
1933 qir_set_emit_block(c
, after_block
);
1935 c
->execute
= c
->undef
;
1937 ntq_activate_execute_for_block(c
);
1942 ntq_emit_jump(struct vc4_compile
*c
, nir_jump_instr
*jump
)
1944 switch (jump
->type
) {
1945 case nir_jump_break
:
1946 qir_SF(c
, c
->execute
);
1947 qir_MOV_cond(c
, QPU_COND_ZS
, c
->execute
,
1948 qir_uniform_ui(c
, c
->loop_break_block
->index
));
1951 case nir_jump_continue
:
1952 qir_SF(c
, c
->execute
);
1953 qir_MOV_cond(c
, QPU_COND_ZS
, c
->execute
,
1954 qir_uniform_ui(c
, c
->loop_cont_block
->index
));
1957 case nir_jump_return
:
1958 unreachable("All returns shouold be lowered\n");
1963 ntq_emit_instr(struct vc4_compile
*c
, nir_instr
*instr
)
1965 switch (instr
->type
) {
1966 case nir_instr_type_alu
:
1967 ntq_emit_alu(c
, nir_instr_as_alu(instr
));
1970 case nir_instr_type_intrinsic
:
1971 ntq_emit_intrinsic(c
, nir_instr_as_intrinsic(instr
));
1974 case nir_instr_type_load_const
:
1975 ntq_emit_load_const(c
, nir_instr_as_load_const(instr
));
1978 case nir_instr_type_ssa_undef
:
1979 ntq_emit_ssa_undef(c
, nir_instr_as_ssa_undef(instr
));
1982 case nir_instr_type_tex
:
1983 ntq_emit_tex(c
, nir_instr_as_tex(instr
));
1986 case nir_instr_type_jump
:
1987 ntq_emit_jump(c
, nir_instr_as_jump(instr
));
1991 fprintf(stderr
, "Unknown NIR instr type: ");
1992 nir_print_instr(instr
, stderr
);
1993 fprintf(stderr
, "\n");
1999 ntq_emit_block(struct vc4_compile
*c
, nir_block
*block
)
2001 nir_foreach_instr(instr
, block
) {
2002 ntq_emit_instr(c
, instr
);
2006 static void ntq_emit_cf_list(struct vc4_compile
*c
, struct exec_list
*list
);
2009 ntq_emit_loop(struct vc4_compile
*c
, nir_loop
*loop
)
2011 if (!c
->vc4
->screen
->has_control_flow
) {
2013 "loop support requires updated kernel.\n");
2014 ntq_emit_cf_list(c
, &loop
->body
);
2018 bool was_top_level
= false;
2019 if (c
->execute
.file
== QFILE_NULL
) {
2020 c
->execute
= qir_MOV(c
, qir_uniform_ui(c
, 0));
2021 was_top_level
= true;
2024 struct qblock
*save_loop_cont_block
= c
->loop_cont_block
;
2025 struct qblock
*save_loop_break_block
= c
->loop_break_block
;
2027 c
->loop_cont_block
= qir_new_block(c
);
2028 c
->loop_break_block
= qir_new_block(c
);
2030 qir_link_blocks(c
->cur_block
, c
->loop_cont_block
);
2031 qir_set_emit_block(c
, c
->loop_cont_block
);
2032 ntq_activate_execute_for_block(c
);
2034 ntq_emit_cf_list(c
, &loop
->body
);
2036 /* If anything had explicitly continued, or is here at the end of the
2037 * loop, then we need to loop again. SF updates are masked by the
2038 * instruction's condition, so we can do the OR of the two conditions
2041 qir_SF(c
, c
->execute
);
2042 struct qinst
*cont_check
=
2046 qir_uniform_ui(c
, c
->loop_cont_block
->index
));
2047 cont_check
->cond
= QPU_COND_ZC
;
2048 cont_check
->sf
= true;
2050 qir_BRANCH(c
, QPU_COND_BRANCH_ANY_ZS
);
2051 qir_link_blocks(c
->cur_block
, c
->loop_cont_block
);
2052 qir_link_blocks(c
->cur_block
, c
->loop_break_block
);
2054 qir_set_emit_block(c
, c
->loop_break_block
);
2056 c
->execute
= c
->undef
;
2058 ntq_activate_execute_for_block(c
);
2060 c
->loop_break_block
= save_loop_break_block
;
2061 c
->loop_cont_block
= save_loop_cont_block
;
2065 ntq_emit_function(struct vc4_compile
*c
, nir_function_impl
*func
)
2067 fprintf(stderr
, "FUNCTIONS not handled.\n");
2072 ntq_emit_cf_list(struct vc4_compile
*c
, struct exec_list
*list
)
2074 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2075 switch (node
->type
) {
2076 case nir_cf_node_block
:
2077 ntq_emit_block(c
, nir_cf_node_as_block(node
));
2080 case nir_cf_node_if
:
2081 ntq_emit_if(c
, nir_cf_node_as_if(node
));
2084 case nir_cf_node_loop
:
2085 ntq_emit_loop(c
, nir_cf_node_as_loop(node
));
2088 case nir_cf_node_function
:
2089 ntq_emit_function(c
, nir_cf_node_as_function(node
));
2093 fprintf(stderr
, "Unknown NIR node type\n");
2100 ntq_emit_impl(struct vc4_compile
*c
, nir_function_impl
*impl
)
2102 ntq_setup_registers(c
, &impl
->registers
);
2103 ntq_emit_cf_list(c
, &impl
->body
);
2107 nir_to_qir(struct vc4_compile
*c
)
2109 if (c
->stage
== QSTAGE_FRAG
&& c
->s
->info
->fs
.uses_discard
)
2110 c
->discard
= qir_MOV(c
, qir_uniform_ui(c
, 0));
2112 ntq_setup_inputs(c
);
2113 ntq_setup_outputs(c
);
2114 ntq_setup_uniforms(c
);
2115 ntq_setup_registers(c
, &c
->s
->registers
);
2117 /* Find the main function and emit the body. */
2118 nir_foreach_function(function
, c
->s
) {
2119 assert(strcmp(function
->name
, "main") == 0);
2120 assert(function
->impl
);
2121 ntq_emit_impl(c
, function
->impl
);
2125 static const nir_shader_compiler_options nir_options
= {
2126 .lower_extract_byte
= true,
2127 .lower_extract_word
= true,
2129 .lower_flrp32
= true,
2132 .lower_fsqrt
= true,
2133 .lower_negate
= true,
2134 .native_integers
= true,
2138 vc4_screen_get_compiler_options(struct pipe_screen
*pscreen
,
2139 enum pipe_shader_ir ir
, unsigned shader
)
2141 return &nir_options
;
2145 count_nir_instrs(nir_shader
*nir
)
2148 nir_foreach_function(function
, nir
) {
2149 if (!function
->impl
)
2151 nir_foreach_block(block
, function
->impl
) {
2152 nir_foreach_instr(instr
, block
)
2159 static struct vc4_compile
*
2160 vc4_shader_ntq(struct vc4_context
*vc4
, enum qstage stage
,
2161 struct vc4_key
*key
, bool fs_threaded
)
2163 struct vc4_compile
*c
= qir_compile_init();
2167 c
->shader_state
= &key
->shader_state
->base
;
2168 c
->program_id
= key
->shader_state
->program_id
;
2170 p_atomic_inc_return(&key
->shader_state
->compiled_variant_count
);
2171 c
->fs_threaded
= fs_threaded
;
2176 c
->fs_key
= (struct vc4_fs_key
*)key
;
2177 if (c
->fs_key
->is_points
) {
2178 c
->point_x
= emit_fragment_varying(c
, ~0, 0);
2179 c
->point_y
= emit_fragment_varying(c
, ~0, 0);
2180 } else if (c
->fs_key
->is_lines
) {
2181 c
->line_x
= emit_fragment_varying(c
, ~0, 0);
2185 c
->vs_key
= (struct vc4_vs_key
*)key
;
2188 c
->vs_key
= (struct vc4_vs_key
*)key
;
2192 c
->s
= nir_shader_clone(c
, key
->shader_state
->base
.ir
.nir
);
2194 if (stage
== QSTAGE_FRAG
)
2195 NIR_PASS_V(c
->s
, vc4_nir_lower_blend
, c
);
2197 struct nir_lower_tex_options tex_options
= {
2198 /* We would need to implement txs, but we don't want the
2199 * int/float conversions
2201 .lower_rect
= false,
2205 /* Apply swizzles to all samplers. */
2206 .swizzle_result
= ~0,
2209 /* Lower the format swizzle and ARB_texture_swizzle-style swizzle.
2210 * The format swizzling applies before sRGB decode, and
2211 * ARB_texture_swizzle is the last thing before returning the sample.
2213 for (int i
= 0; i
< ARRAY_SIZE(key
->tex
); i
++) {
2214 enum pipe_format format
= c
->key
->tex
[i
].format
;
2219 const uint8_t *format_swizzle
= vc4_get_format_swizzle(format
);
2221 for (int j
= 0; j
< 4; j
++) {
2222 uint8_t arb_swiz
= c
->key
->tex
[i
].swizzle
[j
];
2224 if (arb_swiz
<= 3) {
2225 tex_options
.swizzles
[i
][j
] =
2226 format_swizzle
[arb_swiz
];
2228 tex_options
.swizzles
[i
][j
] = arb_swiz
;
2232 if (util_format_is_srgb(format
))
2233 tex_options
.lower_srgb
|= (1 << i
);
2236 NIR_PASS_V(c
->s
, nir_lower_tex
, &tex_options
);
2238 if (c
->fs_key
&& c
->fs_key
->light_twoside
)
2239 NIR_PASS_V(c
->s
, nir_lower_two_sided_color
);
2241 if (c
->vs_key
&& c
->vs_key
->clamp_color
)
2242 NIR_PASS_V(c
->s
, nir_lower_clamp_color_outputs
);
2244 if (c
->key
->ucp_enables
) {
2245 if (stage
== QSTAGE_FRAG
) {
2246 NIR_PASS_V(c
->s
, nir_lower_clip_fs
, c
->key
->ucp_enables
);
2248 NIR_PASS_V(c
->s
, nir_lower_clip_vs
, c
->key
->ucp_enables
);
2249 NIR_PASS_V(c
->s
, nir_lower_io_to_scalar
,
2250 nir_var_shader_out
);
2254 /* FS input scalarizing must happen after nir_lower_two_sided_color,
2255 * which only handles a vec4 at a time. Similarly, VS output
2256 * scalarizing must happen after nir_lower_clip_vs.
2258 if (c
->stage
== QSTAGE_FRAG
)
2259 NIR_PASS_V(c
->s
, nir_lower_io_to_scalar
, nir_var_shader_in
);
2261 NIR_PASS_V(c
->s
, nir_lower_io_to_scalar
, nir_var_shader_out
);
2263 NIR_PASS_V(c
->s
, vc4_nir_lower_io
, c
);
2264 NIR_PASS_V(c
->s
, vc4_nir_lower_txf_ms
, c
);
2265 NIR_PASS_V(c
->s
, nir_lower_idiv
);
2267 vc4_optimize_nir(c
->s
);
2269 NIR_PASS_V(c
->s
, nir_convert_from_ssa
, true);
2271 if (vc4_debug
& VC4_DEBUG_SHADERDB
) {
2272 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %d NIR instructions\n",
2273 qir_get_stage_name(c
->stage
),
2274 c
->program_id
, c
->variant_id
,
2275 count_nir_instrs(c
->s
));
2278 if (vc4_debug
& VC4_DEBUG_NIR
) {
2279 fprintf(stderr
, "%s prog %d/%d NIR:\n",
2280 qir_get_stage_name(c
->stage
),
2281 c
->program_id
, c
->variant_id
);
2282 nir_print_shader(c
->s
, stderr
);
2289 /* FS threading requires that the thread execute
2290 * QPU_SIG_LAST_THREAD_SWITCH exactly once before terminating
2291 * (with no other THRSW afterwards, obviously). If we didn't
2292 * fetch a texture at a top level block, this wouldn't be
2295 if (c
->fs_threaded
&& !c
->last_thrsw_at_top_level
) {
2304 c
->vs_key
->fs_inputs
->input_slots
,
2305 c
->vs_key
->fs_inputs
->num_inputs
);
2312 if (vc4_debug
& VC4_DEBUG_QIR
) {
2313 fprintf(stderr
, "%s prog %d/%d pre-opt QIR:\n",
2314 qir_get_stage_name(c
->stage
),
2315 c
->program_id
, c
->variant_id
);
2317 fprintf(stderr
, "\n");
2321 qir_lower_uniforms(c
);
2323 qir_schedule_instructions(c
);
2324 qir_emit_uniform_stream_resets(c
);
2326 if (vc4_debug
& VC4_DEBUG_QIR
) {
2327 fprintf(stderr
, "%s prog %d/%d QIR:\n",
2328 qir_get_stage_name(c
->stage
),
2329 c
->program_id
, c
->variant_id
);
2331 fprintf(stderr
, "\n");
2334 qir_reorder_uniforms(c
);
2335 vc4_generate_code(vc4
, c
);
2337 if (vc4_debug
& VC4_DEBUG_SHADERDB
) {
2338 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %d instructions\n",
2339 qir_get_stage_name(c
->stage
),
2340 c
->program_id
, c
->variant_id
,
2342 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %d uniforms\n",
2343 qir_get_stage_name(c
->stage
),
2344 c
->program_id
, c
->variant_id
,
2354 vc4_shader_state_create(struct pipe_context
*pctx
,
2355 const struct pipe_shader_state
*cso
)
2357 struct vc4_context
*vc4
= vc4_context(pctx
);
2358 struct vc4_uncompiled_shader
*so
= CALLOC_STRUCT(vc4_uncompiled_shader
);
2362 so
->program_id
= vc4
->next_uncompiled_program_id
++;
2366 if (cso
->type
== PIPE_SHADER_IR_NIR
) {
2367 /* The backend takes ownership of the NIR shader on state
2372 assert(cso
->type
== PIPE_SHADER_IR_TGSI
);
2374 if (vc4_debug
& VC4_DEBUG_TGSI
) {
2375 fprintf(stderr
, "prog %d TGSI:\n",
2377 tgsi_dump(cso
->tokens
, 0);
2378 fprintf(stderr
, "\n");
2380 s
= tgsi_to_nir(cso
->tokens
, &nir_options
);
2383 NIR_PASS_V(s
, nir_opt_global_to_local
);
2384 NIR_PASS_V(s
, nir_convert_to_ssa
);
2385 NIR_PASS_V(s
, nir_normalize_cubemap_coords
);
2387 NIR_PASS_V(s
, nir_lower_load_const_to_scalar
);
2389 vc4_optimize_nir(s
);
2391 NIR_PASS_V(s
, nir_remove_dead_variables
, nir_var_local
);
2393 /* Garbage collect dead instructions */
2396 so
->base
.type
= PIPE_SHADER_IR_NIR
;
2397 so
->base
.ir
.nir
= s
;
2399 if (vc4_debug
& VC4_DEBUG_NIR
) {
2400 fprintf(stderr
, "%s prog %d NIR:\n",
2401 gl_shader_stage_name(s
->stage
),
2403 nir_print_shader(s
, stderr
);
2404 fprintf(stderr
, "\n");
2411 copy_uniform_state_to_shader(struct vc4_compiled_shader
*shader
,
2412 struct vc4_compile
*c
)
2414 int count
= c
->num_uniforms
;
2415 struct vc4_shader_uniform_info
*uinfo
= &shader
->uniforms
;
2417 uinfo
->count
= count
;
2418 uinfo
->data
= ralloc_array(shader
, uint32_t, count
);
2419 memcpy(uinfo
->data
, c
->uniform_data
,
2420 count
* sizeof(*uinfo
->data
));
2421 uinfo
->contents
= ralloc_array(shader
, enum quniform_contents
, count
);
2422 memcpy(uinfo
->contents
, c
->uniform_contents
,
2423 count
* sizeof(*uinfo
->contents
));
2424 uinfo
->num_texture_samples
= c
->num_texture_samples
;
2426 vc4_set_shader_uniform_dirty_flags(shader
);
2430 vc4_setup_compiled_fs_inputs(struct vc4_context
*vc4
, struct vc4_compile
*c
,
2431 struct vc4_compiled_shader
*shader
)
2433 struct vc4_fs_inputs inputs
;
2435 memset(&inputs
, 0, sizeof(inputs
));
2436 inputs
.input_slots
= ralloc_array(shader
,
2437 struct vc4_varying_slot
,
2438 c
->num_input_slots
);
2440 bool input_live
[c
->num_input_slots
];
2442 memset(input_live
, 0, sizeof(input_live
));
2443 qir_for_each_inst_inorder(inst
, c
) {
2444 for (int i
= 0; i
< qir_get_op_nsrc(inst
->op
); i
++) {
2445 if (inst
->src
[i
].file
== QFILE_VARY
)
2446 input_live
[inst
->src
[i
].index
] = true;
2450 for (int i
= 0; i
< c
->num_input_slots
; i
++) {
2451 struct vc4_varying_slot
*slot
= &c
->input_slots
[i
];
2456 /* Skip non-VS-output inputs. */
2457 if (slot
->slot
== (uint8_t)~0)
2460 if (slot
->slot
== VARYING_SLOT_COL0
||
2461 slot
->slot
== VARYING_SLOT_COL1
||
2462 slot
->slot
== VARYING_SLOT_BFC0
||
2463 slot
->slot
== VARYING_SLOT_BFC1
) {
2464 shader
->color_inputs
|= (1 << inputs
.num_inputs
);
2467 inputs
.input_slots
[inputs
.num_inputs
] = *slot
;
2468 inputs
.num_inputs
++;
2470 shader
->num_inputs
= inputs
.num_inputs
;
2472 /* Add our set of inputs to the set of all inputs seen. This way, we
2473 * can have a single pointer that identifies an FS inputs set,
2474 * allowing VS to avoid recompiling when the FS is recompiled (or a
2475 * new one is bound using separate shader objects) but the inputs
2478 struct set_entry
*entry
= _mesa_set_search(vc4
->fs_inputs_set
, &inputs
);
2480 shader
->fs_inputs
= entry
->key
;
2481 ralloc_free(inputs
.input_slots
);
2483 struct vc4_fs_inputs
*alloc_inputs
;
2485 alloc_inputs
= rzalloc(vc4
->fs_inputs_set
, struct vc4_fs_inputs
);
2486 memcpy(alloc_inputs
, &inputs
, sizeof(inputs
));
2487 ralloc_steal(alloc_inputs
, inputs
.input_slots
);
2488 _mesa_set_add(vc4
->fs_inputs_set
, alloc_inputs
);
2490 shader
->fs_inputs
= alloc_inputs
;
2494 static struct vc4_compiled_shader
*
2495 vc4_get_compiled_shader(struct vc4_context
*vc4
, enum qstage stage
,
2496 struct vc4_key
*key
)
2498 struct hash_table
*ht
;
2502 if (stage
== QSTAGE_FRAG
) {
2504 key_size
= sizeof(struct vc4_fs_key
);
2505 try_threading
= vc4
->screen
->has_threaded_fs
;
2508 key_size
= sizeof(struct vc4_vs_key
);
2509 try_threading
= false;
2512 struct vc4_compiled_shader
*shader
;
2513 struct hash_entry
*entry
= _mesa_hash_table_search(ht
, key
);
2517 struct vc4_compile
*c
= vc4_shader_ntq(vc4
, stage
, key
, try_threading
);
2518 /* If the FS failed to compile threaded, fall back to single threaded. */
2519 if (try_threading
&& c
->failed
) {
2520 qir_compile_destroy(c
);
2521 c
= vc4_shader_ntq(vc4
, stage
, key
, false);
2524 shader
= rzalloc(NULL
, struct vc4_compiled_shader
);
2526 shader
->program_id
= vc4
->next_compiled_program_id
++;
2527 if (stage
== QSTAGE_FRAG
) {
2528 vc4_setup_compiled_fs_inputs(vc4
, c
, shader
);
2530 /* Note: the temporary clone in c->s has been freed. */
2531 nir_shader
*orig_shader
= key
->shader_state
->base
.ir
.nir
;
2532 if (orig_shader
->info
->outputs_written
& (1 << FRAG_RESULT_DEPTH
))
2533 shader
->disable_early_z
= true;
2535 shader
->num_inputs
= c
->num_inputs
;
2537 shader
->vattr_offsets
[0] = 0;
2538 for (int i
= 0; i
< 8; i
++) {
2539 shader
->vattr_offsets
[i
+ 1] =
2540 shader
->vattr_offsets
[i
] + c
->vattr_sizes
[i
];
2542 if (c
->vattr_sizes
[i
])
2543 shader
->vattrs_live
|= (1 << i
);
2547 shader
->failed
= c
->failed
;
2549 shader
->failed
= true;
2551 copy_uniform_state_to_shader(shader
, c
);
2552 shader
->bo
= vc4_bo_alloc_shader(vc4
->screen
, c
->qpu_insts
,
2557 shader
->fs_threaded
= c
->fs_threaded
;
2559 /* Copy the compiler UBO range state to the compiled shader, dropping
2560 * out arrays that were never referenced by an indirect load.
2562 * (Note that QIR dead code elimination of an array access still
2563 * leaves that array alive, though)
2565 if (c
->num_ubo_ranges
) {
2566 shader
->num_ubo_ranges
= c
->num_ubo_ranges
;
2567 shader
->ubo_ranges
= ralloc_array(shader
, struct vc4_ubo_range
,
2570 for (int i
= 0; i
< c
->num_uniform_ranges
; i
++) {
2571 struct vc4_compiler_ubo_range
*range
=
2576 shader
->ubo_ranges
[j
].dst_offset
= range
->dst_offset
;
2577 shader
->ubo_ranges
[j
].src_offset
= range
->src_offset
;
2578 shader
->ubo_ranges
[j
].size
= range
->size
;
2579 shader
->ubo_size
+= c
->ubo_ranges
[i
].size
;
2583 if (shader
->ubo_size
) {
2584 if (vc4_debug
& VC4_DEBUG_SHADERDB
) {
2585 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %d UBO uniforms\n",
2586 qir_get_stage_name(c
->stage
),
2587 c
->program_id
, c
->variant_id
,
2588 shader
->ubo_size
/ 4);
2592 qir_compile_destroy(c
);
2594 struct vc4_key
*dup_key
;
2595 dup_key
= rzalloc_size(shader
, key_size
); /* TODO: don't use rzalloc */
2596 memcpy(dup_key
, key
, key_size
);
2597 _mesa_hash_table_insert(ht
, dup_key
, shader
);
2603 vc4_setup_shared_key(struct vc4_context
*vc4
, struct vc4_key
*key
,
2604 struct vc4_texture_stateobj
*texstate
)
2606 for (int i
= 0; i
< texstate
->num_textures
; i
++) {
2607 struct pipe_sampler_view
*sampler
= texstate
->textures
[i
];
2608 struct vc4_sampler_view
*vc4_sampler
= vc4_sampler_view(sampler
);
2609 struct pipe_sampler_state
*sampler_state
=
2610 texstate
->samplers
[i
];
2615 key
->tex
[i
].format
= sampler
->format
;
2616 key
->tex
[i
].swizzle
[0] = sampler
->swizzle_r
;
2617 key
->tex
[i
].swizzle
[1] = sampler
->swizzle_g
;
2618 key
->tex
[i
].swizzle
[2] = sampler
->swizzle_b
;
2619 key
->tex
[i
].swizzle
[3] = sampler
->swizzle_a
;
2621 if (sampler
->texture
->nr_samples
> 1) {
2622 key
->tex
[i
].msaa_width
= sampler
->texture
->width0
;
2623 key
->tex
[i
].msaa_height
= sampler
->texture
->height0
;
2624 } else if (sampler
){
2625 key
->tex
[i
].compare_mode
= sampler_state
->compare_mode
;
2626 key
->tex
[i
].compare_func
= sampler_state
->compare_func
;
2627 key
->tex
[i
].wrap_s
= sampler_state
->wrap_s
;
2628 key
->tex
[i
].wrap_t
= sampler_state
->wrap_t
;
2629 key
->tex
[i
].force_first_level
=
2630 vc4_sampler
->force_first_level
;
2634 key
->ucp_enables
= vc4
->rasterizer
->base
.clip_plane_enable
;
2638 vc4_update_compiled_fs(struct vc4_context
*vc4
, uint8_t prim_mode
)
2640 struct vc4_job
*job
= vc4
->job
;
2641 struct vc4_fs_key local_key
;
2642 struct vc4_fs_key
*key
= &local_key
;
2644 if (!(vc4
->dirty
& (VC4_DIRTY_PRIM_MODE
|
2646 VC4_DIRTY_FRAMEBUFFER
|
2648 VC4_DIRTY_RASTERIZER
|
2649 VC4_DIRTY_SAMPLE_MASK
|
2651 VC4_DIRTY_UNCOMPILED_FS
))) {
2655 memset(key
, 0, sizeof(*key
));
2656 vc4_setup_shared_key(vc4
, &key
->base
, &vc4
->fragtex
);
2657 key
->base
.shader_state
= vc4
->prog
.bind_fs
;
2658 key
->is_points
= (prim_mode
== PIPE_PRIM_POINTS
);
2659 key
->is_lines
= (prim_mode
>= PIPE_PRIM_LINES
&&
2660 prim_mode
<= PIPE_PRIM_LINE_STRIP
);
2661 key
->blend
= vc4
->blend
->rt
[0];
2662 if (vc4
->blend
->logicop_enable
) {
2663 key
->logicop_func
= vc4
->blend
->logicop_func
;
2665 key
->logicop_func
= PIPE_LOGICOP_COPY
;
2668 key
->msaa
= vc4
->rasterizer
->base
.multisample
;
2669 key
->sample_coverage
= (vc4
->rasterizer
->base
.multisample
&&
2670 vc4
->sample_mask
!= (1 << VC4_MAX_SAMPLES
) - 1);
2671 key
->sample_alpha_to_coverage
= vc4
->blend
->alpha_to_coverage
;
2672 key
->sample_alpha_to_one
= vc4
->blend
->alpha_to_one
;
2675 if (vc4
->framebuffer
.cbufs
[0])
2676 key
->color_format
= vc4
->framebuffer
.cbufs
[0]->format
;
2678 key
->stencil_enabled
= vc4
->zsa
->stencil_uniforms
[0] != 0;
2679 key
->stencil_twoside
= vc4
->zsa
->stencil_uniforms
[1] != 0;
2680 key
->stencil_full_writemasks
= vc4
->zsa
->stencil_uniforms
[2] != 0;
2681 key
->depth_enabled
= (vc4
->zsa
->base
.depth
.enabled
||
2682 key
->stencil_enabled
);
2683 if (vc4
->zsa
->base
.alpha
.enabled
) {
2684 key
->alpha_test
= true;
2685 key
->alpha_test_func
= vc4
->zsa
->base
.alpha
.func
;
2688 if (key
->is_points
) {
2689 key
->point_sprite_mask
=
2690 vc4
->rasterizer
->base
.sprite_coord_enable
;
2691 key
->point_coord_upper_left
=
2692 (vc4
->rasterizer
->base
.sprite_coord_mode
==
2693 PIPE_SPRITE_COORD_UPPER_LEFT
);
2696 key
->light_twoside
= vc4
->rasterizer
->base
.light_twoside
;
2698 struct vc4_compiled_shader
*old_fs
= vc4
->prog
.fs
;
2699 vc4
->prog
.fs
= vc4_get_compiled_shader(vc4
, QSTAGE_FRAG
, &key
->base
);
2700 if (vc4
->prog
.fs
== old_fs
)
2703 vc4
->dirty
|= VC4_DIRTY_COMPILED_FS
;
2705 if (vc4
->rasterizer
->base
.flatshade
&&
2706 old_fs
&& vc4
->prog
.fs
->color_inputs
!= old_fs
->color_inputs
) {
2707 vc4
->dirty
|= VC4_DIRTY_FLAT_SHADE_FLAGS
;
2710 if (old_fs
&& vc4
->prog
.fs
->fs_inputs
!= old_fs
->fs_inputs
)
2711 vc4
->dirty
|= VC4_DIRTY_FS_INPUTS
;
2715 vc4_update_compiled_vs(struct vc4_context
*vc4
, uint8_t prim_mode
)
2717 struct vc4_vs_key local_key
;
2718 struct vc4_vs_key
*key
= &local_key
;
2720 if (!(vc4
->dirty
& (VC4_DIRTY_PRIM_MODE
|
2721 VC4_DIRTY_RASTERIZER
|
2723 VC4_DIRTY_VTXSTATE
|
2724 VC4_DIRTY_UNCOMPILED_VS
|
2725 VC4_DIRTY_FS_INPUTS
))) {
2729 memset(key
, 0, sizeof(*key
));
2730 vc4_setup_shared_key(vc4
, &key
->base
, &vc4
->verttex
);
2731 key
->base
.shader_state
= vc4
->prog
.bind_vs
;
2732 key
->fs_inputs
= vc4
->prog
.fs
->fs_inputs
;
2733 key
->clamp_color
= vc4
->rasterizer
->base
.clamp_vertex_color
;
2735 for (int i
= 0; i
< ARRAY_SIZE(key
->attr_formats
); i
++)
2736 key
->attr_formats
[i
] = vc4
->vtx
->pipe
[i
].src_format
;
2738 key
->per_vertex_point_size
=
2739 (prim_mode
== PIPE_PRIM_POINTS
&&
2740 vc4
->rasterizer
->base
.point_size_per_vertex
);
2742 struct vc4_compiled_shader
*vs
=
2743 vc4_get_compiled_shader(vc4
, QSTAGE_VERT
, &key
->base
);
2744 if (vs
!= vc4
->prog
.vs
) {
2746 vc4
->dirty
|= VC4_DIRTY_COMPILED_VS
;
2749 key
->is_coord
= true;
2750 /* Coord shaders don't care what the FS inputs are. */
2751 key
->fs_inputs
= NULL
;
2752 struct vc4_compiled_shader
*cs
=
2753 vc4_get_compiled_shader(vc4
, QSTAGE_COORD
, &key
->base
);
2754 if (cs
!= vc4
->prog
.cs
) {
2756 vc4
->dirty
|= VC4_DIRTY_COMPILED_CS
;
2761 vc4_update_compiled_shaders(struct vc4_context
*vc4
, uint8_t prim_mode
)
2763 vc4_update_compiled_fs(vc4
, prim_mode
);
2764 vc4_update_compiled_vs(vc4
, prim_mode
);
2766 return !(vc4
->prog
.cs
->failed
||
2767 vc4
->prog
.vs
->failed
||
2768 vc4
->prog
.fs
->failed
);
2772 fs_cache_hash(const void *key
)
2774 return _mesa_hash_data(key
, sizeof(struct vc4_fs_key
));
2778 vs_cache_hash(const void *key
)
2780 return _mesa_hash_data(key
, sizeof(struct vc4_vs_key
));
2784 fs_cache_compare(const void *key1
, const void *key2
)
2786 return memcmp(key1
, key2
, sizeof(struct vc4_fs_key
)) == 0;
2790 vs_cache_compare(const void *key1
, const void *key2
)
2792 return memcmp(key1
, key2
, sizeof(struct vc4_vs_key
)) == 0;
2796 fs_inputs_hash(const void *key
)
2798 const struct vc4_fs_inputs
*inputs
= key
;
2800 return _mesa_hash_data(inputs
->input_slots
,
2801 sizeof(*inputs
->input_slots
) *
2802 inputs
->num_inputs
);
2806 fs_inputs_compare(const void *key1
, const void *key2
)
2808 const struct vc4_fs_inputs
*inputs1
= key1
;
2809 const struct vc4_fs_inputs
*inputs2
= key2
;
2811 return (inputs1
->num_inputs
== inputs2
->num_inputs
&&
2812 memcmp(inputs1
->input_slots
,
2813 inputs2
->input_slots
,
2814 sizeof(*inputs1
->input_slots
) *
2815 inputs1
->num_inputs
) == 0);
2819 delete_from_cache_if_matches(struct hash_table
*ht
,
2820 struct hash_entry
*entry
,
2821 struct vc4_uncompiled_shader
*so
)
2823 const struct vc4_key
*key
= entry
->key
;
2825 if (key
->shader_state
== so
) {
2826 struct vc4_compiled_shader
*shader
= entry
->data
;
2827 _mesa_hash_table_remove(ht
, entry
);
2828 vc4_bo_unreference(&shader
->bo
);
2829 ralloc_free(shader
);
2834 vc4_shader_state_delete(struct pipe_context
*pctx
, void *hwcso
)
2836 struct vc4_context
*vc4
= vc4_context(pctx
);
2837 struct vc4_uncompiled_shader
*so
= hwcso
;
2839 struct hash_entry
*entry
;
2840 hash_table_foreach(vc4
->fs_cache
, entry
)
2841 delete_from_cache_if_matches(vc4
->fs_cache
, entry
, so
);
2842 hash_table_foreach(vc4
->vs_cache
, entry
)
2843 delete_from_cache_if_matches(vc4
->vs_cache
, entry
, so
);
2845 ralloc_free(so
->base
.ir
.nir
);
2850 vc4_fp_state_bind(struct pipe_context
*pctx
, void *hwcso
)
2852 struct vc4_context
*vc4
= vc4_context(pctx
);
2853 vc4
->prog
.bind_fs
= hwcso
;
2854 vc4
->dirty
|= VC4_DIRTY_UNCOMPILED_FS
;
2858 vc4_vp_state_bind(struct pipe_context
*pctx
, void *hwcso
)
2860 struct vc4_context
*vc4
= vc4_context(pctx
);
2861 vc4
->prog
.bind_vs
= hwcso
;
2862 vc4
->dirty
|= VC4_DIRTY_UNCOMPILED_VS
;
2866 vc4_program_init(struct pipe_context
*pctx
)
2868 struct vc4_context
*vc4
= vc4_context(pctx
);
2870 pctx
->create_vs_state
= vc4_shader_state_create
;
2871 pctx
->delete_vs_state
= vc4_shader_state_delete
;
2873 pctx
->create_fs_state
= vc4_shader_state_create
;
2874 pctx
->delete_fs_state
= vc4_shader_state_delete
;
2876 pctx
->bind_fs_state
= vc4_fp_state_bind
;
2877 pctx
->bind_vs_state
= vc4_vp_state_bind
;
2879 vc4
->fs_cache
= _mesa_hash_table_create(pctx
, fs_cache_hash
,
2881 vc4
->vs_cache
= _mesa_hash_table_create(pctx
, vs_cache_hash
,
2883 vc4
->fs_inputs_set
= _mesa_set_create(pctx
, fs_inputs_hash
,
2888 vc4_program_fini(struct pipe_context
*pctx
)
2890 struct vc4_context
*vc4
= vc4_context(pctx
);
2892 struct hash_entry
*entry
;
2893 hash_table_foreach(vc4
->fs_cache
, entry
) {
2894 struct vc4_compiled_shader
*shader
= entry
->data
;
2895 vc4_bo_unreference(&shader
->bo
);
2896 ralloc_free(shader
);
2897 _mesa_hash_table_remove(vc4
->fs_cache
, entry
);
2900 hash_table_foreach(vc4
->vs_cache
, entry
) {
2901 struct vc4_compiled_shader
*shader
= entry
->data
;
2902 vc4_bo_unreference(&shader
->bo
);
2903 ralloc_free(shader
);
2904 _mesa_hash_table_remove(vc4
->vs_cache
, entry
);