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3056c6736af0515a456e024ebf28cb688fb6d969
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "pipe/p_state.h"
27 #include "util/u_format.h"
28 #include "util/u_hash_table.h"
29 #include "util/u_hash.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include "util/format_srgb.h"
33 #include "util/ralloc.h"
34 #include "util/hash_table.h"
35 #include "tgsi/tgsi_dump.h"
36 #include "tgsi/tgsi_info.h"
37 #include "tgsi/tgsi_lowering.h"
38
39 #include "vc4_context.h"
40 #include "vc4_qpu.h"
41 #include "vc4_qir.h"
42 #ifdef USE_VC4_SIMULATOR
43 #include "simpenrose/simpenrose.h"
44 #endif
45
46 struct vc4_key {
47 struct vc4_uncompiled_shader *shader_state;
48 struct {
49 enum pipe_format format;
50 unsigned compare_mode:1;
51 unsigned compare_func:3;
52 unsigned wrap_s:3;
53 unsigned wrap_t:3;
54 uint8_t swizzle[4];
55 } tex[VC4_MAX_TEXTURE_SAMPLERS];
56 };
57
58 struct vc4_fs_key {
59 struct vc4_key base;
60 enum pipe_format color_format;
61 bool depth_enabled;
62 bool stencil_enabled;
63 bool stencil_twoside;
64 bool stencil_full_writemasks;
65 bool is_points;
66 bool is_lines;
67 bool alpha_test;
68 bool point_coord_upper_left;
69 bool light_twoside;
70 uint8_t alpha_test_func;
71 uint32_t point_sprite_mask;
72
73 struct pipe_rt_blend_state blend;
74 };
75
76 struct vc4_vs_key {
77 struct vc4_key base;
78
79 /**
80 * This is a proxy for the array of FS input semantics, which is
81 * larger than we would want to put in the key.
82 */
83 uint64_t compiled_fs_id;
84
85 enum pipe_format attr_formats[8];
86 bool is_coord;
87 bool per_vertex_point_size;
88 };
89
90 static void
91 resize_qreg_array(struct vc4_compile *c,
92 struct qreg **regs,
93 uint32_t *size,
94 uint32_t decl_size)
95 {
96 if (*size >= decl_size)
97 return;
98
99 uint32_t old_size = *size;
100 *size = MAX2(*size * 2, decl_size);
101 *regs = reralloc(c, *regs, struct qreg, *size);
102 if (!*regs) {
103 fprintf(stderr, "Malloc failure\n");
104 abort();
105 }
106
107 for (uint32_t i = old_size; i < *size; i++)
108 (*regs)[i] = c->undef;
109 }
110
111 static struct qreg
112 add_uniform(struct vc4_compile *c,
113 enum quniform_contents contents,
114 uint32_t data)
115 {
116 uint32_t uniform = c->num_uniforms++;
117 struct qreg u = { QFILE_UNIF, uniform };
118
119 if (uniform >= c->uniform_array_size) {
120 c->uniform_array_size = MAX2(MAX2(16, uniform + 1),
121 c->uniform_array_size * 2);
122
123 c->uniform_data = reralloc(c, c->uniform_data,
124 uint32_t,
125 c->uniform_array_size);
126 c->uniform_contents = reralloc(c, c->uniform_contents,
127 enum quniform_contents,
128 c->uniform_array_size);
129 }
130
131 c->uniform_contents[uniform] = contents;
132 c->uniform_data[uniform] = data;
133
134 return u;
135 }
136
137 static struct qreg
138 get_temp_for_uniform(struct vc4_compile *c, enum quniform_contents contents,
139 uint32_t data)
140 {
141 struct qreg u = add_uniform(c, contents, data);
142 struct qreg t = qir_MOV(c, u);
143 return t;
144 }
145
146 static struct qreg
147 qir_uniform_ui(struct vc4_compile *c, uint32_t ui)
148 {
149 return get_temp_for_uniform(c, QUNIFORM_CONSTANT, ui);
150 }
151
152 static struct qreg
153 qir_uniform_f(struct vc4_compile *c, float f)
154 {
155 return qir_uniform_ui(c, fui(f));
156 }
157
158 static struct qreg
159 get_src(struct vc4_compile *c, unsigned tgsi_op,
160 struct tgsi_src_register *src, int i)
161 {
162 struct qreg r = c->undef;
163
164 uint32_t s = i;
165 switch (i) {
166 case TGSI_SWIZZLE_X:
167 s = src->SwizzleX;
168 break;
169 case TGSI_SWIZZLE_Y:
170 s = src->SwizzleY;
171 break;
172 case TGSI_SWIZZLE_Z:
173 s = src->SwizzleZ;
174 break;
175 case TGSI_SWIZZLE_W:
176 s = src->SwizzleW;
177 break;
178 default:
179 abort();
180 }
181
182 assert(!src->Indirect);
183
184 switch (src->File) {
185 case TGSI_FILE_NULL:
186 return r;
187 case TGSI_FILE_TEMPORARY:
188 r = c->temps[src->Index * 4 + s];
189 break;
190 case TGSI_FILE_IMMEDIATE:
191 r = c->consts[src->Index * 4 + s];
192 break;
193 case TGSI_FILE_CONSTANT:
194 r = get_temp_for_uniform(c, QUNIFORM_UNIFORM,
195 src->Index * 4 + s);
196 break;
197 case TGSI_FILE_INPUT:
198 r = c->inputs[src->Index * 4 + s];
199 break;
200 case TGSI_FILE_SAMPLER:
201 case TGSI_FILE_SAMPLER_VIEW:
202 r = c->undef;
203 break;
204 default:
205 fprintf(stderr, "unknown src file %d\n", src->File);
206 abort();
207 }
208
209 if (src->Absolute)
210 r = qir_FMAXABS(c, r, r);
211
212 if (src->Negate) {
213 switch (tgsi_opcode_infer_src_type(tgsi_op)) {
214 case TGSI_TYPE_SIGNED:
215 case TGSI_TYPE_UNSIGNED:
216 r = qir_SUB(c, qir_uniform_ui(c, 0), r);
217 break;
218 default:
219 r = qir_FSUB(c, qir_uniform_f(c, 0.0), r);
220 break;
221 }
222 }
223
224 return r;
225 };
226
227
228 static void
229 update_dst(struct vc4_compile *c, struct tgsi_full_instruction *tgsi_inst,
230 int i, struct qreg val)
231 {
232 struct tgsi_dst_register *tgsi_dst = &tgsi_inst->Dst[0].Register;
233
234 assert(!tgsi_dst->Indirect);
235
236 switch (tgsi_dst->File) {
237 case TGSI_FILE_TEMPORARY:
238 c->temps[tgsi_dst->Index * 4 + i] = val;
239 break;
240 case TGSI_FILE_OUTPUT:
241 c->outputs[tgsi_dst->Index * 4 + i] = val;
242 c->num_outputs = MAX2(c->num_outputs,
243 tgsi_dst->Index * 4 + i + 1);
244 break;
245 default:
246 fprintf(stderr, "unknown dst file %d\n", tgsi_dst->File);
247 abort();
248 }
249 };
250
251 static struct qreg
252 get_swizzled_channel(struct vc4_compile *c,
253 struct qreg *srcs, int swiz)
254 {
255 switch (swiz) {
256 default:
257 case UTIL_FORMAT_SWIZZLE_NONE:
258 fprintf(stderr, "warning: unknown swizzle\n");
259 /* FALLTHROUGH */
260 case UTIL_FORMAT_SWIZZLE_0:
261 return qir_uniform_f(c, 0.0);
262 case UTIL_FORMAT_SWIZZLE_1:
263 return qir_uniform_f(c, 1.0);
264 case UTIL_FORMAT_SWIZZLE_X:
265 case UTIL_FORMAT_SWIZZLE_Y:
266 case UTIL_FORMAT_SWIZZLE_Z:
267 case UTIL_FORMAT_SWIZZLE_W:
268 return srcs[swiz];
269 }
270 }
271
272 static struct qreg
273 tgsi_to_qir_alu(struct vc4_compile *c,
274 struct tgsi_full_instruction *tgsi_inst,
275 enum qop op, struct qreg *src, int i)
276 {
277 struct qreg dst = qir_get_temp(c);
278 qir_emit(c, qir_inst4(op, dst,
279 src[0 * 4 + i],
280 src[1 * 4 + i],
281 src[2 * 4 + i],
282 c->undef));
283 return dst;
284 }
285
286 static struct qreg
287 tgsi_to_qir_scalar(struct vc4_compile *c,
288 struct tgsi_full_instruction *tgsi_inst,
289 enum qop op, struct qreg *src, int i)
290 {
291 struct qreg dst = qir_get_temp(c);
292 qir_emit(c, qir_inst(op, dst,
293 src[0 * 4 + 0],
294 c->undef));
295 return dst;
296 }
297
298 static struct qreg
299 qir_srgb_decode(struct vc4_compile *c, struct qreg srgb)
300 {
301 struct qreg low = qir_FMUL(c, srgb, qir_uniform_f(c, 1.0 / 12.92));
302 struct qreg high = qir_POW(c,
303 qir_FMUL(c,
304 qir_FADD(c,
305 srgb,
306 qir_uniform_f(c, 0.055)),
307 qir_uniform_f(c, 1.0 / 1.055)),
308 qir_uniform_f(c, 2.4));
309
310 qir_SF(c, qir_FSUB(c, srgb, qir_uniform_f(c, 0.04045)));
311 return qir_SEL_X_Y_NS(c, low, high);
312 }
313
314 static struct qreg
315 qir_srgb_encode(struct vc4_compile *c, struct qreg linear)
316 {
317 struct qreg low = qir_FMUL(c, linear, qir_uniform_f(c, 12.92));
318 struct qreg high = qir_FSUB(c,
319 qir_FMUL(c,
320 qir_uniform_f(c, 1.055),
321 qir_POW(c,
322 linear,
323 qir_uniform_f(c, 0.41666))),
324 qir_uniform_f(c, 0.055));
325
326 qir_SF(c, qir_FSUB(c, linear, qir_uniform_f(c, 0.0031308)));
327 return qir_SEL_X_Y_NS(c, low, high);
328 }
329
330 static struct qreg
331 tgsi_to_qir_umul(struct vc4_compile *c,
332 struct tgsi_full_instruction *tgsi_inst,
333 enum qop op, struct qreg *src, int i)
334 {
335 struct qreg src0_hi = qir_SHR(c, src[0 * 4 + i],
336 qir_uniform_ui(c, 16));
337 struct qreg src0_lo = qir_AND(c, src[0 * 4 + i],
338 qir_uniform_ui(c, 0xffff));
339 struct qreg src1_hi = qir_SHR(c, src[1 * 4 + i],
340 qir_uniform_ui(c, 16));
341 struct qreg src1_lo = qir_AND(c, src[1 * 4 + i],
342 qir_uniform_ui(c, 0xffff));
343
344 struct qreg hilo = qir_MUL24(c, src0_hi, src1_lo);
345 struct qreg lohi = qir_MUL24(c, src0_lo, src1_hi);
346 struct qreg lolo = qir_MUL24(c, src0_lo, src1_lo);
347
348 return qir_ADD(c, lolo, qir_SHL(c,
349 qir_ADD(c, hilo, lohi),
350 qir_uniform_ui(c, 16)));
351 }
352
353 static struct qreg
354 tgsi_to_qir_idiv(struct vc4_compile *c,
355 struct tgsi_full_instruction *tgsi_inst,
356 enum qop op, struct qreg *src, int i)
357 {
358 return qir_FTOI(c, qir_FMUL(c,
359 qir_ITOF(c, src[0 * 4 + i]),
360 qir_RCP(c, qir_ITOF(c, src[1 * 4 + i]))));
361 }
362
363 static struct qreg
364 tgsi_to_qir_ineg(struct vc4_compile *c,
365 struct tgsi_full_instruction *tgsi_inst,
366 enum qop op, struct qreg *src, int i)
367 {
368 return qir_SUB(c, qir_uniform_ui(c, 0), src[0 * 4 + i]);
369 }
370
371 static struct qreg
372 tgsi_to_qir_seq(struct vc4_compile *c,
373 struct tgsi_full_instruction *tgsi_inst,
374 enum qop op, struct qreg *src, int i)
375 {
376 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
377 return qir_SEL_X_0_ZS(c, qir_uniform_f(c, 1.0));
378 }
379
380 static struct qreg
381 tgsi_to_qir_sne(struct vc4_compile *c,
382 struct tgsi_full_instruction *tgsi_inst,
383 enum qop op, struct qreg *src, int i)
384 {
385 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
386 return qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0));
387 }
388
389 static struct qreg
390 tgsi_to_qir_slt(struct vc4_compile *c,
391 struct tgsi_full_instruction *tgsi_inst,
392 enum qop op, struct qreg *src, int i)
393 {
394 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
395 return qir_SEL_X_0_NS(c, qir_uniform_f(c, 1.0));
396 }
397
398 static struct qreg
399 tgsi_to_qir_sge(struct vc4_compile *c,
400 struct tgsi_full_instruction *tgsi_inst,
401 enum qop op, struct qreg *src, int i)
402 {
403 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
404 return qir_SEL_X_0_NC(c, qir_uniform_f(c, 1.0));
405 }
406
407 static struct qreg
408 tgsi_to_qir_fseq(struct vc4_compile *c,
409 struct tgsi_full_instruction *tgsi_inst,
410 enum qop op, struct qreg *src, int i)
411 {
412 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
413 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
414 }
415
416 static struct qreg
417 tgsi_to_qir_fsne(struct vc4_compile *c,
418 struct tgsi_full_instruction *tgsi_inst,
419 enum qop op, struct qreg *src, int i)
420 {
421 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
422 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
423 }
424
425 static struct qreg
426 tgsi_to_qir_fslt(struct vc4_compile *c,
427 struct tgsi_full_instruction *tgsi_inst,
428 enum qop op, struct qreg *src, int i)
429 {
430 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
431 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
432 }
433
434 static struct qreg
435 tgsi_to_qir_fsge(struct vc4_compile *c,
436 struct tgsi_full_instruction *tgsi_inst,
437 enum qop op, struct qreg *src, int i)
438 {
439 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
440 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
441 }
442
443 static struct qreg
444 tgsi_to_qir_useq(struct vc4_compile *c,
445 struct tgsi_full_instruction *tgsi_inst,
446 enum qop op, struct qreg *src, int i)
447 {
448 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
449 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
450 }
451
452 static struct qreg
453 tgsi_to_qir_usne(struct vc4_compile *c,
454 struct tgsi_full_instruction *tgsi_inst,
455 enum qop op, struct qreg *src, int i)
456 {
457 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
458 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
459 }
460
461 static struct qreg
462 tgsi_to_qir_islt(struct vc4_compile *c,
463 struct tgsi_full_instruction *tgsi_inst,
464 enum qop op, struct qreg *src, int i)
465 {
466 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
467 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
468 }
469
470 static struct qreg
471 tgsi_to_qir_isge(struct vc4_compile *c,
472 struct tgsi_full_instruction *tgsi_inst,
473 enum qop op, struct qreg *src, int i)
474 {
475 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
476 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
477 }
478
479 static struct qreg
480 tgsi_to_qir_cmp(struct vc4_compile *c,
481 struct tgsi_full_instruction *tgsi_inst,
482 enum qop op, struct qreg *src, int i)
483 {
484 qir_SF(c, src[0 * 4 + i]);
485 return qir_SEL_X_Y_NS(c,
486 src[1 * 4 + i],
487 src[2 * 4 + i]);
488 }
489
490 static struct qreg
491 tgsi_to_qir_mad(struct vc4_compile *c,
492 struct tgsi_full_instruction *tgsi_inst,
493 enum qop op, struct qreg *src, int i)
494 {
495 return qir_FADD(c,
496 qir_FMUL(c,
497 src[0 * 4 + i],
498 src[1 * 4 + i]),
499 src[2 * 4 + i]);
500 }
501
502 static struct qreg
503 tgsi_to_qir_lrp(struct vc4_compile *c,
504 struct tgsi_full_instruction *tgsi_inst,
505 enum qop op, struct qreg *src, int i)
506 {
507 struct qreg src0 = src[0 * 4 + i];
508 struct qreg src1 = src[1 * 4 + i];
509 struct qreg src2 = src[2 * 4 + i];
510
511 /* LRP is:
512 * src0 * src1 + (1 - src0) * src2.
513 * -> src0 * src1 + src2 - src0 * src2
514 * -> src2 + src0 * (src1 - src2)
515 */
516 return qir_FADD(c, src2, qir_FMUL(c, src0, qir_FSUB(c, src1, src2)));
517
518 }
519
520 static void
521 tgsi_to_qir_tex(struct vc4_compile *c,
522 struct tgsi_full_instruction *tgsi_inst,
523 enum qop op, struct qreg *src)
524 {
525 assert(!tgsi_inst->Instruction.Saturate);
526
527 struct qreg s = src[0 * 4 + 0];
528 struct qreg t = src[0 * 4 + 1];
529 struct qreg r = src[0 * 4 + 2];
530 uint32_t unit = tgsi_inst->Src[1].Register.Index;
531 bool is_txl = tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL;
532
533 struct qreg proj = c->undef;
534 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
535 proj = qir_RCP(c, src[0 * 4 + 3]);
536 s = qir_FMUL(c, s, proj);
537 t = qir_FMUL(c, t, proj);
538 }
539
540 struct qreg texture_u[] = {
541 add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit),
542 add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
543 add_uniform(c, QUNIFORM_CONSTANT, 0),
544 add_uniform(c, QUNIFORM_CONSTANT, 0),
545 };
546 uint32_t next_texture_u = 0;
547
548 /* There is no native support for GL texture rectangle coordinates, so
549 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
550 * 1]).
551 */
552 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_RECT ||
553 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT) {
554 s = qir_FMUL(c, s,
555 get_temp_for_uniform(c,
556 QUNIFORM_TEXRECT_SCALE_X,
557 unit));
558 t = qir_FMUL(c, t,
559 get_temp_for_uniform(c,
560 QUNIFORM_TEXRECT_SCALE_Y,
561 unit));
562 }
563
564 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
565 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
566 is_txl) {
567 texture_u[2] = add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P2,
568 unit | (is_txl << 16));
569 }
570
571 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
572 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE) {
573 struct qreg ma = qir_FMAXABS(c, qir_FMAXABS(c, s, t), r);
574 struct qreg rcp_ma = qir_RCP(c, ma);
575 s = qir_FMUL(c, s, rcp_ma);
576 t = qir_FMUL(c, t, rcp_ma);
577 r = qir_FMUL(c, r, rcp_ma);
578
579 qir_TEX_R(c, r, texture_u[next_texture_u++]);
580 } else if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
581 c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP ||
582 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
583 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
584 qir_TEX_R(c, get_temp_for_uniform(c, QUNIFORM_TEXTURE_BORDER_COLOR, unit),
585 texture_u[next_texture_u++]);
586 }
587
588 if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP) {
589 s = qir_FMIN(c, qir_FMAX(c, s, qir_uniform_f(c, 0.0)),
590 qir_uniform_f(c, 1.0));
591 }
592
593 if (c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
594 t = qir_FMIN(c, qir_FMAX(c, t, qir_uniform_f(c, 0.0)),
595 qir_uniform_f(c, 1.0));
596 }
597
598 qir_TEX_T(c, t, texture_u[next_texture_u++]);
599
600 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
601 tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL)
602 qir_TEX_B(c, src[0 * 4 + 3], texture_u[next_texture_u++]);
603
604 qir_TEX_S(c, s, texture_u[next_texture_u++]);
605
606 c->num_texture_samples++;
607 struct qreg r4 = qir_TEX_RESULT(c);
608
609 enum pipe_format format = c->key->tex[unit].format;
610
611 struct qreg unpacked[4];
612 if (util_format_is_depth_or_stencil(format)) {
613 struct qreg depthf = qir_ITOF(c, qir_SHR(c, r4,
614 qir_uniform_ui(c, 8)));
615 struct qreg normalized = qir_FMUL(c, depthf,
616 qir_uniform_f(c, 1.0f/0xffffff));
617
618 struct qreg depth_output;
619
620 struct qreg one = qir_uniform_f(c, 1.0f);
621 if (c->key->tex[unit].compare_mode) {
622 struct qreg compare = src[0 * 4 + 2];
623
624 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP)
625 compare = qir_FMUL(c, compare, proj);
626
627 switch (c->key->tex[unit].compare_func) {
628 case PIPE_FUNC_NEVER:
629 depth_output = qir_uniform_f(c, 0.0f);
630 break;
631 case PIPE_FUNC_ALWAYS:
632 depth_output = one;
633 break;
634 case PIPE_FUNC_EQUAL:
635 qir_SF(c, qir_FSUB(c, compare, normalized));
636 depth_output = qir_SEL_X_0_ZS(c, one);
637 break;
638 case PIPE_FUNC_NOTEQUAL:
639 qir_SF(c, qir_FSUB(c, compare, normalized));
640 depth_output = qir_SEL_X_0_ZC(c, one);
641 break;
642 case PIPE_FUNC_GREATER:
643 qir_SF(c, qir_FSUB(c, compare, normalized));
644 depth_output = qir_SEL_X_0_NC(c, one);
645 break;
646 case PIPE_FUNC_GEQUAL:
647 qir_SF(c, qir_FSUB(c, normalized, compare));
648 depth_output = qir_SEL_X_0_NS(c, one);
649 break;
650 case PIPE_FUNC_LESS:
651 qir_SF(c, qir_FSUB(c, compare, normalized));
652 depth_output = qir_SEL_X_0_NS(c, one);
653 break;
654 case PIPE_FUNC_LEQUAL:
655 qir_SF(c, qir_FSUB(c, normalized, compare));
656 depth_output = qir_SEL_X_0_NC(c, one);
657 break;
658 }
659 } else {
660 depth_output = normalized;
661 }
662
663 for (int i = 0; i < 4; i++)
664 unpacked[i] = depth_output;
665 } else {
666 for (int i = 0; i < 4; i++)
667 unpacked[i] = qir_R4_UNPACK(c, r4, i);
668 }
669
670 const uint8_t *format_swiz = vc4_get_format_swizzle(format);
671 struct qreg texture_output[4];
672 for (int i = 0; i < 4; i++) {
673 texture_output[i] = get_swizzled_channel(c, unpacked,
674 format_swiz[i]);
675 }
676
677 if (util_format_is_srgb(format)) {
678 for (int i = 0; i < 3; i++)
679 texture_output[i] = qir_srgb_decode(c,
680 texture_output[i]);
681 }
682
683 for (int i = 0; i < 4; i++) {
684 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
685 continue;
686
687 update_dst(c, tgsi_inst, i,
688 get_swizzled_channel(c, texture_output,
689 c->key->tex[unit].swizzle[i]));
690 }
691 }
692
693 static struct qreg
694 tgsi_to_qir_trunc(struct vc4_compile *c,
695 struct tgsi_full_instruction *tgsi_inst,
696 enum qop op, struct qreg *src, int i)
697 {
698 return qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
699 }
700
701 /**
702 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
703 * to zero).
704 */
705 static struct qreg
706 tgsi_to_qir_frc(struct vc4_compile *c,
707 struct tgsi_full_instruction *tgsi_inst,
708 enum qop op, struct qreg *src, int i)
709 {
710 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
711 struct qreg diff = qir_FSUB(c, src[0 * 4 + i], trunc);
712 qir_SF(c, diff);
713 return qir_SEL_X_Y_NS(c,
714 qir_FADD(c, diff, qir_uniform_f(c, 1.0)),
715 diff);
716 }
717
718 /**
719 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
720 * zero).
721 */
722 static struct qreg
723 tgsi_to_qir_flr(struct vc4_compile *c,
724 struct tgsi_full_instruction *tgsi_inst,
725 enum qop op, struct qreg *src, int i)
726 {
727 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
728
729 /* This will be < 0 if we truncated and the truncation was of a value
730 * that was < 0 in the first place.
731 */
732 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], trunc));
733
734 return qir_SEL_X_Y_NS(c,
735 qir_FSUB(c, trunc, qir_uniform_f(c, 1.0)),
736 trunc);
737 }
738
739 /**
740 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
741 * zero).
742 */
743 static struct qreg
744 tgsi_to_qir_ceil(struct vc4_compile *c,
745 struct tgsi_full_instruction *tgsi_inst,
746 enum qop op, struct qreg *src, int i)
747 {
748 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
749
750 /* This will be < 0 if we truncated and the truncation was of a value
751 * that was > 0 in the first place.
752 */
753 qir_SF(c, qir_FSUB(c, trunc, src[0 * 4 + i]));
754
755 return qir_SEL_X_Y_NS(c,
756 qir_FADD(c, trunc, qir_uniform_f(c, 1.0)),
757 trunc);
758 }
759
760 static struct qreg
761 tgsi_to_qir_abs(struct vc4_compile *c,
762 struct tgsi_full_instruction *tgsi_inst,
763 enum qop op, struct qreg *src, int i)
764 {
765 struct qreg arg = src[0 * 4 + i];
766 return qir_FMAXABS(c, arg, arg);
767 }
768
769 /* Note that this instruction replicates its result from the x channel */
770 static struct qreg
771 tgsi_to_qir_sin(struct vc4_compile *c,
772 struct tgsi_full_instruction *tgsi_inst,
773 enum qop op, struct qreg *src, int i)
774 {
775 float coeff[] = {
776 -2.0 * M_PI,
777 pow(2.0 * M_PI, 3) / (3 * 2 * 1),
778 -pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
779 pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
780 -pow(2.0 * M_PI, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
781 };
782
783 struct qreg scaled_x =
784 qir_FMUL(c,
785 src[0 * 4 + 0],
786 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
787
788 struct qreg x = qir_FADD(c,
789 tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0),
790 qir_uniform_f(c, -0.5));
791 struct qreg x2 = qir_FMUL(c, x, x);
792 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
793 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
794 x = qir_FMUL(c, x, x2);
795 sum = qir_FADD(c,
796 sum,
797 qir_FMUL(c,
798 x,
799 qir_uniform_f(c, coeff[i])));
800 }
801 return sum;
802 }
803
804 /* Note that this instruction replicates its result from the x channel */
805 static struct qreg
806 tgsi_to_qir_cos(struct vc4_compile *c,
807 struct tgsi_full_instruction *tgsi_inst,
808 enum qop op, struct qreg *src, int i)
809 {
810 float coeff[] = {
811 -1.0f,
812 pow(2.0 * M_PI, 2) / (2 * 1),
813 -pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
814 pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
815 -pow(2.0 * M_PI, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
816 pow(2.0 * M_PI, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
817 };
818
819 struct qreg scaled_x =
820 qir_FMUL(c, src[0 * 4 + 0],
821 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
822 struct qreg x_frac = qir_FADD(c,
823 tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0),
824 qir_uniform_f(c, -0.5));
825
826 struct qreg sum = qir_uniform_f(c, coeff[0]);
827 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
828 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
829 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
830 if (i != 1)
831 x = qir_FMUL(c, x, x2);
832
833 struct qreg mul = qir_FMUL(c,
834 x,
835 qir_uniform_f(c, coeff[i]));
836 if (i == 0)
837 sum = mul;
838 else
839 sum = qir_FADD(c, sum, mul);
840 }
841 return sum;
842 }
843
844 static struct qreg
845 tgsi_to_qir_clamp(struct vc4_compile *c,
846 struct tgsi_full_instruction *tgsi_inst,
847 enum qop op, struct qreg *src, int i)
848 {
849 return qir_FMAX(c, qir_FMIN(c,
850 src[0 * 4 + i],
851 src[2 * 4 + i]),
852 src[1 * 4 + i]);
853 }
854
855 static struct qreg
856 tgsi_to_qir_ssg(struct vc4_compile *c,
857 struct tgsi_full_instruction *tgsi_inst,
858 enum qop op, struct qreg *src, int i)
859 {
860 qir_SF(c, src[0 * 4 + i]);
861 return qir_SEL_X_Y_NC(c,
862 qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0)),
863 qir_uniform_f(c, -1.0));
864 }
865
866 static void
867 emit_vertex_input(struct vc4_compile *c, int attr)
868 {
869 enum pipe_format format = c->vs_key->attr_formats[attr];
870 struct qreg vpm_reads[4];
871
872 /* Right now, we're setting the VPM offsets to be 16 bytes wide every
873 * time, so we always read 4 32-bit VPM entries.
874 */
875 for (int i = 0; i < 4; i++) {
876 vpm_reads[i] = qir_get_temp(c);
877 qir_emit(c, qir_inst(QOP_VPM_READ,
878 vpm_reads[i],
879 c->undef,
880 c->undef));
881 c->num_inputs++;
882 }
883
884 bool format_warned = false;
885 const struct util_format_description *desc =
886 util_format_description(format);
887
888 for (int i = 0; i < 4; i++) {
889 uint8_t swiz = desc->swizzle[i];
890 struct qreg result;
891
892 if (swiz > UTIL_FORMAT_SWIZZLE_W)
893 result = get_swizzled_channel(c, vpm_reads, swiz);
894 else if (desc->channel[swiz].size == 32 &&
895 desc->channel[swiz].type == UTIL_FORMAT_TYPE_FLOAT) {
896 result = get_swizzled_channel(c, vpm_reads, swiz);
897 } else if (desc->channel[swiz].size == 8 &&
898 (desc->channel[swiz].type == UTIL_FORMAT_TYPE_UNSIGNED ||
899 desc->channel[swiz].type == UTIL_FORMAT_TYPE_SIGNED) &&
900 desc->channel[swiz].normalized) {
901 struct qreg vpm = vpm_reads[0];
902 if (desc->channel[swiz].type == UTIL_FORMAT_TYPE_SIGNED)
903 vpm = qir_XOR(c, vpm, qir_uniform_ui(c, 0x80808080));
904 result = qir_UNPACK_8(c, vpm, swiz);
905 } else {
906 if (!format_warned) {
907 fprintf(stderr,
908 "vtx element %d unsupported type: %s\n",
909 attr, util_format_name(format));
910 format_warned = true;
911 }
912 result = qir_uniform_f(c, 0.0);
913 }
914
915 if (desc->channel[swiz].normalized &&
916 desc->channel[swiz].type == UTIL_FORMAT_TYPE_SIGNED) {
917 result = qir_FSUB(c,
918 qir_FMUL(c,
919 result,
920 qir_uniform_f(c, 2.0)),
921 qir_uniform_f(c, 1.0));
922 }
923
924 c->inputs[attr * 4 + i] = result;
925 }
926 }
927
928 static void
929 tgsi_to_qir_kill_if(struct vc4_compile *c, struct qreg *src, int i)
930 {
931 if (c->discard.file == QFILE_NULL)
932 c->discard = qir_uniform_f(c, 0.0);
933 qir_SF(c, src[0 * 4 + i]);
934 c->discard = qir_SEL_X_Y_NS(c, qir_uniform_f(c, 1.0),
935 c->discard);
936 }
937
938 static void
939 emit_fragcoord_input(struct vc4_compile *c, int attr)
940 {
941 c->inputs[attr * 4 + 0] = qir_FRAG_X(c);
942 c->inputs[attr * 4 + 1] = qir_FRAG_Y(c);
943 c->inputs[attr * 4 + 2] =
944 qir_FMUL(c,
945 qir_ITOF(c, qir_FRAG_Z(c)),
946 qir_uniform_f(c, 1.0 / 0xffffff));
947 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
948 }
949
950 static void
951 emit_point_coord_input(struct vc4_compile *c, int attr)
952 {
953 if (c->point_x.file == QFILE_NULL) {
954 c->point_x = qir_uniform_f(c, 0.0);
955 c->point_y = qir_uniform_f(c, 0.0);
956 }
957
958 c->inputs[attr * 4 + 0] = c->point_x;
959 if (c->fs_key->point_coord_upper_left) {
960 c->inputs[attr * 4 + 1] = qir_FSUB(c,
961 qir_uniform_f(c, 1.0),
962 c->point_y);
963 } else {
964 c->inputs[attr * 4 + 1] = c->point_y;
965 }
966 c->inputs[attr * 4 + 2] = qir_uniform_f(c, 0.0);
967 c->inputs[attr * 4 + 3] = qir_uniform_f(c, 1.0);
968 }
969
970 static struct qreg
971 emit_fragment_varying(struct vc4_compile *c, uint8_t semantic,
972 uint8_t index, uint8_t swizzle)
973 {
974 uint32_t i = c->num_input_semantics++;
975 struct qreg vary = {
976 QFILE_VARY,
977 i
978 };
979
980 if (c->num_input_semantics >= c->input_semantics_array_size) {
981 c->input_semantics_array_size =
982 MAX2(4, c->input_semantics_array_size * 2);
983
984 c->input_semantics = reralloc(c, c->input_semantics,
985 struct vc4_varying_semantic,
986 c->input_semantics_array_size);
987 }
988
989 c->input_semantics[i].semantic = semantic;
990 c->input_semantics[i].index = index;
991 c->input_semantics[i].swizzle = swizzle;
992
993 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
994 }
995
996 static void
997 emit_fragment_input(struct vc4_compile *c, int attr,
998 struct tgsi_full_declaration *decl)
999 {
1000 for (int i = 0; i < 4; i++) {
1001 c->inputs[attr * 4 + i] =
1002 emit_fragment_varying(c,
1003 decl->Semantic.Name,
1004 decl->Semantic.Index,
1005 i);
1006 c->num_inputs++;
1007 }
1008 }
1009
1010 static void
1011 emit_face_input(struct vc4_compile *c, int attr)
1012 {
1013 c->inputs[attr * 4 + 0] = qir_FSUB(c,
1014 qir_uniform_f(c, 1.0),
1015 qir_FMUL(c,
1016 qir_ITOF(c, qir_FRAG_REV_FLAG(c)),
1017 qir_uniform_f(c, 2.0)));
1018 c->inputs[attr * 4 + 1] = qir_uniform_f(c, 0.0);
1019 c->inputs[attr * 4 + 2] = qir_uniform_f(c, 0.0);
1020 c->inputs[attr * 4 + 3] = qir_uniform_f(c, 1.0);
1021 }
1022
1023 static void
1024 emit_tgsi_declaration(struct vc4_compile *c,
1025 struct tgsi_full_declaration *decl)
1026 {
1027 switch (decl->Declaration.File) {
1028 case TGSI_FILE_TEMPORARY: {
1029 uint32_t old_size = c->temps_array_size;
1030 resize_qreg_array(c, &c->temps, &c->temps_array_size,
1031 (decl->Range.Last + 1) * 4);
1032
1033 for (int i = old_size; i < c->temps_array_size; i++)
1034 c->temps[i] = qir_uniform_ui(c, 0);
1035 break;
1036 }
1037
1038 case TGSI_FILE_INPUT:
1039 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1040 (decl->Range.Last + 1) * 4);
1041
1042 for (int i = decl->Range.First;
1043 i <= decl->Range.Last;
1044 i++) {
1045 if (c->stage == QSTAGE_FRAG) {
1046 if (decl->Semantic.Name ==
1047 TGSI_SEMANTIC_POSITION) {
1048 emit_fragcoord_input(c, i);
1049 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
1050 emit_face_input(c, i);
1051 } else if (decl->Semantic.Name == TGSI_SEMANTIC_GENERIC &&
1052 (c->fs_key->point_sprite_mask &
1053 (1 << decl->Semantic.Index))) {
1054 emit_point_coord_input(c, i);
1055 } else {
1056 emit_fragment_input(c, i, decl);
1057 }
1058 } else {
1059 emit_vertex_input(c, i);
1060 }
1061 }
1062 break;
1063
1064 case TGSI_FILE_OUTPUT: {
1065 uint32_t old_array_size = c->outputs_array_size;
1066 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
1067 (decl->Range.Last + 1) * 4);
1068
1069 if (old_array_size != c->outputs_array_size) {
1070 c->output_semantics = reralloc(c,
1071 c->output_semantics,
1072 struct vc4_varying_semantic,
1073 c->outputs_array_size);
1074 }
1075
1076 struct vc4_varying_semantic *sem =
1077 &c->output_semantics[decl->Range.First * 4];
1078 for (int i = 0; i < 4; i++) {
1079 sem[i].semantic = decl->Semantic.Name;
1080 sem[i].index = decl->Semantic.Index;
1081 sem[i].swizzle = i;
1082 }
1083
1084 switch (decl->Semantic.Name) {
1085 case TGSI_SEMANTIC_POSITION:
1086 c->output_position_index = decl->Range.First * 4;
1087 break;
1088 case TGSI_SEMANTIC_COLOR:
1089 c->output_color_index = decl->Range.First * 4;
1090 break;
1091 case TGSI_SEMANTIC_PSIZE:
1092 c->output_point_size_index = decl->Range.First * 4;
1093 break;
1094 }
1095
1096 break;
1097 }
1098 }
1099 }
1100
1101 static void
1102 emit_tgsi_instruction(struct vc4_compile *c,
1103 struct tgsi_full_instruction *tgsi_inst)
1104 {
1105 struct {
1106 enum qop op;
1107 struct qreg (*func)(struct vc4_compile *c,
1108 struct tgsi_full_instruction *tgsi_inst,
1109 enum qop op,
1110 struct qreg *src, int i);
1111 } op_trans[] = {
1112 [TGSI_OPCODE_MOV] = { QOP_MOV, tgsi_to_qir_alu },
1113 [TGSI_OPCODE_ABS] = { 0, tgsi_to_qir_abs },
1114 [TGSI_OPCODE_MUL] = { QOP_FMUL, tgsi_to_qir_alu },
1115 [TGSI_OPCODE_ADD] = { QOP_FADD, tgsi_to_qir_alu },
1116 [TGSI_OPCODE_SUB] = { QOP_FSUB, tgsi_to_qir_alu },
1117 [TGSI_OPCODE_MIN] = { QOP_FMIN, tgsi_to_qir_alu },
1118 [TGSI_OPCODE_MAX] = { QOP_FMAX, tgsi_to_qir_alu },
1119 [TGSI_OPCODE_F2I] = { QOP_FTOI, tgsi_to_qir_alu },
1120 [TGSI_OPCODE_I2F] = { QOP_ITOF, tgsi_to_qir_alu },
1121 [TGSI_OPCODE_UADD] = { QOP_ADD, tgsi_to_qir_alu },
1122 [TGSI_OPCODE_USHR] = { QOP_SHR, tgsi_to_qir_alu },
1123 [TGSI_OPCODE_ISHR] = { QOP_ASR, tgsi_to_qir_alu },
1124 [TGSI_OPCODE_SHL] = { QOP_SHL, tgsi_to_qir_alu },
1125 [TGSI_OPCODE_IMIN] = { QOP_MIN, tgsi_to_qir_alu },
1126 [TGSI_OPCODE_IMAX] = { QOP_MAX, tgsi_to_qir_alu },
1127 [TGSI_OPCODE_AND] = { QOP_AND, tgsi_to_qir_alu },
1128 [TGSI_OPCODE_OR] = { QOP_OR, tgsi_to_qir_alu },
1129 [TGSI_OPCODE_XOR] = { QOP_XOR, tgsi_to_qir_alu },
1130 [TGSI_OPCODE_NOT] = { QOP_NOT, tgsi_to_qir_alu },
1131
1132 [TGSI_OPCODE_UMUL] = { 0, tgsi_to_qir_umul },
1133 [TGSI_OPCODE_IDIV] = { 0, tgsi_to_qir_idiv },
1134 [TGSI_OPCODE_INEG] = { 0, tgsi_to_qir_ineg },
1135
1136 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_alu },
1137 [TGSI_OPCODE_SEQ] = { 0, tgsi_to_qir_seq },
1138 [TGSI_OPCODE_SNE] = { 0, tgsi_to_qir_sne },
1139 [TGSI_OPCODE_SGE] = { 0, tgsi_to_qir_sge },
1140 [TGSI_OPCODE_SLT] = { 0, tgsi_to_qir_slt },
1141 [TGSI_OPCODE_FSEQ] = { 0, tgsi_to_qir_fseq },
1142 [TGSI_OPCODE_FSNE] = { 0, tgsi_to_qir_fsne },
1143 [TGSI_OPCODE_FSGE] = { 0, tgsi_to_qir_fsge },
1144 [TGSI_OPCODE_FSLT] = { 0, tgsi_to_qir_fslt },
1145 [TGSI_OPCODE_USEQ] = { 0, tgsi_to_qir_useq },
1146 [TGSI_OPCODE_USNE] = { 0, tgsi_to_qir_usne },
1147 [TGSI_OPCODE_ISGE] = { 0, tgsi_to_qir_isge },
1148 [TGSI_OPCODE_ISLT] = { 0, tgsi_to_qir_islt },
1149
1150 [TGSI_OPCODE_CMP] = { 0, tgsi_to_qir_cmp },
1151 [TGSI_OPCODE_MAD] = { 0, tgsi_to_qir_mad },
1152 [TGSI_OPCODE_RCP] = { QOP_RCP, tgsi_to_qir_scalar },
1153 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_scalar },
1154 [TGSI_OPCODE_EX2] = { QOP_EXP2, tgsi_to_qir_scalar },
1155 [TGSI_OPCODE_LG2] = { QOP_LOG2, tgsi_to_qir_scalar },
1156 [TGSI_OPCODE_LRP] = { 0, tgsi_to_qir_lrp },
1157 [TGSI_OPCODE_TRUNC] = { 0, tgsi_to_qir_trunc },
1158 [TGSI_OPCODE_CEIL] = { 0, tgsi_to_qir_ceil },
1159 [TGSI_OPCODE_FRC] = { 0, tgsi_to_qir_frc },
1160 [TGSI_OPCODE_FLR] = { 0, tgsi_to_qir_flr },
1161 [TGSI_OPCODE_SIN] = { 0, tgsi_to_qir_sin },
1162 [TGSI_OPCODE_COS] = { 0, tgsi_to_qir_cos },
1163 [TGSI_OPCODE_CLAMP] = { 0, tgsi_to_qir_clamp },
1164 [TGSI_OPCODE_SSG] = { 0, tgsi_to_qir_ssg },
1165 };
1166 static int asdf = 0;
1167 uint32_t tgsi_op = tgsi_inst->Instruction.Opcode;
1168
1169 if (tgsi_op == TGSI_OPCODE_END)
1170 return;
1171
1172 struct qreg src_regs[12];
1173 for (int s = 0; s < 3; s++) {
1174 for (int i = 0; i < 4; i++) {
1175 src_regs[4 * s + i] =
1176 get_src(c, tgsi_inst->Instruction.Opcode,
1177 &tgsi_inst->Src[s].Register, i);
1178 }
1179 }
1180
1181 switch (tgsi_op) {
1182 case TGSI_OPCODE_TEX:
1183 case TGSI_OPCODE_TXP:
1184 case TGSI_OPCODE_TXB:
1185 case TGSI_OPCODE_TXL:
1186 tgsi_to_qir_tex(c, tgsi_inst,
1187 op_trans[tgsi_op].op, src_regs);
1188 return;
1189 case TGSI_OPCODE_KILL:
1190 c->discard = qir_uniform_f(c, 1.0);
1191 return;
1192 case TGSI_OPCODE_KILL_IF:
1193 for (int i = 0; i < 4; i++)
1194 tgsi_to_qir_kill_if(c, src_regs, i);
1195 return;
1196 default:
1197 break;
1198 }
1199
1200 if (tgsi_op > ARRAY_SIZE(op_trans) || !(op_trans[tgsi_op].func)) {
1201 fprintf(stderr, "unknown tgsi inst: ");
1202 tgsi_dump_instruction(tgsi_inst, asdf++);
1203 fprintf(stderr, "\n");
1204 abort();
1205 }
1206
1207 for (int i = 0; i < 4; i++) {
1208 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
1209 continue;
1210
1211 struct qreg result;
1212
1213 result = op_trans[tgsi_op].func(c, tgsi_inst,
1214 op_trans[tgsi_op].op,
1215 src_regs, i);
1216
1217 if (tgsi_inst->Instruction.Saturate) {
1218 float low = (tgsi_inst->Instruction.Saturate ==
1219 TGSI_SAT_MINUS_PLUS_ONE ? -1.0 : 0.0);
1220 result = qir_FMAX(c,
1221 qir_FMIN(c,
1222 result,
1223 qir_uniform_f(c, 1.0)),
1224 qir_uniform_f(c, low));
1225 }
1226
1227 update_dst(c, tgsi_inst, i, result);
1228 }
1229 }
1230
1231 static void
1232 parse_tgsi_immediate(struct vc4_compile *c, struct tgsi_full_immediate *imm)
1233 {
1234 for (int i = 0; i < 4; i++) {
1235 unsigned n = c->num_consts++;
1236 resize_qreg_array(c, &c->consts, &c->consts_array_size, n + 1);
1237 c->consts[n] = qir_uniform_ui(c, imm->u[i].Uint);
1238 }
1239 }
1240
1241 static struct qreg
1242 vc4_blend_channel(struct vc4_compile *c,
1243 struct qreg *dst,
1244 struct qreg *src,
1245 struct qreg val,
1246 unsigned factor,
1247 int channel)
1248 {
1249 switch(factor) {
1250 case PIPE_BLENDFACTOR_ONE:
1251 return val;
1252 case PIPE_BLENDFACTOR_SRC_COLOR:
1253 return qir_FMUL(c, val, src[channel]);
1254 case PIPE_BLENDFACTOR_SRC_ALPHA:
1255 return qir_FMUL(c, val, src[3]);
1256 case PIPE_BLENDFACTOR_DST_ALPHA:
1257 return qir_FMUL(c, val, dst[3]);
1258 case PIPE_BLENDFACTOR_DST_COLOR:
1259 return qir_FMUL(c, val, dst[channel]);
1260 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
1261 return qir_FMIN(c, src[3], qir_FSUB(c,
1262 qir_uniform_f(c, 1.0),
1263 dst[3]));
1264 case PIPE_BLENDFACTOR_CONST_COLOR:
1265 return qir_FMUL(c, val,
1266 get_temp_for_uniform(c,
1267 QUNIFORM_BLEND_CONST_COLOR,
1268 channel));
1269 case PIPE_BLENDFACTOR_CONST_ALPHA:
1270 return qir_FMUL(c, val,
1271 get_temp_for_uniform(c,
1272 QUNIFORM_BLEND_CONST_COLOR,
1273 3));
1274 case PIPE_BLENDFACTOR_ZERO:
1275 return qir_uniform_f(c, 0.0);
1276 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
1277 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1278 src[channel]));
1279 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
1280 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1281 src[3]));
1282 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
1283 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1284 dst[3]));
1285 case PIPE_BLENDFACTOR_INV_DST_COLOR:
1286 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1287 dst[channel]));
1288 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
1289 return qir_FMUL(c, val,
1290 qir_FSUB(c, qir_uniform_f(c, 1.0),
1291 get_temp_for_uniform(c,
1292 QUNIFORM_BLEND_CONST_COLOR,
1293 channel)));
1294 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
1295 return qir_FMUL(c, val,
1296 qir_FSUB(c, qir_uniform_f(c, 1.0),
1297 get_temp_for_uniform(c,
1298 QUNIFORM_BLEND_CONST_COLOR,
1299 3)));
1300
1301 default:
1302 case PIPE_BLENDFACTOR_SRC1_COLOR:
1303 case PIPE_BLENDFACTOR_SRC1_ALPHA:
1304 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
1305 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
1306 /* Unsupported. */
1307 fprintf(stderr, "Unknown blend factor %d\n", factor);
1308 return val;
1309 }
1310 }
1311
1312 static struct qreg
1313 vc4_blend_func(struct vc4_compile *c,
1314 struct qreg src, struct qreg dst,
1315 unsigned func)
1316 {
1317 switch (func) {
1318 case PIPE_BLEND_ADD:
1319 return qir_FADD(c, src, dst);
1320 case PIPE_BLEND_SUBTRACT:
1321 return qir_FSUB(c, src, dst);
1322 case PIPE_BLEND_REVERSE_SUBTRACT:
1323 return qir_FSUB(c, dst, src);
1324 case PIPE_BLEND_MIN:
1325 return qir_FMIN(c, src, dst);
1326 case PIPE_BLEND_MAX:
1327 return qir_FMAX(c, src, dst);
1328
1329 default:
1330 /* Unsupported. */
1331 fprintf(stderr, "Unknown blend func %d\n", func);
1332 return src;
1333
1334 }
1335 }
1336
1337 /**
1338 * Implements fixed function blending in shader code.
1339 *
1340 * VC4 doesn't have any hardware support for blending. Instead, you read the
1341 * current contents of the destination from the tile buffer after having
1342 * waited for the scoreboard (which is handled by vc4_qpu_emit.c), then do
1343 * math using your output color and that destination value, and update the
1344 * output color appropriately.
1345 */
1346 static void
1347 vc4_blend(struct vc4_compile *c, struct qreg *result,
1348 struct qreg *dst_color, struct qreg *src_color)
1349 {
1350 struct pipe_rt_blend_state *blend = &c->fs_key->blend;
1351
1352 if (!blend->blend_enable) {
1353 for (int i = 0; i < 4; i++)
1354 result[i] = src_color[i];
1355 return;
1356 }
1357
1358 struct qreg src_blend[4], dst_blend[4];
1359 for (int i = 0; i < 3; i++) {
1360 src_blend[i] = vc4_blend_channel(c,
1361 dst_color, src_color,
1362 src_color[i],
1363 blend->rgb_src_factor, i);
1364 dst_blend[i] = vc4_blend_channel(c,
1365 dst_color, src_color,
1366 dst_color[i],
1367 blend->rgb_dst_factor, i);
1368 }
1369 src_blend[3] = vc4_blend_channel(c,
1370 dst_color, src_color,
1371 src_color[3],
1372 blend->alpha_src_factor, 3);
1373 dst_blend[3] = vc4_blend_channel(c,
1374 dst_color, src_color,
1375 dst_color[3],
1376 blend->alpha_dst_factor, 3);
1377
1378 for (int i = 0; i < 3; i++) {
1379 result[i] = vc4_blend_func(c,
1380 src_blend[i], dst_blend[i],
1381 blend->rgb_func);
1382 }
1383 result[3] = vc4_blend_func(c,
1384 src_blend[3], dst_blend[3],
1385 blend->alpha_func);
1386 }
1387
1388 static void
1389 alpha_test_discard(struct vc4_compile *c)
1390 {
1391 struct qreg src_alpha;
1392 struct qreg alpha_ref = get_temp_for_uniform(c, QUNIFORM_ALPHA_REF, 0);
1393
1394 if (!c->fs_key->alpha_test)
1395 return;
1396
1397 if (c->output_color_index != -1)
1398 src_alpha = c->outputs[c->output_color_index + 3];
1399 else
1400 src_alpha = qir_uniform_f(c, 1.0);
1401
1402 if (c->discard.file == QFILE_NULL)
1403 c->discard = qir_uniform_f(c, 0.0);
1404
1405 switch (c->fs_key->alpha_test_func) {
1406 case PIPE_FUNC_NEVER:
1407 c->discard = qir_uniform_f(c, 1.0);
1408 break;
1409 case PIPE_FUNC_ALWAYS:
1410 break;
1411 case PIPE_FUNC_EQUAL:
1412 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1413 c->discard = qir_SEL_X_Y_ZS(c, c->discard,
1414 qir_uniform_f(c, 1.0));
1415 break;
1416 case PIPE_FUNC_NOTEQUAL:
1417 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1418 c->discard = qir_SEL_X_Y_ZC(c, c->discard,
1419 qir_uniform_f(c, 1.0));
1420 break;
1421 case PIPE_FUNC_GREATER:
1422 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1423 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1424 qir_uniform_f(c, 1.0));
1425 break;
1426 case PIPE_FUNC_GEQUAL:
1427 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1428 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1429 qir_uniform_f(c, 1.0));
1430 break;
1431 case PIPE_FUNC_LESS:
1432 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1433 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1434 qir_uniform_f(c, 1.0));
1435 break;
1436 case PIPE_FUNC_LEQUAL:
1437 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1438 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1439 qir_uniform_f(c, 1.0));
1440 break;
1441 }
1442 }
1443
1444 static void
1445 emit_frag_end(struct vc4_compile *c)
1446 {
1447 alpha_test_discard(c);
1448
1449 enum pipe_format color_format = c->fs_key->color_format;
1450 const uint8_t *format_swiz = vc4_get_format_swizzle(color_format);
1451 struct qreg tlb_read_color[4] = { c->undef, c->undef, c->undef, c->undef };
1452 struct qreg dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1453 struct qreg linear_dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1454 if (c->fs_key->blend.blend_enable ||
1455 c->fs_key->blend.colormask != 0xf) {
1456 struct qreg r4 = qir_TLB_COLOR_READ(c);
1457 for (int i = 0; i < 4; i++)
1458 tlb_read_color[i] = qir_R4_UNPACK(c, r4, i);
1459 for (int i = 0; i < 4; i++) {
1460 dst_color[i] = get_swizzled_channel(c,
1461 tlb_read_color,
1462 format_swiz[i]);
1463 if (util_format_is_srgb(color_format) && i != 3) {
1464 linear_dst_color[i] =
1465 qir_srgb_decode(c, dst_color[i]);
1466 } else {
1467 linear_dst_color[i] = dst_color[i];
1468 }
1469 }
1470 }
1471
1472 struct qreg blend_color[4];
1473 struct qreg undef_array[4] = {
1474 c->undef, c->undef, c->undef, c->undef
1475 };
1476 vc4_blend(c, blend_color, linear_dst_color,
1477 (c->output_color_index != -1 ?
1478 c->outputs + c->output_color_index :
1479 undef_array));
1480
1481 if (util_format_is_srgb(color_format)) {
1482 for (int i = 0; i < 3; i++)
1483 blend_color[i] = qir_srgb_encode(c, blend_color[i]);
1484 }
1485
1486 /* If the bit isn't set in the color mask, then just return the
1487 * original dst color, instead.
1488 */
1489 for (int i = 0; i < 4; i++) {
1490 if (!(c->fs_key->blend.colormask & (1 << i))) {
1491 blend_color[i] = dst_color[i];
1492 }
1493 }
1494
1495 /* Debug: Sometimes you're getting a black output and just want to see
1496 * if the FS is getting executed at all. Spam magenta into the color
1497 * output.
1498 */
1499 if (0) {
1500 blend_color[0] = qir_uniform_f(c, 1.0);
1501 blend_color[1] = qir_uniform_f(c, 0.0);
1502 blend_color[2] = qir_uniform_f(c, 1.0);
1503 blend_color[3] = qir_uniform_f(c, 0.5);
1504 }
1505
1506 struct qreg swizzled_outputs[4];
1507 for (int i = 0; i < 4; i++) {
1508 swizzled_outputs[i] = get_swizzled_channel(c, blend_color,
1509 format_swiz[i]);
1510 }
1511
1512 if (c->discard.file != QFILE_NULL)
1513 qir_TLB_DISCARD_SETUP(c, c->discard);
1514
1515 if (c->fs_key->stencil_enabled) {
1516 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 0));
1517 if (c->fs_key->stencil_twoside) {
1518 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 1));
1519 }
1520 if (c->fs_key->stencil_full_writemasks) {
1521 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 2));
1522 }
1523 }
1524
1525 if (c->fs_key->depth_enabled) {
1526 struct qreg z;
1527 if (c->output_position_index != -1) {
1528 z = qir_FTOI(c, qir_FMUL(c, c->outputs[c->output_position_index + 2],
1529 qir_uniform_f(c, 0xffffff)));
1530 } else {
1531 z = qir_FRAG_Z(c);
1532 }
1533 qir_TLB_Z_WRITE(c, z);
1534 }
1535
1536 bool color_written = false;
1537 for (int i = 0; i < 4; i++) {
1538 if (swizzled_outputs[i].file != QFILE_NULL)
1539 color_written = true;
1540 }
1541
1542 struct qreg packed_color;
1543 if (color_written) {
1544 /* Fill in any undefined colors. The simulator will assertion
1545 * fail if we read something that wasn't written, and I don't
1546 * know what hardware does.
1547 */
1548 for (int i = 0; i < 4; i++) {
1549 if (swizzled_outputs[i].file == QFILE_NULL)
1550 swizzled_outputs[i] = qir_uniform_f(c, 0.0);
1551 }
1552 packed_color = qir_get_temp(c);
1553 qir_emit(c, qir_inst4(QOP_PACK_COLORS, packed_color,
1554 swizzled_outputs[0],
1555 swizzled_outputs[1],
1556 swizzled_outputs[2],
1557 swizzled_outputs[3]));
1558 } else {
1559 packed_color = qir_uniform_ui(c, 0);
1560 }
1561
1562 qir_emit(c, qir_inst(QOP_TLB_COLOR_WRITE, c->undef,
1563 packed_color, c->undef));
1564 }
1565
1566 static void
1567 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1568 {
1569 struct qreg xyi[2];
1570
1571 for (int i = 0; i < 2; i++) {
1572 struct qreg scale =
1573 add_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1574
1575 xyi[i] = qir_FTOI(c, qir_FMUL(c,
1576 qir_FMUL(c,
1577 c->outputs[i],
1578 scale),
1579 rcp_w));
1580 }
1581
1582 qir_VPM_WRITE(c, qir_PACK_SCALED(c, xyi[0], xyi[1]));
1583 }
1584
1585 static void
1586 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1587 {
1588 struct qreg zscale = add_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1589 struct qreg zoffset = add_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1590
1591 qir_VPM_WRITE(c, qir_FMUL(c, qir_FADD(c, qir_FMUL(c,
1592 c->outputs[2],
1593 zscale),
1594 zoffset),
1595 rcp_w));
1596 }
1597
1598 static void
1599 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1600 {
1601 qir_VPM_WRITE(c, rcp_w);
1602 }
1603
1604 static void
1605 emit_point_size_write(struct vc4_compile *c)
1606 {
1607 struct qreg point_size;
1608
1609 if (c->output_point_size_index)
1610 point_size = c->outputs[c->output_point_size_index + 3];
1611 else
1612 point_size = qir_uniform_f(c, 1.0);
1613
1614 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1615 * BCM21553).
1616 */
1617 point_size = qir_FMAX(c, point_size, qir_uniform_f(c, .125));
1618
1619 qir_VPM_WRITE(c, point_size);
1620 }
1621
1622 static void
1623 emit_vert_end(struct vc4_compile *c,
1624 struct vc4_varying_semantic *fs_inputs,
1625 uint32_t num_fs_inputs)
1626 {
1627 struct qreg rcp_w = qir_RCP(c, c->outputs[3]);
1628
1629 emit_scaled_viewport_write(c, rcp_w);
1630 emit_zs_write(c, rcp_w);
1631 emit_rcp_wc_write(c, rcp_w);
1632 if (c->vs_key->per_vertex_point_size)
1633 emit_point_size_write(c);
1634
1635 for (int i = 0; i < num_fs_inputs; i++) {
1636 struct vc4_varying_semantic *input = &fs_inputs[i];
1637 int j;
1638 for (j = 0; j < c->num_outputs; j++) {
1639 struct vc4_varying_semantic *output =
1640 &c->output_semantics[j];
1641 if (input->semantic == output->semantic &&
1642 input->index == output->index &&
1643 input->swizzle == output->swizzle) {
1644 qir_VPM_WRITE(c, c->outputs[j]);
1645 break;
1646 }
1647 }
1648 /* Emit padding if we didn't find a declared VS output for
1649 * this FS input.
1650 */
1651 if (j == c->num_outputs)
1652 qir_VPM_WRITE(c, qir_uniform_f(c, 0.0));
1653 }
1654 }
1655
1656 static void
1657 emit_coord_end(struct vc4_compile *c)
1658 {
1659 struct qreg rcp_w = qir_RCP(c, c->outputs[3]);
1660
1661 for (int i = 0; i < 4; i++)
1662 qir_VPM_WRITE(c, c->outputs[i]);
1663
1664 emit_scaled_viewport_write(c, rcp_w);
1665 emit_zs_write(c, rcp_w);
1666 emit_rcp_wc_write(c, rcp_w);
1667 if (c->vs_key->per_vertex_point_size)
1668 emit_point_size_write(c);
1669 }
1670
1671 static struct vc4_compile *
1672 vc4_shader_tgsi_to_qir(struct vc4_context *vc4, enum qstage stage,
1673 struct vc4_key *key)
1674 {
1675 struct vc4_compile *c = qir_compile_init();
1676 int ret;
1677
1678 c->stage = stage;
1679 c->shader_state = &key->shader_state->base;
1680
1681 c->key = key;
1682 switch (stage) {
1683 case QSTAGE_FRAG:
1684 c->fs_key = (struct vc4_fs_key *)key;
1685 if (c->fs_key->is_points) {
1686 c->point_x = emit_fragment_varying(c, ~0, ~0, 0);
1687 c->point_y = emit_fragment_varying(c, ~0, ~0, 0);
1688 } else if (c->fs_key->is_lines) {
1689 c->line_x = emit_fragment_varying(c, ~0, ~0, 0);
1690 }
1691 break;
1692 case QSTAGE_VERT:
1693 c->vs_key = (struct vc4_vs_key *)key;
1694 break;
1695 case QSTAGE_COORD:
1696 c->vs_key = (struct vc4_vs_key *)key;
1697 break;
1698 }
1699
1700 const struct tgsi_token *tokens = key->shader_state->base.tokens;
1701 if (c->fs_key && c->fs_key->light_twoside) {
1702 if (!key->shader_state->twoside_tokens) {
1703 const struct tgsi_lowering_config lowering_config = {
1704 .color_two_side = true,
1705 };
1706 struct tgsi_shader_info info;
1707 key->shader_state->twoside_tokens =
1708 tgsi_transform_lowering(&lowering_config,
1709 key->shader_state->base.tokens,
1710 &info);
1711
1712 /* If no transformation occurred, then NULL is
1713 * returned and we just use our original tokens.
1714 */
1715 if (!key->shader_state->twoside_tokens) {
1716 key->shader_state->twoside_tokens =
1717 key->shader_state->base.tokens;
1718 }
1719 }
1720 tokens = key->shader_state->twoside_tokens;
1721 }
1722
1723 ret = tgsi_parse_init(&c->parser, tokens);
1724 assert(ret == TGSI_PARSE_OK);
1725
1726 if (vc4_debug & VC4_DEBUG_TGSI) {
1727 fprintf(stderr, "TGSI:\n");
1728 tgsi_dump(tokens, 0);
1729 }
1730
1731 while (!tgsi_parse_end_of_tokens(&c->parser)) {
1732 tgsi_parse_token(&c->parser);
1733
1734 switch (c->parser.FullToken.Token.Type) {
1735 case TGSI_TOKEN_TYPE_DECLARATION:
1736 emit_tgsi_declaration(c,
1737 &c->parser.FullToken.FullDeclaration);
1738 break;
1739
1740 case TGSI_TOKEN_TYPE_INSTRUCTION:
1741 emit_tgsi_instruction(c,
1742 &c->parser.FullToken.FullInstruction);
1743 break;
1744
1745 case TGSI_TOKEN_TYPE_IMMEDIATE:
1746 parse_tgsi_immediate(c,
1747 &c->parser.FullToken.FullImmediate);
1748 break;
1749 }
1750 }
1751
1752 switch (stage) {
1753 case QSTAGE_FRAG:
1754 emit_frag_end(c);
1755 break;
1756 case QSTAGE_VERT:
1757 emit_vert_end(c,
1758 vc4->prog.fs->input_semantics,
1759 vc4->prog.fs->num_inputs);
1760 break;
1761 case QSTAGE_COORD:
1762 emit_coord_end(c);
1763 break;
1764 }
1765
1766 tgsi_parse_free(&c->parser);
1767
1768 qir_optimize(c);
1769
1770 if (vc4_debug & VC4_DEBUG_QIR) {
1771 fprintf(stderr, "QIR:\n");
1772 qir_dump(c);
1773 }
1774 qir_reorder_uniforms(c);
1775 vc4_generate_code(vc4, c);
1776
1777 if (vc4_debug & VC4_DEBUG_SHADERDB) {
1778 fprintf(stderr, "SHADER-DB: %s: %d instructions\n",
1779 qir_get_stage_name(c->stage), c->qpu_inst_count);
1780 fprintf(stderr, "SHADER-DB: %s: %d uniforms\n",
1781 qir_get_stage_name(c->stage), c->num_uniforms);
1782 }
1783
1784 return c;
1785 }
1786
1787 static void *
1788 vc4_shader_state_create(struct pipe_context *pctx,
1789 const struct pipe_shader_state *cso)
1790 {
1791 struct vc4_uncompiled_shader *so = CALLOC_STRUCT(vc4_uncompiled_shader);
1792 if (!so)
1793 return NULL;
1794
1795 const struct tgsi_lowering_config lowering_config = {
1796 .lower_DST = true,
1797 .lower_XPD = true,
1798 .lower_SCS = true,
1799 .lower_POW = true,
1800 .lower_LIT = true,
1801 .lower_EXP = true,
1802 .lower_LOG = true,
1803 .lower_DP4 = true,
1804 .lower_DP3 = true,
1805 .lower_DPH = true,
1806 .lower_DP2 = true,
1807 .lower_DP2A = true,
1808 };
1809
1810 struct tgsi_shader_info info;
1811 so->base.tokens = tgsi_transform_lowering(&lowering_config, cso->tokens, &info);
1812 if (!so->base.tokens)
1813 so->base.tokens = tgsi_dup_tokens(cso->tokens);
1814
1815 return so;
1816 }
1817
1818 static void
1819 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
1820 struct vc4_compile *c)
1821 {
1822 int count = c->num_uniforms;
1823 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
1824
1825 uinfo->count = count;
1826 uinfo->data = ralloc_array(shader, uint32_t, count);
1827 memcpy(uinfo->data, c->uniform_data,
1828 count * sizeof(*uinfo->data));
1829 uinfo->contents = ralloc_array(shader, enum quniform_contents, count);
1830 memcpy(uinfo->contents, c->uniform_contents,
1831 count * sizeof(*uinfo->contents));
1832 uinfo->num_texture_samples = c->num_texture_samples;
1833 }
1834
1835 static struct vc4_compiled_shader *
1836 vc4_get_compiled_shader(struct vc4_context *vc4, enum qstage stage,
1837 struct vc4_key *key)
1838 {
1839 struct util_hash_table *ht;
1840 uint32_t key_size;
1841 if (stage == QSTAGE_FRAG) {
1842 ht = vc4->fs_cache;
1843 key_size = sizeof(struct vc4_fs_key);
1844 } else {
1845 ht = vc4->vs_cache;
1846 key_size = sizeof(struct vc4_vs_key);
1847 }
1848
1849 struct vc4_compiled_shader *shader;
1850 shader = util_hash_table_get(ht, key);
1851 if (shader)
1852 return shader;
1853
1854 struct vc4_compile *c = vc4_shader_tgsi_to_qir(vc4, stage, key);
1855 shader = rzalloc(NULL, struct vc4_compiled_shader);
1856
1857 shader->program_id = vc4->next_compiled_program_id++;
1858 if (stage == QSTAGE_FRAG) {
1859 shader->input_semantics = ralloc_array(shader,
1860 struct vc4_varying_semantic,
1861 c->num_input_semantics);
1862
1863 for (int i = 0; i < c->num_input_semantics; i++) {
1864 struct vc4_varying_semantic *sem = &c->input_semantics[i];
1865
1866 /* Skip non-VS-output inputs. */
1867 if (sem->semantic == (uint8_t)~0)
1868 continue;
1869
1870 if (sem->semantic == TGSI_SEMANTIC_COLOR)
1871 shader->color_inputs |= (1 << shader->num_inputs);
1872 shader->input_semantics[shader->num_inputs] = *sem;
1873 shader->num_inputs++;
1874 }
1875 } else {
1876 shader->num_inputs = c->num_inputs;
1877 }
1878
1879 copy_uniform_state_to_shader(shader, c);
1880 shader->bo = vc4_bo_alloc_mem(vc4->screen, c->qpu_insts,
1881 c->qpu_inst_count * sizeof(uint64_t),
1882 "code");
1883
1884 qir_compile_destroy(c);
1885
1886 struct vc4_key *dup_key;
1887 dup_key = malloc(key_size);
1888 memcpy(dup_key, key, key_size);
1889 util_hash_table_set(ht, dup_key, shader);
1890
1891 return shader;
1892 }
1893
1894 static void
1895 vc4_setup_shared_key(struct vc4_key *key, struct vc4_texture_stateobj *texstate)
1896 {
1897 for (int i = 0; i < texstate->num_textures; i++) {
1898 struct pipe_sampler_view *sampler = texstate->textures[i];
1899 struct pipe_sampler_state *sampler_state =
1900 texstate->samplers[i];
1901
1902 if (sampler) {
1903 key->tex[i].format = sampler->format;
1904 key->tex[i].swizzle[0] = sampler->swizzle_r;
1905 key->tex[i].swizzle[1] = sampler->swizzle_g;
1906 key->tex[i].swizzle[2] = sampler->swizzle_b;
1907 key->tex[i].swizzle[3] = sampler->swizzle_a;
1908 key->tex[i].compare_mode = sampler_state->compare_mode;
1909 key->tex[i].compare_func = sampler_state->compare_func;
1910 key->tex[i].wrap_s = sampler_state->wrap_s;
1911 key->tex[i].wrap_t = sampler_state->wrap_t;
1912 }
1913 }
1914 }
1915
1916 static void
1917 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
1918 {
1919 struct vc4_fs_key local_key;
1920 struct vc4_fs_key *key = &local_key;
1921
1922 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
1923 VC4_DIRTY_BLEND |
1924 VC4_DIRTY_FRAMEBUFFER |
1925 VC4_DIRTY_ZSA |
1926 VC4_DIRTY_RASTERIZER |
1927 VC4_DIRTY_FRAGTEX |
1928 VC4_DIRTY_TEXSTATE |
1929 VC4_DIRTY_PROG))) {
1930 return;
1931 }
1932
1933 memset(key, 0, sizeof(*key));
1934 vc4_setup_shared_key(&key->base, &vc4->fragtex);
1935 key->base.shader_state = vc4->prog.bind_fs;
1936 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
1937 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
1938 prim_mode <= PIPE_PRIM_LINE_STRIP);
1939 key->blend = vc4->blend->rt[0];
1940
1941 if (vc4->framebuffer.cbufs[0])
1942 key->color_format = vc4->framebuffer.cbufs[0]->format;
1943
1944 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
1945 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
1946 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
1947 key->depth_enabled = (vc4->zsa->base.depth.enabled ||
1948 key->stencil_enabled);
1949 if (vc4->zsa->base.alpha.enabled) {
1950 key->alpha_test = true;
1951 key->alpha_test_func = vc4->zsa->base.alpha.func;
1952 }
1953
1954 if (key->is_points) {
1955 key->point_sprite_mask =
1956 vc4->rasterizer->base.sprite_coord_enable;
1957 key->point_coord_upper_left =
1958 (vc4->rasterizer->base.sprite_coord_mode ==
1959 PIPE_SPRITE_COORD_UPPER_LEFT);
1960 }
1961
1962 key->light_twoside = vc4->rasterizer->base.light_twoside;
1963
1964 struct vc4_compiled_shader *old_fs = vc4->prog.fs;
1965 vc4->prog.fs = vc4_get_compiled_shader(vc4, QSTAGE_FRAG, &key->base);
1966 if (vc4->prog.fs == old_fs)
1967 return;
1968
1969 if (vc4->rasterizer->base.flatshade &&
1970 old_fs && vc4->prog.fs->color_inputs != old_fs->color_inputs) {
1971 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
1972 }
1973 }
1974
1975 static void
1976 vc4_update_compiled_vs(struct vc4_context *vc4, uint8_t prim_mode)
1977 {
1978 struct vc4_vs_key local_key;
1979 struct vc4_vs_key *key = &local_key;
1980
1981 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
1982 VC4_DIRTY_RASTERIZER |
1983 VC4_DIRTY_VERTTEX |
1984 VC4_DIRTY_TEXSTATE |
1985 VC4_DIRTY_VTXSTATE |
1986 VC4_DIRTY_PROG))) {
1987 return;
1988 }
1989
1990 memset(key, 0, sizeof(*key));
1991 vc4_setup_shared_key(&key->base, &vc4->verttex);
1992 key->base.shader_state = vc4->prog.bind_vs;
1993 key->compiled_fs_id = vc4->prog.fs->program_id;
1994
1995 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
1996 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
1997
1998 key->per_vertex_point_size =
1999 (prim_mode == PIPE_PRIM_POINTS &&
2000 vc4->rasterizer->base.point_size_per_vertex);
2001
2002 vc4->prog.vs = vc4_get_compiled_shader(vc4, QSTAGE_VERT, &key->base);
2003 key->is_coord = true;
2004 vc4->prog.cs = vc4_get_compiled_shader(vc4, QSTAGE_COORD, &key->base);
2005 }
2006
2007 void
2008 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
2009 {
2010 vc4_update_compiled_fs(vc4, prim_mode);
2011 vc4_update_compiled_vs(vc4, prim_mode);
2012 }
2013
2014 static unsigned
2015 fs_cache_hash(void *key)
2016 {
2017 return _mesa_hash_data(key, sizeof(struct vc4_fs_key));
2018 }
2019
2020 static unsigned
2021 vs_cache_hash(void *key)
2022 {
2023 return _mesa_hash_data(key, sizeof(struct vc4_vs_key));
2024 }
2025
2026 static int
2027 fs_cache_compare(void *key1, void *key2)
2028 {
2029 return memcmp(key1, key2, sizeof(struct vc4_fs_key));
2030 }
2031
2032 static int
2033 vs_cache_compare(void *key1, void *key2)
2034 {
2035 return memcmp(key1, key2, sizeof(struct vc4_vs_key));
2036 }
2037
2038 struct delete_state {
2039 struct vc4_context *vc4;
2040 struct vc4_uncompiled_shader *shader_state;
2041 };
2042
2043 static enum pipe_error
2044 fs_delete_from_cache(void *in_key, void *in_value, void *data)
2045 {
2046 struct delete_state *del = data;
2047 struct vc4_fs_key *key = in_key;
2048 struct vc4_compiled_shader *shader = in_value;
2049
2050 if (key->base.shader_state == data) {
2051 util_hash_table_remove(del->vc4->fs_cache, key);
2052 vc4_bo_unreference(&shader->bo);
2053 ralloc_free(shader);
2054 }
2055
2056 return 0;
2057 }
2058
2059 static enum pipe_error
2060 vs_delete_from_cache(void *in_key, void *in_value, void *data)
2061 {
2062 struct delete_state *del = data;
2063 struct vc4_vs_key *key = in_key;
2064 struct vc4_compiled_shader *shader = in_value;
2065
2066 if (key->base.shader_state == data) {
2067 util_hash_table_remove(del->vc4->vs_cache, key);
2068 vc4_bo_unreference(&shader->bo);
2069 ralloc_free(shader);
2070 }
2071
2072 return 0;
2073 }
2074
2075 static void
2076 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
2077 {
2078 struct vc4_context *vc4 = vc4_context(pctx);
2079 struct vc4_uncompiled_shader *so = hwcso;
2080 struct delete_state del;
2081
2082 del.vc4 = vc4;
2083 del.shader_state = so;
2084 util_hash_table_foreach(vc4->fs_cache, fs_delete_from_cache, &del);
2085 util_hash_table_foreach(vc4->vs_cache, vs_delete_from_cache, &del);
2086
2087 if (so->twoside_tokens != so->base.tokens)
2088 free((void *)so->twoside_tokens);
2089 free((void *)so->base.tokens);
2090 free(so);
2091 }
2092
2093 static uint32_t translate_wrap(uint32_t p_wrap, bool using_nearest)
2094 {
2095 switch (p_wrap) {
2096 case PIPE_TEX_WRAP_REPEAT:
2097 return 0;
2098 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
2099 return 1;
2100 case PIPE_TEX_WRAP_MIRROR_REPEAT:
2101 return 2;
2102 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
2103 return 3;
2104 case PIPE_TEX_WRAP_CLAMP:
2105 return (using_nearest ? 1 : 3);
2106 default:
2107 fprintf(stderr, "Unknown wrap mode %d\n", p_wrap);
2108 assert(!"not reached");
2109 return 0;
2110 }
2111 }
2112
2113 static void
2114 write_texture_p0(struct vc4_context *vc4,
2115 struct vc4_texture_stateobj *texstate,
2116 uint32_t unit)
2117 {
2118 struct pipe_sampler_view *texture = texstate->textures[unit];
2119 struct vc4_resource *rsc = vc4_resource(texture->texture);
2120
2121 cl_reloc(vc4, &vc4->uniforms, rsc->bo,
2122 VC4_SET_FIELD(rsc->slices[0].offset >> 12, VC4_TEX_P0_OFFSET) |
2123 VC4_SET_FIELD(texture->u.tex.last_level, VC4_TEX_P0_MIPLVLS) |
2124 VC4_SET_FIELD(texture->target == PIPE_TEXTURE_CUBE,
2125 VC4_TEX_P0_CMMODE) |
2126 VC4_SET_FIELD(rsc->vc4_format & 7, VC4_TEX_P0_TYPE));
2127 }
2128
2129 static void
2130 write_texture_p1(struct vc4_context *vc4,
2131 struct vc4_texture_stateobj *texstate,
2132 uint32_t unit)
2133 {
2134 struct pipe_sampler_view *texture = texstate->textures[unit];
2135 struct vc4_resource *rsc = vc4_resource(texture->texture);
2136 struct pipe_sampler_state *sampler = texstate->samplers[unit];
2137 static const uint8_t minfilter_map[6] = {
2138 VC4_TEX_P1_MINFILT_NEAR_MIP_NEAR,
2139 VC4_TEX_P1_MINFILT_LIN_MIP_NEAR,
2140 VC4_TEX_P1_MINFILT_NEAR_MIP_LIN,
2141 VC4_TEX_P1_MINFILT_LIN_MIP_LIN,
2142 VC4_TEX_P1_MINFILT_NEAREST,
2143 VC4_TEX_P1_MINFILT_LINEAR,
2144 };
2145 static const uint32_t magfilter_map[] = {
2146 [PIPE_TEX_FILTER_NEAREST] = VC4_TEX_P1_MAGFILT_NEAREST,
2147 [PIPE_TEX_FILTER_LINEAR] = VC4_TEX_P1_MAGFILT_LINEAR,
2148 };
2149
2150 bool either_nearest =
2151 (sampler->mag_img_filter == PIPE_TEX_MIPFILTER_NEAREST ||
2152 sampler->min_img_filter == PIPE_TEX_MIPFILTER_NEAREST);
2153
2154 cl_u32(&vc4->uniforms,
2155 VC4_SET_FIELD(rsc->vc4_format >> 4, VC4_TEX_P1_TYPE4) |
2156 VC4_SET_FIELD(texture->texture->height0 & 2047,
2157 VC4_TEX_P1_HEIGHT) |
2158 VC4_SET_FIELD(texture->texture->width0 & 2047,
2159 VC4_TEX_P1_WIDTH) |
2160 VC4_SET_FIELD(magfilter_map[sampler->mag_img_filter],
2161 VC4_TEX_P1_MAGFILT) |
2162 VC4_SET_FIELD(minfilter_map[sampler->min_mip_filter * 2 +
2163 sampler->min_img_filter],
2164 VC4_TEX_P1_MINFILT) |
2165 VC4_SET_FIELD(translate_wrap(sampler->wrap_s, either_nearest),
2166 VC4_TEX_P1_WRAP_S) |
2167 VC4_SET_FIELD(translate_wrap(sampler->wrap_t, either_nearest),
2168 VC4_TEX_P1_WRAP_T));
2169 }
2170
2171 static void
2172 write_texture_p2(struct vc4_context *vc4,
2173 struct vc4_texture_stateobj *texstate,
2174 uint32_t data)
2175 {
2176 uint32_t unit = data & 0xffff;
2177 struct pipe_sampler_view *texture = texstate->textures[unit];
2178 struct vc4_resource *rsc = vc4_resource(texture->texture);
2179
2180 cl_u32(&vc4->uniforms,
2181 VC4_SET_FIELD(VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE,
2182 VC4_TEX_P2_PTYPE) |
2183 VC4_SET_FIELD(rsc->cube_map_stride >> 12, VC4_TEX_P2_CMST) |
2184 VC4_SET_FIELD((data >> 16) & 1, VC4_TEX_P2_BSLOD));
2185 }
2186
2187
2188 #define SWIZ(x,y,z,w) { \
2189 UTIL_FORMAT_SWIZZLE_##x, \
2190 UTIL_FORMAT_SWIZZLE_##y, \
2191 UTIL_FORMAT_SWIZZLE_##z, \
2192 UTIL_FORMAT_SWIZZLE_##w \
2193 }
2194
2195 static void
2196 write_texture_border_color(struct vc4_context *vc4,
2197 struct vc4_texture_stateobj *texstate,
2198 uint32_t unit)
2199 {
2200 struct pipe_sampler_state *sampler = texstate->samplers[unit];
2201 struct pipe_sampler_view *texture = texstate->textures[unit];
2202 struct vc4_resource *rsc = vc4_resource(texture->texture);
2203 union util_color uc;
2204
2205 const struct util_format_description *tex_format_desc =
2206 util_format_description(texture->format);
2207
2208 float border_color[4];
2209 for (int i = 0; i < 4; i++)
2210 border_color[i] = sampler->border_color.f[i];
2211 if (util_format_is_srgb(texture->format)) {
2212 for (int i = 0; i < 3; i++)
2213 border_color[i] =
2214 util_format_linear_to_srgb_float(border_color[i]);
2215 }
2216
2217 /* Turn the border color into the layout of channels that it would
2218 * have when stored as texture contents.
2219 */
2220 float storage_color[4];
2221 util_format_unswizzle_4f(storage_color,
2222 border_color,
2223 tex_format_desc->swizzle);
2224
2225 /* Now, pack so that when the vc4_format-sampled texture contents are
2226 * replaced with our border color, the vc4_get_format_swizzle()
2227 * swizzling will get the right channels.
2228 */
2229 if (util_format_is_depth_or_stencil(texture->format)) {
2230 uc.ui[0] = util_pack_z(PIPE_FORMAT_Z24X8_UNORM,
2231 sampler->border_color.f[0]) << 8;
2232 } else {
2233 switch (rsc->vc4_format) {
2234 default:
2235 case VC4_TEXTURE_TYPE_RGBA8888:
2236 util_pack_color(storage_color,
2237 PIPE_FORMAT_R8G8B8A8_UNORM, &uc);
2238 break;
2239 case VC4_TEXTURE_TYPE_RGBA4444:
2240 util_pack_color(storage_color,
2241 PIPE_FORMAT_A8B8G8R8_UNORM, &uc);
2242 break;
2243 case VC4_TEXTURE_TYPE_RGB565:
2244 util_pack_color(storage_color,
2245 PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
2246 break;
2247 case VC4_TEXTURE_TYPE_ALPHA:
2248 uc.ui[0] = float_to_ubyte(storage_color[0]) << 24;
2249 break;
2250 case VC4_TEXTURE_TYPE_LUMALPHA:
2251 uc.ui[0] = ((float_to_ubyte(storage_color[1]) << 24) |
2252 (float_to_ubyte(storage_color[0]) << 0));
2253 break;
2254 }
2255 }
2256
2257 cl_u32(&vc4->uniforms, uc.ui[0]);
2258 }
2259
2260 static uint32_t
2261 get_texrect_scale(struct vc4_texture_stateobj *texstate,
2262 enum quniform_contents contents,
2263 uint32_t data)
2264 {
2265 struct pipe_sampler_view *texture = texstate->textures[data];
2266 uint32_t dim;
2267
2268 if (contents == QUNIFORM_TEXRECT_SCALE_X)
2269 dim = texture->texture->width0;
2270 else
2271 dim = texture->texture->height0;
2272
2273 return fui(1.0f / dim);
2274 }
2275
2276 void
2277 vc4_write_uniforms(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
2278 struct vc4_constbuf_stateobj *cb,
2279 struct vc4_texture_stateobj *texstate)
2280 {
2281 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
2282 const uint32_t *gallium_uniforms = cb->cb[0].user_buffer;
2283
2284 cl_start_shader_reloc(&vc4->uniforms, uinfo->num_texture_samples);
2285
2286 for (int i = 0; i < uinfo->count; i++) {
2287
2288 switch (uinfo->contents[i]) {
2289 case QUNIFORM_CONSTANT:
2290 cl_u32(&vc4->uniforms, uinfo->data[i]);
2291 break;
2292 case QUNIFORM_UNIFORM:
2293 cl_u32(&vc4->uniforms,
2294 gallium_uniforms[uinfo->data[i]]);
2295 break;
2296 case QUNIFORM_VIEWPORT_X_SCALE:
2297 cl_f(&vc4->uniforms, vc4->viewport.scale[0] * 16.0f);
2298 break;
2299 case QUNIFORM_VIEWPORT_Y_SCALE:
2300 cl_f(&vc4->uniforms, vc4->viewport.scale[1] * 16.0f);
2301 break;
2302
2303 case QUNIFORM_VIEWPORT_Z_OFFSET:
2304 cl_f(&vc4->uniforms, vc4->viewport.translate[2]);
2305 break;
2306 case QUNIFORM_VIEWPORT_Z_SCALE:
2307 cl_f(&vc4->uniforms, vc4->viewport.scale[2]);
2308 break;
2309
2310 case QUNIFORM_TEXTURE_CONFIG_P0:
2311 write_texture_p0(vc4, texstate, uinfo->data[i]);
2312 break;
2313
2314 case QUNIFORM_TEXTURE_CONFIG_P1:
2315 write_texture_p1(vc4, texstate, uinfo->data[i]);
2316 break;
2317
2318 case QUNIFORM_TEXTURE_CONFIG_P2:
2319 write_texture_p2(vc4, texstate, uinfo->data[i]);
2320 break;
2321
2322 case QUNIFORM_TEXTURE_BORDER_COLOR:
2323 write_texture_border_color(vc4, texstate, uinfo->data[i]);
2324 break;
2325
2326 case QUNIFORM_TEXRECT_SCALE_X:
2327 case QUNIFORM_TEXRECT_SCALE_Y:
2328 cl_u32(&vc4->uniforms,
2329 get_texrect_scale(texstate,
2330 uinfo->contents[i],
2331 uinfo->data[i]));
2332 break;
2333
2334 case QUNIFORM_BLEND_CONST_COLOR:
2335 cl_f(&vc4->uniforms,
2336 vc4->blend_color.color[uinfo->data[i]]);
2337 break;
2338
2339 case QUNIFORM_STENCIL:
2340 cl_u32(&vc4->uniforms,
2341 vc4->zsa->stencil_uniforms[uinfo->data[i]] |
2342 (uinfo->data[i] <= 1 ?
2343 (vc4->stencil_ref.ref_value[uinfo->data[i]] << 8) :
2344 0));
2345 break;
2346
2347 case QUNIFORM_ALPHA_REF:
2348 cl_f(&vc4->uniforms, vc4->zsa->base.alpha.ref_value);
2349 break;
2350 }
2351 #if 0
2352 uint32_t written_val = *(uint32_t *)(vc4->uniforms.next - 4);
2353 fprintf(stderr, "%p/%d: %d: 0x%08x (%f)\n",
2354 shader, i, written_val, uif(written_val));
2355 #endif
2356 }
2357 }
2358
2359 static void
2360 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
2361 {
2362 struct vc4_context *vc4 = vc4_context(pctx);
2363 vc4->prog.bind_fs = hwcso;
2364 vc4->prog.dirty |= VC4_SHADER_DIRTY_FP;
2365 vc4->dirty |= VC4_DIRTY_PROG;
2366 }
2367
2368 static void
2369 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
2370 {
2371 struct vc4_context *vc4 = vc4_context(pctx);
2372 vc4->prog.bind_vs = hwcso;
2373 vc4->prog.dirty |= VC4_SHADER_DIRTY_VP;
2374 vc4->dirty |= VC4_DIRTY_PROG;
2375 }
2376
2377 void
2378 vc4_program_init(struct pipe_context *pctx)
2379 {
2380 struct vc4_context *vc4 = vc4_context(pctx);
2381
2382 pctx->create_vs_state = vc4_shader_state_create;
2383 pctx->delete_vs_state = vc4_shader_state_delete;
2384
2385 pctx->create_fs_state = vc4_shader_state_create;
2386 pctx->delete_fs_state = vc4_shader_state_delete;
2387
2388 pctx->bind_fs_state = vc4_fp_state_bind;
2389 pctx->bind_vs_state = vc4_vp_state_bind;
2390
2391 vc4->fs_cache = util_hash_table_create(fs_cache_hash, fs_cache_compare);
2392 vc4->vs_cache = util_hash_table_create(vs_cache_hash, vs_cache_compare);
2393 }