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[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "util/u_format.h"
27 #include "util/u_hash.h"
28 #include "util/u_math.h"
29 #include "util/u_memory.h"
30 #include "util/ralloc.h"
31 #include "util/hash_table.h"
32 #include "tgsi/tgsi_dump.h"
33 #include "tgsi/tgsi_info.h"
34 #include "tgsi/tgsi_lowering.h"
35 #include "tgsi/tgsi_parse.h"
36 #include "nir/tgsi_to_nir.h"
37
38 #include "vc4_context.h"
39 #include "vc4_qpu.h"
40 #include "vc4_qir.h"
41 #ifdef USE_VC4_SIMULATOR
42 #include "simpenrose/simpenrose.h"
43 #endif
44
45 static struct qreg
46 ntq_get_src(struct vc4_compile *c, nir_src src, int i);
47
48 static void
49 resize_qreg_array(struct vc4_compile *c,
50 struct qreg **regs,
51 uint32_t *size,
52 uint32_t decl_size)
53 {
54 if (*size >= decl_size)
55 return;
56
57 uint32_t old_size = *size;
58 *size = MAX2(*size * 2, decl_size);
59 *regs = reralloc(c, *regs, struct qreg, *size);
60 if (!*regs) {
61 fprintf(stderr, "Malloc failure\n");
62 abort();
63 }
64
65 for (uint32_t i = old_size; i < *size; i++)
66 (*regs)[i] = c->undef;
67 }
68
69 static struct qreg
70 indirect_uniform_load(struct vc4_compile *c, nir_intrinsic_instr *intr)
71 {
72 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0);
73 uint32_t offset = intr->const_index[0];
74 struct vc4_compiler_ubo_range *range = NULL;
75 unsigned i;
76 for (i = 0; i < c->num_uniform_ranges; i++) {
77 range = &c->ubo_ranges[i];
78 if (offset >= range->src_offset &&
79 offset < range->src_offset + range->size) {
80 break;
81 }
82 }
83 /* The driver-location-based offset always has to be within a declared
84 * uniform range.
85 */
86 assert(range);
87 if (!range->used) {
88 range->used = true;
89 range->dst_offset = c->next_ubo_dst_offset;
90 c->next_ubo_dst_offset += range->size;
91 c->num_ubo_ranges++;
92 };
93
94 offset -= range->src_offset;
95
96 /* Adjust for where we stored the TGSI register base. */
97 indirect_offset = qir_ADD(c, indirect_offset,
98 qir_uniform_ui(c, (range->dst_offset +
99 offset)));
100
101 /* Clamp to [0, array size). Note that MIN/MAX are signed. */
102 indirect_offset = qir_MAX(c, indirect_offset, qir_uniform_ui(c, 0));
103 indirect_offset = qir_MIN(c, indirect_offset,
104 qir_uniform_ui(c, (range->dst_offset +
105 range->size - 4)));
106
107 qir_TEX_DIRECT(c, indirect_offset, qir_uniform(c, QUNIFORM_UBO_ADDR, 0));
108 c->num_texture_samples++;
109 return qir_TEX_RESULT(c);
110 }
111
112 static struct qreg *
113 ntq_get_dest(struct vc4_compile *c, nir_dest dest)
114 {
115 assert(!dest.is_ssa);
116 nir_register *reg = dest.reg.reg;
117 struct hash_entry *entry = _mesa_hash_table_search(c->def_ht, reg);
118 assert(reg->num_array_elems == 0);
119 assert(dest.reg.base_offset == 0);
120
121 struct qreg *qregs = entry->data;
122 return qregs;
123 }
124
125 static struct qreg
126 ntq_get_src(struct vc4_compile *c, nir_src src, int i)
127 {
128 struct hash_entry *entry;
129 if (src.is_ssa) {
130 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
131 assert(i < src.ssa->num_components);
132 } else {
133 nir_register *reg = src.reg.reg;
134 entry = _mesa_hash_table_search(c->def_ht, reg);
135 assert(reg->num_array_elems == 0);
136 assert(src.reg.base_offset == 0);
137 assert(i < reg->num_components);
138 }
139
140 struct qreg *qregs = entry->data;
141 return qregs[i];
142 }
143
144 static struct qreg
145 ntq_get_alu_src(struct vc4_compile *c, nir_alu_instr *instr,
146 unsigned src)
147 {
148 assert(util_is_power_of_two(instr->dest.write_mask));
149 unsigned chan = ffs(instr->dest.write_mask) - 1;
150 struct qreg r = ntq_get_src(c, instr->src[src].src,
151 instr->src[src].swizzle[chan]);
152
153 assert(!instr->src[src].abs);
154 assert(!instr->src[src].negate);
155
156 return r;
157 };
158
159 static struct qreg
160 get_swizzled_channel(struct vc4_compile *c,
161 struct qreg *srcs, int swiz)
162 {
163 switch (swiz) {
164 default:
165 case UTIL_FORMAT_SWIZZLE_NONE:
166 fprintf(stderr, "warning: unknown swizzle\n");
167 /* FALLTHROUGH */
168 case UTIL_FORMAT_SWIZZLE_0:
169 return qir_uniform_f(c, 0.0);
170 case UTIL_FORMAT_SWIZZLE_1:
171 return qir_uniform_f(c, 1.0);
172 case UTIL_FORMAT_SWIZZLE_X:
173 case UTIL_FORMAT_SWIZZLE_Y:
174 case UTIL_FORMAT_SWIZZLE_Z:
175 case UTIL_FORMAT_SWIZZLE_W:
176 return srcs[swiz];
177 }
178 }
179
180 static inline struct qreg
181 qir_SAT(struct vc4_compile *c, struct qreg val)
182 {
183 return qir_FMAX(c,
184 qir_FMIN(c, val, qir_uniform_f(c, 1.0)),
185 qir_uniform_f(c, 0.0));
186 }
187
188 static struct qreg
189 ntq_rcp(struct vc4_compile *c, struct qreg x)
190 {
191 struct qreg r = qir_RCP(c, x);
192
193 /* Apply a Newton-Raphson step to improve the accuracy. */
194 r = qir_FMUL(c, r, qir_FSUB(c,
195 qir_uniform_f(c, 2.0),
196 qir_FMUL(c, x, r)));
197
198 return r;
199 }
200
201 static struct qreg
202 ntq_rsq(struct vc4_compile *c, struct qreg x)
203 {
204 struct qreg r = qir_RSQ(c, x);
205
206 /* Apply a Newton-Raphson step to improve the accuracy. */
207 r = qir_FMUL(c, r, qir_FSUB(c,
208 qir_uniform_f(c, 1.5),
209 qir_FMUL(c,
210 qir_uniform_f(c, 0.5),
211 qir_FMUL(c, x,
212 qir_FMUL(c, r, r)))));
213
214 return r;
215 }
216
217 static struct qreg
218 qir_srgb_decode(struct vc4_compile *c, struct qreg srgb)
219 {
220 struct qreg low = qir_FMUL(c, srgb, qir_uniform_f(c, 1.0 / 12.92));
221 struct qreg high = qir_POW(c,
222 qir_FMUL(c,
223 qir_FADD(c,
224 srgb,
225 qir_uniform_f(c, 0.055)),
226 qir_uniform_f(c, 1.0 / 1.055)),
227 qir_uniform_f(c, 2.4));
228
229 qir_SF(c, qir_FSUB(c, srgb, qir_uniform_f(c, 0.04045)));
230 return qir_SEL_X_Y_NS(c, low, high);
231 }
232
233 static struct qreg
234 qir_srgb_encode(struct vc4_compile *c, struct qreg linear)
235 {
236 struct qreg low = qir_FMUL(c, linear, qir_uniform_f(c, 12.92));
237 struct qreg high = qir_FSUB(c,
238 qir_FMUL(c,
239 qir_uniform_f(c, 1.055),
240 qir_POW(c,
241 linear,
242 qir_uniform_f(c, 0.41666))),
243 qir_uniform_f(c, 0.055));
244
245 qir_SF(c, qir_FSUB(c, linear, qir_uniform_f(c, 0.0031308)));
246 return qir_SEL_X_Y_NS(c, low, high);
247 }
248
249 static struct qreg
250 ntq_umul(struct vc4_compile *c, struct qreg src0, struct qreg src1)
251 {
252 struct qreg src0_hi = qir_SHR(c, src0,
253 qir_uniform_ui(c, 24));
254 struct qreg src1_hi = qir_SHR(c, src1,
255 qir_uniform_ui(c, 24));
256
257 struct qreg hilo = qir_MUL24(c, src0_hi, src1);
258 struct qreg lohi = qir_MUL24(c, src0, src1_hi);
259 struct qreg lolo = qir_MUL24(c, src0, src1);
260
261 return qir_ADD(c, lolo, qir_SHL(c,
262 qir_ADD(c, hilo, lohi),
263 qir_uniform_ui(c, 24)));
264 }
265
266 static void
267 ntq_emit_tex(struct vc4_compile *c, nir_tex_instr *instr)
268 {
269 struct qreg s, t, r, lod, proj, compare;
270 bool is_txb = false, is_txl = false, has_proj = false;
271 unsigned unit = instr->sampler_index;
272
273 for (unsigned i = 0; i < instr->num_srcs; i++) {
274 switch (instr->src[i].src_type) {
275 case nir_tex_src_coord:
276 s = ntq_get_src(c, instr->src[i].src, 0);
277 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D)
278 t = qir_uniform_f(c, 0.5);
279 else
280 t = ntq_get_src(c, instr->src[i].src, 1);
281 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
282 r = ntq_get_src(c, instr->src[i].src, 2);
283 break;
284 case nir_tex_src_bias:
285 lod = ntq_get_src(c, instr->src[i].src, 0);
286 is_txb = true;
287 break;
288 case nir_tex_src_lod:
289 lod = ntq_get_src(c, instr->src[i].src, 0);
290 is_txl = true;
291 break;
292 case nir_tex_src_comparitor:
293 compare = ntq_get_src(c, instr->src[i].src, 0);
294 break;
295 case nir_tex_src_projector:
296 proj = qir_RCP(c, ntq_get_src(c, instr->src[i].src, 0));
297 s = qir_FMUL(c, s, proj);
298 t = qir_FMUL(c, t, proj);
299 has_proj = true;
300 break;
301 default:
302 unreachable("unknown texture source");
303 }
304 }
305
306 struct qreg texture_u[] = {
307 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit),
308 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
309 qir_uniform(c, QUNIFORM_CONSTANT, 0),
310 qir_uniform(c, QUNIFORM_CONSTANT, 0),
311 };
312 uint32_t next_texture_u = 0;
313
314 /* There is no native support for GL texture rectangle coordinates, so
315 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
316 * 1]).
317 */
318 if (instr->sampler_dim == GLSL_SAMPLER_DIM_RECT) {
319 s = qir_FMUL(c, s,
320 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_X, unit));
321 t = qir_FMUL(c, t,
322 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_Y, unit));
323 }
324
325 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE || is_txl) {
326 texture_u[2] = qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P2,
327 unit | (is_txl << 16));
328 }
329
330 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
331 struct qreg ma = qir_FMAXABS(c, qir_FMAXABS(c, s, t), r);
332 struct qreg rcp_ma = qir_RCP(c, ma);
333 s = qir_FMUL(c, s, rcp_ma);
334 t = qir_FMUL(c, t, rcp_ma);
335 r = qir_FMUL(c, r, rcp_ma);
336
337 qir_TEX_R(c, r, texture_u[next_texture_u++]);
338 } else if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
339 c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP ||
340 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
341 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
342 qir_TEX_R(c, qir_uniform(c, QUNIFORM_TEXTURE_BORDER_COLOR, unit),
343 texture_u[next_texture_u++]);
344 }
345
346 if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP) {
347 s = qir_SAT(c, s);
348 }
349
350 if (c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
351 t = qir_SAT(c, t);
352 }
353
354 qir_TEX_T(c, t, texture_u[next_texture_u++]);
355
356 if (is_txl || is_txb)
357 qir_TEX_B(c, lod, texture_u[next_texture_u++]);
358
359 qir_TEX_S(c, s, texture_u[next_texture_u++]);
360
361 c->num_texture_samples++;
362 struct qreg tex = qir_TEX_RESULT(c);
363
364 enum pipe_format format = c->key->tex[unit].format;
365
366 struct qreg unpacked[4];
367 if (util_format_is_depth_or_stencil(format)) {
368 struct qreg depthf = qir_ITOF(c, qir_SHR(c, tex,
369 qir_uniform_ui(c, 8)));
370 struct qreg normalized = qir_FMUL(c, depthf,
371 qir_uniform_f(c, 1.0f/0xffffff));
372
373 struct qreg depth_output;
374
375 struct qreg one = qir_uniform_f(c, 1.0f);
376 if (c->key->tex[unit].compare_mode) {
377 if (has_proj)
378 compare = qir_FMUL(c, compare, proj);
379
380 switch (c->key->tex[unit].compare_func) {
381 case PIPE_FUNC_NEVER:
382 depth_output = qir_uniform_f(c, 0.0f);
383 break;
384 case PIPE_FUNC_ALWAYS:
385 depth_output = one;
386 break;
387 case PIPE_FUNC_EQUAL:
388 qir_SF(c, qir_FSUB(c, compare, normalized));
389 depth_output = qir_SEL_X_0_ZS(c, one);
390 break;
391 case PIPE_FUNC_NOTEQUAL:
392 qir_SF(c, qir_FSUB(c, compare, normalized));
393 depth_output = qir_SEL_X_0_ZC(c, one);
394 break;
395 case PIPE_FUNC_GREATER:
396 qir_SF(c, qir_FSUB(c, compare, normalized));
397 depth_output = qir_SEL_X_0_NC(c, one);
398 break;
399 case PIPE_FUNC_GEQUAL:
400 qir_SF(c, qir_FSUB(c, normalized, compare));
401 depth_output = qir_SEL_X_0_NS(c, one);
402 break;
403 case PIPE_FUNC_LESS:
404 qir_SF(c, qir_FSUB(c, compare, normalized));
405 depth_output = qir_SEL_X_0_NS(c, one);
406 break;
407 case PIPE_FUNC_LEQUAL:
408 qir_SF(c, qir_FSUB(c, normalized, compare));
409 depth_output = qir_SEL_X_0_NC(c, one);
410 break;
411 }
412 } else {
413 depth_output = normalized;
414 }
415
416 for (int i = 0; i < 4; i++)
417 unpacked[i] = depth_output;
418 } else {
419 for (int i = 0; i < 4; i++)
420 unpacked[i] = qir_UNPACK_8_F(c, tex, i);
421 }
422
423 const uint8_t *format_swiz = vc4_get_format_swizzle(format);
424 struct qreg texture_output[4];
425 for (int i = 0; i < 4; i++) {
426 texture_output[i] = get_swizzled_channel(c, unpacked,
427 format_swiz[i]);
428 }
429
430 if (util_format_is_srgb(format)) {
431 for (int i = 0; i < 3; i++)
432 texture_output[i] = qir_srgb_decode(c,
433 texture_output[i]);
434 }
435
436 struct qreg *dest = ntq_get_dest(c, instr->dest);
437 for (int i = 0; i < 4; i++) {
438 dest[i] = get_swizzled_channel(c, texture_output,
439 c->key->tex[unit].swizzle[i]);
440 }
441 }
442
443 /**
444 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
445 * to zero).
446 */
447 static struct qreg
448 ntq_ffract(struct vc4_compile *c, struct qreg src)
449 {
450 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
451 struct qreg diff = qir_FSUB(c, src, trunc);
452 qir_SF(c, diff);
453 return qir_SEL_X_Y_NS(c,
454 qir_FADD(c, diff, qir_uniform_f(c, 1.0)),
455 diff);
456 }
457
458 /**
459 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
460 * zero).
461 */
462 static struct qreg
463 ntq_ffloor(struct vc4_compile *c, struct qreg src)
464 {
465 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
466
467 /* This will be < 0 if we truncated and the truncation was of a value
468 * that was < 0 in the first place.
469 */
470 qir_SF(c, qir_FSUB(c, src, trunc));
471
472 return qir_SEL_X_Y_NS(c,
473 qir_FSUB(c, trunc, qir_uniform_f(c, 1.0)),
474 trunc);
475 }
476
477 /**
478 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
479 * zero).
480 */
481 static struct qreg
482 ntq_fceil(struct vc4_compile *c, struct qreg src)
483 {
484 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
485
486 /* This will be < 0 if we truncated and the truncation was of a value
487 * that was > 0 in the first place.
488 */
489 qir_SF(c, qir_FSUB(c, trunc, src));
490
491 return qir_SEL_X_Y_NS(c,
492 qir_FADD(c, trunc, qir_uniform_f(c, 1.0)),
493 trunc);
494 }
495
496 static struct qreg
497 ntq_fsin(struct vc4_compile *c, struct qreg src)
498 {
499 float coeff[] = {
500 -2.0 * M_PI,
501 pow(2.0 * M_PI, 3) / (3 * 2 * 1),
502 -pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
503 pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
504 -pow(2.0 * M_PI, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
505 };
506
507 struct qreg scaled_x =
508 qir_FMUL(c,
509 src,
510 qir_uniform_f(c, 1.0 / (M_PI * 2.0)));
511
512 struct qreg x = qir_FADD(c,
513 ntq_ffract(c, scaled_x),
514 qir_uniform_f(c, -0.5));
515 struct qreg x2 = qir_FMUL(c, x, x);
516 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
517 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
518 x = qir_FMUL(c, x, x2);
519 sum = qir_FADD(c,
520 sum,
521 qir_FMUL(c,
522 x,
523 qir_uniform_f(c, coeff[i])));
524 }
525 return sum;
526 }
527
528 static struct qreg
529 ntq_fcos(struct vc4_compile *c, struct qreg src)
530 {
531 float coeff[] = {
532 -1.0f,
533 pow(2.0 * M_PI, 2) / (2 * 1),
534 -pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
535 pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
536 -pow(2.0 * M_PI, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
537 pow(2.0 * M_PI, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
538 };
539
540 struct qreg scaled_x =
541 qir_FMUL(c, src,
542 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
543 struct qreg x_frac = qir_FADD(c,
544 ntq_ffract(c, scaled_x),
545 qir_uniform_f(c, -0.5));
546
547 struct qreg sum = qir_uniform_f(c, coeff[0]);
548 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
549 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
550 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
551 if (i != 1)
552 x = qir_FMUL(c, x, x2);
553
554 struct qreg mul = qir_FMUL(c,
555 x,
556 qir_uniform_f(c, coeff[i]));
557 if (i == 0)
558 sum = mul;
559 else
560 sum = qir_FADD(c, sum, mul);
561 }
562 return sum;
563 }
564
565 static struct qreg
566 ntq_fsign(struct vc4_compile *c, struct qreg src)
567 {
568 qir_SF(c, src);
569 return qir_SEL_X_Y_NC(c,
570 qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0)),
571 qir_uniform_f(c, -1.0));
572 }
573
574 static struct qreg
575 get_channel_from_vpm(struct vc4_compile *c,
576 struct qreg *vpm_reads,
577 uint8_t swiz,
578 const struct util_format_description *desc)
579 {
580 const struct util_format_channel_description *chan =
581 &desc->channel[swiz];
582 struct qreg temp;
583
584 if (swiz > UTIL_FORMAT_SWIZZLE_W)
585 return get_swizzled_channel(c, vpm_reads, swiz);
586 else if (chan->size == 32 &&
587 chan->type == UTIL_FORMAT_TYPE_FLOAT) {
588 return get_swizzled_channel(c, vpm_reads, swiz);
589 } else if (chan->size == 32 &&
590 chan->type == UTIL_FORMAT_TYPE_SIGNED) {
591 if (chan->normalized) {
592 return qir_FMUL(c,
593 qir_ITOF(c, vpm_reads[swiz]),
594 qir_uniform_f(c,
595 1.0 / 0x7fffffff));
596 } else {
597 return qir_ITOF(c, vpm_reads[swiz]);
598 }
599 } else if (chan->size == 8 &&
600 (chan->type == UTIL_FORMAT_TYPE_UNSIGNED ||
601 chan->type == UTIL_FORMAT_TYPE_SIGNED)) {
602 struct qreg vpm = vpm_reads[0];
603 if (chan->type == UTIL_FORMAT_TYPE_SIGNED) {
604 temp = qir_XOR(c, vpm, qir_uniform_ui(c, 0x80808080));
605 if (chan->normalized) {
606 return qir_FSUB(c, qir_FMUL(c,
607 qir_UNPACK_8_F(c, temp, swiz),
608 qir_uniform_f(c, 2.0)),
609 qir_uniform_f(c, 1.0));
610 } else {
611 return qir_FADD(c,
612 qir_ITOF(c,
613 qir_UNPACK_8_I(c, temp,
614 swiz)),
615 qir_uniform_f(c, -128.0));
616 }
617 } else {
618 if (chan->normalized) {
619 return qir_UNPACK_8_F(c, vpm, swiz);
620 } else {
621 return qir_ITOF(c, qir_UNPACK_8_I(c, vpm, swiz));
622 }
623 }
624 } else if (chan->size == 16 &&
625 (chan->type == UTIL_FORMAT_TYPE_UNSIGNED ||
626 chan->type == UTIL_FORMAT_TYPE_SIGNED)) {
627 struct qreg vpm = vpm_reads[swiz / 2];
628
629 /* Note that UNPACK_16F eats a half float, not ints, so we use
630 * UNPACK_16_I for all of these.
631 */
632 if (chan->type == UTIL_FORMAT_TYPE_SIGNED) {
633 temp = qir_ITOF(c, qir_UNPACK_16_I(c, vpm, swiz % 2));
634 if (chan->normalized) {
635 return qir_FMUL(c, temp,
636 qir_uniform_f(c, 1/32768.0f));
637 } else {
638 return temp;
639 }
640 } else {
641 /* UNPACK_16I sign-extends, so we have to emit ANDs. */
642 temp = vpm;
643 if (swiz == 1 || swiz == 3)
644 temp = qir_UNPACK_16_I(c, temp, 1);
645 temp = qir_AND(c, temp, qir_uniform_ui(c, 0xffff));
646 temp = qir_ITOF(c, temp);
647
648 if (chan->normalized) {
649 return qir_FMUL(c, temp,
650 qir_uniform_f(c, 1 / 65535.0));
651 } else {
652 return temp;
653 }
654 }
655 } else {
656 return c->undef;
657 }
658 }
659
660 static void
661 emit_vertex_input(struct vc4_compile *c, int attr)
662 {
663 enum pipe_format format = c->vs_key->attr_formats[attr];
664 uint32_t attr_size = util_format_get_blocksize(format);
665 struct qreg vpm_reads[4];
666
667 c->vattr_sizes[attr] = align(attr_size, 4);
668 for (int i = 0; i < align(attr_size, 4) / 4; i++) {
669 struct qreg vpm = { QFILE_VPM, attr * 4 + i };
670 vpm_reads[i] = qir_MOV(c, vpm);
671 c->num_inputs++;
672 }
673
674 bool format_warned = false;
675 const struct util_format_description *desc =
676 util_format_description(format);
677
678 for (int i = 0; i < 4; i++) {
679 uint8_t swiz = desc->swizzle[i];
680 struct qreg result = get_channel_from_vpm(c, vpm_reads,
681 swiz, desc);
682
683 if (result.file == QFILE_NULL) {
684 if (!format_warned) {
685 fprintf(stderr,
686 "vtx element %d unsupported type: %s\n",
687 attr, util_format_name(format));
688 format_warned = true;
689 }
690 result = qir_uniform_f(c, 0.0);
691 }
692 c->inputs[attr * 4 + i] = result;
693 }
694 }
695
696 static void
697 emit_fragcoord_input(struct vc4_compile *c, int attr)
698 {
699 c->inputs[attr * 4 + 0] = qir_FRAG_X(c);
700 c->inputs[attr * 4 + 1] = qir_FRAG_Y(c);
701 c->inputs[attr * 4 + 2] =
702 qir_FMUL(c,
703 qir_ITOF(c, qir_FRAG_Z(c)),
704 qir_uniform_f(c, 1.0 / 0xffffff));
705 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
706 }
707
708 static struct qreg
709 emit_fragment_varying(struct vc4_compile *c, uint8_t semantic,
710 uint8_t index, uint8_t swizzle)
711 {
712 uint32_t i = c->num_input_semantics++;
713 struct qreg vary = {
714 QFILE_VARY,
715 i
716 };
717
718 if (c->num_input_semantics >= c->input_semantics_array_size) {
719 c->input_semantics_array_size =
720 MAX2(4, c->input_semantics_array_size * 2);
721
722 c->input_semantics = reralloc(c, c->input_semantics,
723 struct vc4_varying_semantic,
724 c->input_semantics_array_size);
725 }
726
727 c->input_semantics[i].semantic = semantic;
728 c->input_semantics[i].index = index;
729 c->input_semantics[i].swizzle = swizzle;
730
731 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
732 }
733
734 static void
735 emit_fragment_input(struct vc4_compile *c, int attr,
736 unsigned semantic_name, unsigned semantic_index)
737 {
738 for (int i = 0; i < 4; i++) {
739 c->inputs[attr * 4 + i] =
740 emit_fragment_varying(c,
741 semantic_name,
742 semantic_index,
743 i);
744 c->num_inputs++;
745 }
746 }
747
748 static void
749 add_output(struct vc4_compile *c,
750 uint32_t decl_offset,
751 uint8_t semantic_name,
752 uint8_t semantic_index,
753 uint8_t semantic_swizzle)
754 {
755 uint32_t old_array_size = c->outputs_array_size;
756 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
757 decl_offset + 1);
758
759 if (old_array_size != c->outputs_array_size) {
760 c->output_semantics = reralloc(c,
761 c->output_semantics,
762 struct vc4_varying_semantic,
763 c->outputs_array_size);
764 }
765
766 c->output_semantics[decl_offset].semantic = semantic_name;
767 c->output_semantics[decl_offset].index = semantic_index;
768 c->output_semantics[decl_offset].swizzle = semantic_swizzle;
769 }
770
771 static void
772 declare_uniform_range(struct vc4_compile *c, uint32_t start, uint32_t size)
773 {
774 unsigned array_id = c->num_uniform_ranges++;
775 if (array_id >= c->ubo_ranges_array_size) {
776 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
777 array_id + 1);
778 c->ubo_ranges = reralloc(c, c->ubo_ranges,
779 struct vc4_compiler_ubo_range,
780 c->ubo_ranges_array_size);
781 }
782
783 c->ubo_ranges[array_id].dst_offset = 0;
784 c->ubo_ranges[array_id].src_offset = start;
785 c->ubo_ranges[array_id].size = size;
786 c->ubo_ranges[array_id].used = false;
787 }
788
789 static void
790 ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr)
791 {
792 /* Vectors are special in that they have non-scalarized writemasks,
793 * and just take the first swizzle channel for each argument in order
794 * into each writemask channel.
795 */
796 if (instr->op == nir_op_vec2 ||
797 instr->op == nir_op_vec3 ||
798 instr->op == nir_op_vec4) {
799 struct qreg srcs[4];
800 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
801 srcs[i] = ntq_get_src(c, instr->src[i].src,
802 instr->src[i].swizzle[0]);
803 struct qreg *dest = ntq_get_dest(c, instr->dest.dest);
804 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
805 dest[i] = srcs[i];
806 return;
807 }
808
809 /* General case: We can just grab the one used channel per src. */
810 struct qreg src[nir_op_infos[instr->op].num_inputs];
811 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
812 src[i] = ntq_get_alu_src(c, instr, i);
813 }
814
815 /* Pick the channel to store the output in. */
816 assert(!instr->dest.saturate);
817 struct qreg *dest = ntq_get_dest(c, instr->dest.dest);
818 assert(util_is_power_of_two(instr->dest.write_mask));
819 dest += ffs(instr->dest.write_mask) - 1;
820
821 switch (instr->op) {
822 case nir_op_fmov:
823 case nir_op_imov:
824 *dest = qir_MOV(c, src[0]);
825 break;
826 case nir_op_fmul:
827 *dest = qir_FMUL(c, src[0], src[1]);
828 break;
829 case nir_op_fadd:
830 *dest = qir_FADD(c, src[0], src[1]);
831 break;
832 case nir_op_fsub:
833 *dest = qir_FSUB(c, src[0], src[1]);
834 break;
835 case nir_op_fmin:
836 *dest = qir_FMIN(c, src[0], src[1]);
837 break;
838 case nir_op_fmax:
839 *dest = qir_FMAX(c, src[0], src[1]);
840 break;
841
842 case nir_op_f2i:
843 case nir_op_f2u:
844 *dest = qir_FTOI(c, src[0]);
845 break;
846 case nir_op_i2f:
847 case nir_op_u2f:
848 *dest = qir_ITOF(c, src[0]);
849 break;
850 case nir_op_b2f:
851 *dest = qir_AND(c, src[0], qir_uniform_f(c, 1.0));
852 break;
853 case nir_op_b2i:
854 *dest = qir_AND(c, src[0], qir_uniform_ui(c, 1));
855 break;
856 case nir_op_i2b:
857 case nir_op_f2b:
858 qir_SF(c, src[0]);
859 *dest = qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
860 break;
861
862 case nir_op_iadd:
863 *dest = qir_ADD(c, src[0], src[1]);
864 break;
865 case nir_op_ushr:
866 *dest = qir_SHR(c, src[0], src[1]);
867 break;
868 case nir_op_isub:
869 *dest = qir_SUB(c, src[0], src[1]);
870 break;
871 case nir_op_ishr:
872 *dest = qir_ASR(c, src[0], src[1]);
873 break;
874 case nir_op_ishl:
875 *dest = qir_SHL(c, src[0], src[1]);
876 break;
877 case nir_op_imin:
878 *dest = qir_MIN(c, src[0], src[1]);
879 break;
880 case nir_op_imax:
881 *dest = qir_MAX(c, src[0], src[1]);
882 break;
883 case nir_op_iand:
884 *dest = qir_AND(c, src[0], src[1]);
885 break;
886 case nir_op_ior:
887 *dest = qir_OR(c, src[0], src[1]);
888 break;
889 case nir_op_ixor:
890 *dest = qir_XOR(c, src[0], src[1]);
891 break;
892 case nir_op_inot:
893 *dest = qir_NOT(c, src[0]);
894 break;
895
896 case nir_op_imul:
897 *dest = ntq_umul(c, src[0], src[1]);
898 break;
899
900 case nir_op_seq:
901 qir_SF(c, qir_FSUB(c, src[0], src[1]));
902 *dest = qir_SEL_X_0_ZS(c, qir_uniform_f(c, 1.0));
903 break;
904 case nir_op_sne:
905 qir_SF(c, qir_FSUB(c, src[0], src[1]));
906 *dest = qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0));
907 break;
908 case nir_op_sge:
909 qir_SF(c, qir_FSUB(c, src[0], src[1]));
910 *dest = qir_SEL_X_0_NC(c, qir_uniform_f(c, 1.0));
911 break;
912 case nir_op_slt:
913 qir_SF(c, qir_FSUB(c, src[0], src[1]));
914 *dest = qir_SEL_X_0_NS(c, qir_uniform_f(c, 1.0));
915 break;
916 case nir_op_feq:
917 qir_SF(c, qir_FSUB(c, src[0], src[1]));
918 *dest = qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
919 break;
920 case nir_op_fne:
921 qir_SF(c, qir_FSUB(c, src[0], src[1]));
922 *dest = qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
923 break;
924 case nir_op_fge:
925 qir_SF(c, qir_FSUB(c, src[0], src[1]));
926 *dest = qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
927 break;
928 case nir_op_flt:
929 qir_SF(c, qir_FSUB(c, src[0], src[1]));
930 *dest = qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
931 break;
932 case nir_op_ieq:
933 qir_SF(c, qir_SUB(c, src[0], src[1]));
934 *dest = qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
935 break;
936 case nir_op_ine:
937 qir_SF(c, qir_SUB(c, src[0], src[1]));
938 *dest = qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
939 break;
940 case nir_op_ige:
941 qir_SF(c, qir_SUB(c, src[0], src[1]));
942 *dest = qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
943 break;
944 case nir_op_ilt:
945 qir_SF(c, qir_SUB(c, src[0], src[1]));
946 *dest = qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
947 break;
948
949 case nir_op_bcsel:
950 qir_SF(c, src[0]);
951 *dest = qir_SEL_X_Y_NS(c, src[1], src[2]);
952 break;
953 case nir_op_fcsel:
954 qir_SF(c, src[0]);
955 *dest = qir_SEL_X_Y_ZC(c, src[1], src[2]);
956 break;
957
958 case nir_op_frcp:
959 *dest = ntq_rcp(c, src[0]);
960 break;
961 case nir_op_frsq:
962 *dest = ntq_rsq(c, src[0]);
963 break;
964 case nir_op_fexp2:
965 *dest = qir_EXP2(c, src[0]);
966 break;
967 case nir_op_flog2:
968 *dest = qir_LOG2(c, src[0]);
969 break;
970
971 case nir_op_ftrunc:
972 *dest = qir_ITOF(c, qir_FTOI(c, src[0]));
973 break;
974 case nir_op_fceil:
975 *dest = ntq_fceil(c, src[0]);
976 break;
977 case nir_op_ffract:
978 *dest = ntq_ffract(c, src[0]);
979 break;
980 case nir_op_ffloor:
981 *dest = ntq_ffloor(c, src[0]);
982 break;
983
984 case nir_op_fsin:
985 *dest = ntq_fsin(c, src[0]);
986 break;
987 case nir_op_fcos:
988 *dest = ntq_fcos(c, src[0]);
989 break;
990
991 case nir_op_fsign:
992 *dest = ntq_fsign(c, src[0]);
993 break;
994
995 case nir_op_fabs:
996 *dest = qir_FMAXABS(c, src[0], src[0]);
997 break;
998 case nir_op_iabs:
999 *dest = qir_MAX(c, src[0],
1000 qir_SUB(c, qir_uniform_ui(c, 0), src[0]));
1001 break;
1002
1003 default:
1004 fprintf(stderr, "unknown NIR ALU inst: ");
1005 nir_print_instr(&instr->instr, stderr);
1006 fprintf(stderr, "\n");
1007 abort();
1008 }
1009 }
1010
1011 static struct qreg
1012 vc4_blend_channel(struct vc4_compile *c,
1013 struct qreg *dst,
1014 struct qreg *src,
1015 struct qreg val,
1016 unsigned factor,
1017 int channel)
1018 {
1019 switch(factor) {
1020 case PIPE_BLENDFACTOR_ONE:
1021 return val;
1022 case PIPE_BLENDFACTOR_SRC_COLOR:
1023 return qir_FMUL(c, val, src[channel]);
1024 case PIPE_BLENDFACTOR_SRC_ALPHA:
1025 return qir_FMUL(c, val, src[3]);
1026 case PIPE_BLENDFACTOR_DST_ALPHA:
1027 return qir_FMUL(c, val, dst[3]);
1028 case PIPE_BLENDFACTOR_DST_COLOR:
1029 return qir_FMUL(c, val, dst[channel]);
1030 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
1031 if (channel != 3) {
1032 return qir_FMUL(c,
1033 val,
1034 qir_FMIN(c,
1035 src[3],
1036 qir_FSUB(c,
1037 qir_uniform_f(c, 1.0),
1038 dst[3])));
1039 } else {
1040 return val;
1041 }
1042 case PIPE_BLENDFACTOR_CONST_COLOR:
1043 return qir_FMUL(c, val,
1044 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR,
1045 channel));
1046 case PIPE_BLENDFACTOR_CONST_ALPHA:
1047 return qir_FMUL(c, val,
1048 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR, 3));
1049 case PIPE_BLENDFACTOR_ZERO:
1050 return qir_uniform_f(c, 0.0);
1051 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
1052 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1053 src[channel]));
1054 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
1055 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1056 src[3]));
1057 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
1058 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1059 dst[3]));
1060 case PIPE_BLENDFACTOR_INV_DST_COLOR:
1061 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1062 dst[channel]));
1063 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
1064 return qir_FMUL(c, val,
1065 qir_FSUB(c, qir_uniform_f(c, 1.0),
1066 qir_uniform(c,
1067 QUNIFORM_BLEND_CONST_COLOR,
1068 channel)));
1069 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
1070 return qir_FMUL(c, val,
1071 qir_FSUB(c, qir_uniform_f(c, 1.0),
1072 qir_uniform(c,
1073 QUNIFORM_BLEND_CONST_COLOR,
1074 3)));
1075
1076 default:
1077 case PIPE_BLENDFACTOR_SRC1_COLOR:
1078 case PIPE_BLENDFACTOR_SRC1_ALPHA:
1079 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
1080 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
1081 /* Unsupported. */
1082 fprintf(stderr, "Unknown blend factor %d\n", factor);
1083 return val;
1084 }
1085 }
1086
1087 static struct qreg
1088 vc4_blend_func(struct vc4_compile *c,
1089 struct qreg src, struct qreg dst,
1090 unsigned func)
1091 {
1092 switch (func) {
1093 case PIPE_BLEND_ADD:
1094 return qir_FADD(c, src, dst);
1095 case PIPE_BLEND_SUBTRACT:
1096 return qir_FSUB(c, src, dst);
1097 case PIPE_BLEND_REVERSE_SUBTRACT:
1098 return qir_FSUB(c, dst, src);
1099 case PIPE_BLEND_MIN:
1100 return qir_FMIN(c, src, dst);
1101 case PIPE_BLEND_MAX:
1102 return qir_FMAX(c, src, dst);
1103
1104 default:
1105 /* Unsupported. */
1106 fprintf(stderr, "Unknown blend func %d\n", func);
1107 return src;
1108
1109 }
1110 }
1111
1112 /**
1113 * Implements fixed function blending in shader code.
1114 *
1115 * VC4 doesn't have any hardware support for blending. Instead, you read the
1116 * current contents of the destination from the tile buffer after having
1117 * waited for the scoreboard (which is handled by vc4_qpu_emit.c), then do
1118 * math using your output color and that destination value, and update the
1119 * output color appropriately.
1120 */
1121 static void
1122 vc4_blend(struct vc4_compile *c, struct qreg *result,
1123 struct qreg *dst_color, struct qreg *src_color)
1124 {
1125 struct pipe_rt_blend_state *blend = &c->fs_key->blend;
1126
1127 if (!blend->blend_enable) {
1128 for (int i = 0; i < 4; i++)
1129 result[i] = src_color[i];
1130 return;
1131 }
1132
1133 struct qreg clamped_src[4];
1134 struct qreg clamped_dst[4];
1135 for (int i = 0; i < 4; i++) {
1136 clamped_src[i] = qir_SAT(c, src_color[i]);
1137 clamped_dst[i] = qir_SAT(c, dst_color[i]);
1138 }
1139 src_color = clamped_src;
1140 dst_color = clamped_dst;
1141
1142 struct qreg src_blend[4], dst_blend[4];
1143 for (int i = 0; i < 3; i++) {
1144 src_blend[i] = vc4_blend_channel(c,
1145 dst_color, src_color,
1146 src_color[i],
1147 blend->rgb_src_factor, i);
1148 dst_blend[i] = vc4_blend_channel(c,
1149 dst_color, src_color,
1150 dst_color[i],
1151 blend->rgb_dst_factor, i);
1152 }
1153 src_blend[3] = vc4_blend_channel(c,
1154 dst_color, src_color,
1155 src_color[3],
1156 blend->alpha_src_factor, 3);
1157 dst_blend[3] = vc4_blend_channel(c,
1158 dst_color, src_color,
1159 dst_color[3],
1160 blend->alpha_dst_factor, 3);
1161
1162 for (int i = 0; i < 3; i++) {
1163 result[i] = vc4_blend_func(c,
1164 src_blend[i], dst_blend[i],
1165 blend->rgb_func);
1166 }
1167 result[3] = vc4_blend_func(c,
1168 src_blend[3], dst_blend[3],
1169 blend->alpha_func);
1170 }
1171
1172 static void
1173 clip_distance_discard(struct vc4_compile *c)
1174 {
1175 for (int i = 0; i < PIPE_MAX_CLIP_PLANES; i++) {
1176 if (!(c->key->ucp_enables & (1 << i)))
1177 continue;
1178
1179 struct qreg dist = emit_fragment_varying(c,
1180 TGSI_SEMANTIC_CLIPDIST,
1181 i,
1182 TGSI_SWIZZLE_X);
1183
1184 qir_SF(c, dist);
1185
1186 if (c->discard.file == QFILE_NULL)
1187 c->discard = qir_uniform_ui(c, 0);
1188
1189 c->discard = qir_SEL_X_Y_NS(c, qir_uniform_ui(c, ~0),
1190 c->discard);
1191 }
1192 }
1193
1194 static void
1195 alpha_test_discard(struct vc4_compile *c)
1196 {
1197 struct qreg src_alpha;
1198 struct qreg alpha_ref = qir_uniform(c, QUNIFORM_ALPHA_REF, 0);
1199
1200 if (!c->fs_key->alpha_test)
1201 return;
1202
1203 if (c->output_color_index != -1)
1204 src_alpha = c->outputs[c->output_color_index + 3];
1205 else
1206 src_alpha = qir_uniform_f(c, 1.0);
1207
1208 if (c->discard.file == QFILE_NULL)
1209 c->discard = qir_uniform_ui(c, 0);
1210
1211 switch (c->fs_key->alpha_test_func) {
1212 case PIPE_FUNC_NEVER:
1213 c->discard = qir_uniform_ui(c, ~0);
1214 break;
1215 case PIPE_FUNC_ALWAYS:
1216 break;
1217 case PIPE_FUNC_EQUAL:
1218 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1219 c->discard = qir_SEL_X_Y_ZS(c, c->discard,
1220 qir_uniform_ui(c, ~0));
1221 break;
1222 case PIPE_FUNC_NOTEQUAL:
1223 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1224 c->discard = qir_SEL_X_Y_ZC(c, c->discard,
1225 qir_uniform_ui(c, ~0));
1226 break;
1227 case PIPE_FUNC_GREATER:
1228 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1229 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1230 qir_uniform_ui(c, ~0));
1231 break;
1232 case PIPE_FUNC_GEQUAL:
1233 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1234 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1235 qir_uniform_ui(c, ~0));
1236 break;
1237 case PIPE_FUNC_LESS:
1238 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1239 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1240 qir_uniform_ui(c, ~0));
1241 break;
1242 case PIPE_FUNC_LEQUAL:
1243 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1244 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1245 qir_uniform_ui(c, ~0));
1246 break;
1247 }
1248 }
1249
1250 static struct qreg
1251 vc4_logicop(struct vc4_compile *c, struct qreg src, struct qreg dst)
1252 {
1253 switch (c->fs_key->logicop_func) {
1254 case PIPE_LOGICOP_CLEAR:
1255 return qir_uniform_f(c, 0.0);
1256 case PIPE_LOGICOP_NOR:
1257 return qir_NOT(c, qir_OR(c, src, dst));
1258 case PIPE_LOGICOP_AND_INVERTED:
1259 return qir_AND(c, qir_NOT(c, src), dst);
1260 case PIPE_LOGICOP_COPY_INVERTED:
1261 return qir_NOT(c, src);
1262 case PIPE_LOGICOP_AND_REVERSE:
1263 return qir_AND(c, src, qir_NOT(c, dst));
1264 case PIPE_LOGICOP_INVERT:
1265 return qir_NOT(c, dst);
1266 case PIPE_LOGICOP_XOR:
1267 return qir_XOR(c, src, dst);
1268 case PIPE_LOGICOP_NAND:
1269 return qir_NOT(c, qir_AND(c, src, dst));
1270 case PIPE_LOGICOP_AND:
1271 return qir_AND(c, src, dst);
1272 case PIPE_LOGICOP_EQUIV:
1273 return qir_NOT(c, qir_XOR(c, src, dst));
1274 case PIPE_LOGICOP_NOOP:
1275 return dst;
1276 case PIPE_LOGICOP_OR_INVERTED:
1277 return qir_OR(c, qir_NOT(c, src), dst);
1278 case PIPE_LOGICOP_OR_REVERSE:
1279 return qir_OR(c, src, qir_NOT(c, dst));
1280 case PIPE_LOGICOP_OR:
1281 return qir_OR(c, src, dst);
1282 case PIPE_LOGICOP_SET:
1283 return qir_uniform_ui(c, ~0);
1284 case PIPE_LOGICOP_COPY:
1285 default:
1286 return src;
1287 }
1288 }
1289
1290 /**
1291 * Applies the GL blending pipeline and returns the packed (8888) output
1292 * color.
1293 */
1294 static struct qreg
1295 blend_pipeline(struct vc4_compile *c)
1296 {
1297 enum pipe_format color_format = c->fs_key->color_format;
1298 const uint8_t *format_swiz = vc4_get_format_swizzle(color_format);
1299 struct qreg tlb_read_color[4] = { c->undef, c->undef, c->undef, c->undef };
1300 struct qreg dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1301 struct qreg linear_dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1302 struct qreg packed_dst_color = c->undef;
1303
1304 if (c->fs_key->blend.blend_enable ||
1305 c->fs_key->blend.colormask != 0xf ||
1306 c->fs_key->logicop_func != PIPE_LOGICOP_COPY) {
1307 packed_dst_color = qir_TLB_COLOR_READ(c);
1308 for (int i = 0; i < 4; i++)
1309 tlb_read_color[i] = qir_UNPACK_8_F(c,
1310 packed_dst_color, i);
1311 for (int i = 0; i < 4; i++) {
1312 dst_color[i] = get_swizzled_channel(c,
1313 tlb_read_color,
1314 format_swiz[i]);
1315 if (util_format_is_srgb(color_format) && i != 3) {
1316 linear_dst_color[i] =
1317 qir_srgb_decode(c, dst_color[i]);
1318 } else {
1319 linear_dst_color[i] = dst_color[i];
1320 }
1321 }
1322 }
1323
1324 struct qreg undef_array[4] = { c->undef, c->undef, c->undef, c->undef };
1325 const struct qreg *output_colors = (c->output_color_index != -1 ?
1326 c->outputs + c->output_color_index :
1327 undef_array);
1328 struct qreg blend_src_color[4];
1329 for (int i = 0; i < 4; i++)
1330 blend_src_color[i] = output_colors[i];
1331
1332 struct qreg blend_color[4];
1333 vc4_blend(c, blend_color, linear_dst_color, blend_src_color);
1334
1335 if (util_format_is_srgb(color_format)) {
1336 for (int i = 0; i < 3; i++)
1337 blend_color[i] = qir_srgb_encode(c, blend_color[i]);
1338 }
1339
1340 /* Debug: Sometimes you're getting a black output and just want to see
1341 * if the FS is getting executed at all. Spam magenta into the color
1342 * output.
1343 */
1344 if (0) {
1345 blend_color[0] = qir_uniform_f(c, 1.0);
1346 blend_color[1] = qir_uniform_f(c, 0.0);
1347 blend_color[2] = qir_uniform_f(c, 1.0);
1348 blend_color[3] = qir_uniform_f(c, 0.5);
1349 }
1350
1351 struct qreg swizzled_outputs[4];
1352 for (int i = 0; i < 4; i++) {
1353 swizzled_outputs[i] = get_swizzled_channel(c, blend_color,
1354 format_swiz[i]);
1355 }
1356
1357 struct qreg packed_color = c->undef;
1358 for (int i = 0; i < 4; i++) {
1359 if (swizzled_outputs[i].file == QFILE_NULL)
1360 continue;
1361 if (packed_color.file == QFILE_NULL) {
1362 packed_color = qir_PACK_8888_F(c, swizzled_outputs[i]);
1363 } else {
1364 packed_color = qir_PACK_8_F(c,
1365 packed_color,
1366 swizzled_outputs[i],
1367 i);
1368 }
1369 }
1370
1371 if (packed_color.file == QFILE_NULL)
1372 packed_color = qir_uniform_ui(c, 0);
1373
1374 if (c->fs_key->logicop_func != PIPE_LOGICOP_COPY) {
1375 packed_color = vc4_logicop(c, packed_color, packed_dst_color);
1376 }
1377
1378 /* If the bit isn't set in the color mask, then just return the
1379 * original dst color, instead.
1380 */
1381 uint32_t colormask = 0xffffffff;
1382 for (int i = 0; i < 4; i++) {
1383 if (format_swiz[i] < 4 &&
1384 !(c->fs_key->blend.colormask & (1 << format_swiz[i]))) {
1385 colormask &= ~(0xff << (i * 8));
1386 }
1387 }
1388 if (colormask != 0xffffffff) {
1389 packed_color = qir_OR(c,
1390 qir_AND(c, packed_color,
1391 qir_uniform_ui(c, colormask)),
1392 qir_AND(c, packed_dst_color,
1393 qir_uniform_ui(c, ~colormask)));
1394 }
1395
1396 return packed_color;
1397 }
1398
1399 static void
1400 emit_frag_end(struct vc4_compile *c)
1401 {
1402 clip_distance_discard(c);
1403 alpha_test_discard(c);
1404 struct qreg color = blend_pipeline(c);
1405
1406 if (c->discard.file != QFILE_NULL)
1407 qir_TLB_DISCARD_SETUP(c, c->discard);
1408
1409 if (c->fs_key->stencil_enabled) {
1410 qir_TLB_STENCIL_SETUP(c, qir_uniform(c, QUNIFORM_STENCIL, 0));
1411 if (c->fs_key->stencil_twoside) {
1412 qir_TLB_STENCIL_SETUP(c, qir_uniform(c, QUNIFORM_STENCIL, 1));
1413 }
1414 if (c->fs_key->stencil_full_writemasks) {
1415 qir_TLB_STENCIL_SETUP(c, qir_uniform(c, QUNIFORM_STENCIL, 2));
1416 }
1417 }
1418
1419 if (c->fs_key->depth_enabled) {
1420 struct qreg z;
1421 if (c->output_position_index != -1) {
1422 z = qir_FTOI(c, qir_FMUL(c, c->outputs[c->output_position_index + 2],
1423 qir_uniform_f(c, 0xffffff)));
1424 } else {
1425 z = qir_FRAG_Z(c);
1426 }
1427 qir_TLB_Z_WRITE(c, z);
1428 }
1429
1430 qir_TLB_COLOR_WRITE(c, color);
1431 }
1432
1433 static void
1434 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1435 {
1436 struct qreg xyi[2];
1437
1438 for (int i = 0; i < 2; i++) {
1439 struct qreg scale =
1440 qir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1441
1442 xyi[i] = qir_FTOI(c, qir_FMUL(c,
1443 qir_FMUL(c,
1444 c->outputs[c->output_position_index + i],
1445 scale),
1446 rcp_w));
1447 }
1448
1449 qir_VPM_WRITE(c, qir_PACK_SCALED(c, xyi[0], xyi[1]));
1450 }
1451
1452 static void
1453 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1454 {
1455 struct qreg zscale = qir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1456 struct qreg zoffset = qir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1457
1458 qir_VPM_WRITE(c, qir_FADD(c, qir_FMUL(c, qir_FMUL(c,
1459 c->outputs[c->output_position_index + 2],
1460 zscale),
1461 rcp_w),
1462 zoffset));
1463 }
1464
1465 static void
1466 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1467 {
1468 qir_VPM_WRITE(c, rcp_w);
1469 }
1470
1471 static void
1472 emit_point_size_write(struct vc4_compile *c)
1473 {
1474 struct qreg point_size;
1475
1476 if (c->output_point_size_index != -1)
1477 point_size = c->outputs[c->output_point_size_index + 3];
1478 else
1479 point_size = qir_uniform_f(c, 1.0);
1480
1481 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1482 * BCM21553).
1483 */
1484 point_size = qir_FMAX(c, point_size, qir_uniform_f(c, .125));
1485
1486 qir_VPM_WRITE(c, point_size);
1487 }
1488
1489 /**
1490 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1491 *
1492 * The simulator insists that there be at least one vertex attribute, so
1493 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also
1494 * insists that all vertex attributes loaded get read by the VS/CS, so we have
1495 * to consume it here.
1496 */
1497 static void
1498 emit_stub_vpm_read(struct vc4_compile *c)
1499 {
1500 if (c->num_inputs)
1501 return;
1502
1503 c->vattr_sizes[0] = 4;
1504 struct qreg vpm = { QFILE_VPM, 0 };
1505 (void)qir_MOV(c, vpm);
1506 c->num_inputs++;
1507 }
1508
1509 static void
1510 emit_ucp_clipdistance(struct vc4_compile *c)
1511 {
1512 unsigned cv;
1513 if (c->output_clipvertex_index != -1)
1514 cv = c->output_clipvertex_index;
1515 else if (c->output_position_index != -1)
1516 cv = c->output_position_index;
1517 else
1518 return;
1519
1520 for (int plane = 0; plane < PIPE_MAX_CLIP_PLANES; plane++) {
1521 if (!(c->key->ucp_enables & (1 << plane)))
1522 continue;
1523
1524 /* Pick the next outputs[] that hasn't been written to, since
1525 * there are no other program writes left to be processed at
1526 * this point. If something had been declared but not written
1527 * (like a w component), we'll just smash over the top of it.
1528 */
1529 uint32_t output_index = c->num_outputs++;
1530 add_output(c, output_index,
1531 TGSI_SEMANTIC_CLIPDIST,
1532 plane,
1533 TGSI_SWIZZLE_X);
1534
1535
1536 struct qreg dist = qir_uniform_f(c, 0.0);
1537 for (int i = 0; i < 4; i++) {
1538 struct qreg pos_chan = c->outputs[cv + i];
1539 struct qreg ucp =
1540 qir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1541 plane * 4 + i);
1542 dist = qir_FADD(c, dist, qir_FMUL(c, pos_chan, ucp));
1543 }
1544
1545 c->outputs[output_index] = dist;
1546 }
1547 }
1548
1549 static void
1550 emit_vert_end(struct vc4_compile *c,
1551 struct vc4_varying_semantic *fs_inputs,
1552 uint32_t num_fs_inputs)
1553 {
1554 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1555
1556 emit_stub_vpm_read(c);
1557 emit_ucp_clipdistance(c);
1558
1559 emit_scaled_viewport_write(c, rcp_w);
1560 emit_zs_write(c, rcp_w);
1561 emit_rcp_wc_write(c, rcp_w);
1562 if (c->vs_key->per_vertex_point_size)
1563 emit_point_size_write(c);
1564
1565 for (int i = 0; i < num_fs_inputs; i++) {
1566 struct vc4_varying_semantic *input = &fs_inputs[i];
1567 int j;
1568
1569 for (j = 0; j < c->num_outputs; j++) {
1570 struct vc4_varying_semantic *output =
1571 &c->output_semantics[j];
1572
1573 if (input->semantic == output->semantic &&
1574 input->index == output->index &&
1575 input->swizzle == output->swizzle) {
1576 qir_VPM_WRITE(c, c->outputs[j]);
1577 break;
1578 }
1579 }
1580 /* Emit padding if we didn't find a declared VS output for
1581 * this FS input.
1582 */
1583 if (j == c->num_outputs)
1584 qir_VPM_WRITE(c, qir_uniform_f(c, 0.0));
1585 }
1586 }
1587
1588 static void
1589 emit_coord_end(struct vc4_compile *c)
1590 {
1591 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1592
1593 emit_stub_vpm_read(c);
1594
1595 for (int i = 0; i < 4; i++)
1596 qir_VPM_WRITE(c, c->outputs[c->output_position_index + i]);
1597
1598 emit_scaled_viewport_write(c, rcp_w);
1599 emit_zs_write(c, rcp_w);
1600 emit_rcp_wc_write(c, rcp_w);
1601 if (c->vs_key->per_vertex_point_size)
1602 emit_point_size_write(c);
1603 }
1604
1605 static void
1606 vc4_optimize_nir(struct nir_shader *s)
1607 {
1608 bool progress;
1609
1610 do {
1611 progress = false;
1612
1613 nir_lower_vars_to_ssa(s);
1614 nir_lower_alu_to_scalar(s);
1615
1616 progress = nir_copy_prop(s) || progress;
1617 progress = nir_opt_dce(s) || progress;
1618 progress = nir_opt_cse(s) || progress;
1619 progress = nir_opt_peephole_select(s) || progress;
1620 progress = nir_opt_algebraic(s) || progress;
1621 progress = nir_opt_constant_folding(s) || progress;
1622 } while (progress);
1623 }
1624
1625 static int
1626 driver_location_compare(const void *in_a, const void *in_b)
1627 {
1628 const nir_variable *const *a = in_a;
1629 const nir_variable *const *b = in_b;
1630
1631 return (*a)->data.driver_location - (*b)->data.driver_location;
1632 }
1633
1634 static void
1635 ntq_setup_inputs(struct vc4_compile *c)
1636 {
1637 unsigned num_entries = 0;
1638 foreach_list_typed(nir_variable, var, node, &c->s->inputs)
1639 num_entries++;
1640
1641 nir_variable *vars[num_entries];
1642
1643 unsigned i = 0;
1644 foreach_list_typed(nir_variable, var, node, &c->s->inputs)
1645 vars[i++] = var;
1646
1647 /* Sort the variables so that we emit the input setup in
1648 * driver_location order. This is required for VPM reads, whose data
1649 * is fetched into the VPM in driver_location (TGSI register index)
1650 * order.
1651 */
1652 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1653
1654 for (unsigned i = 0; i < num_entries; i++) {
1655 nir_variable *var = vars[i];
1656 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1657 /* XXX: map loc slots to semantics */
1658 unsigned semantic_name = var->data.location;
1659 unsigned semantic_index = var->data.index;
1660 unsigned loc = var->data.driver_location;
1661
1662 assert(array_len == 1);
1663 (void)array_len;
1664 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1665 (loc + 1) * 4);
1666
1667 if (c->stage == QSTAGE_FRAG) {
1668 if (semantic_name == TGSI_SEMANTIC_POSITION) {
1669 emit_fragcoord_input(c, loc);
1670 } else if (semantic_name == TGSI_SEMANTIC_FACE) {
1671 c->inputs[loc * 4 + 0] = qir_FRAG_REV_FLAG(c);
1672 } else if (semantic_name == TGSI_SEMANTIC_GENERIC &&
1673 (c->fs_key->point_sprite_mask &
1674 (1 << semantic_index))) {
1675 c->inputs[loc * 4 + 0] = c->point_x;
1676 c->inputs[loc * 4 + 1] = c->point_y;
1677 } else {
1678 emit_fragment_input(c, loc,
1679 semantic_name,
1680 semantic_index);
1681 }
1682 } else {
1683 emit_vertex_input(c, loc);
1684 }
1685 }
1686 }
1687
1688 static void
1689 ntq_setup_outputs(struct vc4_compile *c)
1690 {
1691 foreach_list_typed(nir_variable, var, node, &c->s->outputs) {
1692 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1693 /* XXX: map loc slots to semantics */
1694 unsigned semantic_name = var->data.location;
1695 unsigned semantic_index = var->data.index;
1696 unsigned loc = var->data.driver_location * 4;
1697
1698 assert(array_len == 1);
1699 (void)array_len;
1700
1701 /* NIR hack to pass through
1702 * TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS */
1703 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1704 semantic_index == -1)
1705 semantic_index = 0;
1706
1707 for (int i = 0; i < 4; i++) {
1708 add_output(c,
1709 loc + i,
1710 semantic_name,
1711 semantic_index,
1712 i);
1713 }
1714
1715 switch (semantic_name) {
1716 case TGSI_SEMANTIC_POSITION:
1717 c->output_position_index = loc;
1718 break;
1719 case TGSI_SEMANTIC_CLIPVERTEX:
1720 c->output_clipvertex_index = loc;
1721 break;
1722 case TGSI_SEMANTIC_COLOR:
1723 c->output_color_index = loc;
1724 break;
1725 case TGSI_SEMANTIC_PSIZE:
1726 c->output_point_size_index = loc;
1727 break;
1728 }
1729
1730 }
1731 }
1732
1733 static void
1734 ntq_setup_uniforms(struct vc4_compile *c)
1735 {
1736 foreach_list_typed(nir_variable, var, node, &c->s->uniforms) {
1737 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1738 unsigned array_elem_size = 4 * sizeof(float);
1739
1740 declare_uniform_range(c, var->data.driver_location * array_elem_size,
1741 array_len * array_elem_size);
1742
1743 }
1744 }
1745
1746 /**
1747 * Sets up the mapping from nir_register to struct qreg *.
1748 *
1749 * Each nir_register gets a struct qreg per 32-bit component being stored.
1750 */
1751 static void
1752 ntq_setup_registers(struct vc4_compile *c, struct exec_list *list)
1753 {
1754 foreach_list_typed(nir_register, nir_reg, node, list) {
1755 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1756 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1757 array_len *
1758 nir_reg->num_components);
1759
1760 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1761
1762 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1763 qregs[i] = qir_uniform_ui(c, 0);
1764 }
1765 }
1766
1767 static void
1768 ntq_emit_load_const(struct vc4_compile *c, nir_load_const_instr *instr)
1769 {
1770 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1771 instr->def.num_components);
1772 for (int i = 0; i < instr->def.num_components; i++)
1773 qregs[i] = qir_uniform_ui(c, instr->value.u[i]);
1774
1775 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1776 }
1777
1778 static void
1779 ntq_emit_intrinsic(struct vc4_compile *c, nir_intrinsic_instr *instr)
1780 {
1781 const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
1782 struct qreg *dest = NULL;
1783
1784 if (info->has_dest) {
1785 dest = ntq_get_dest(c, instr->dest);
1786 }
1787
1788 switch (instr->intrinsic) {
1789 case nir_intrinsic_load_uniform:
1790 assert(instr->num_components == 1);
1791 *dest = qir_uniform(c, QUNIFORM_UNIFORM, instr->const_index[0]);
1792 break;
1793
1794 case nir_intrinsic_load_uniform_indirect:
1795 *dest = indirect_uniform_load(c, instr);
1796
1797 break;
1798
1799 case nir_intrinsic_load_input:
1800 assert(instr->num_components == 1);
1801 *dest = c->inputs[instr->const_index[0]];
1802
1803 break;
1804
1805 case nir_intrinsic_store_output:
1806 assert(instr->num_components == 1);
1807 c->outputs[instr->const_index[0]] =
1808 qir_MOV(c, ntq_get_src(c, instr->src[0], 0));
1809 c->num_outputs = MAX2(c->num_outputs, instr->const_index[0] + 1);
1810 break;
1811
1812 case nir_intrinsic_discard:
1813 c->discard = qir_uniform_ui(c, ~0);
1814 break;
1815
1816 case nir_intrinsic_discard_if:
1817 if (c->discard.file == QFILE_NULL)
1818 c->discard = qir_uniform_ui(c, 0);
1819 c->discard = qir_OR(c, c->discard,
1820 ntq_get_src(c, instr->src[0], 0));
1821 break;
1822
1823 default:
1824 fprintf(stderr, "Unknown intrinsic: ");
1825 nir_print_instr(&instr->instr, stderr);
1826 fprintf(stderr, "\n");
1827 break;
1828 }
1829 }
1830
1831 static void
1832 ntq_emit_if(struct vc4_compile *c, nir_if *if_stmt)
1833 {
1834 fprintf(stderr, "general IF statements not handled.\n");
1835 }
1836
1837 static void
1838 ntq_emit_instr(struct vc4_compile *c, nir_instr *instr)
1839 {
1840 switch (instr->type) {
1841 case nir_instr_type_alu:
1842 ntq_emit_alu(c, nir_instr_as_alu(instr));
1843 break;
1844
1845 case nir_instr_type_intrinsic:
1846 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
1847 break;
1848
1849 case nir_instr_type_load_const:
1850 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
1851 break;
1852
1853 case nir_instr_type_tex:
1854 ntq_emit_tex(c, nir_instr_as_tex(instr));
1855 break;
1856
1857 default:
1858 fprintf(stderr, "Unknown NIR instr type: ");
1859 nir_print_instr(instr, stderr);
1860 fprintf(stderr, "\n");
1861 abort();
1862 }
1863 }
1864
1865 static void
1866 ntq_emit_block(struct vc4_compile *c, nir_block *block)
1867 {
1868 nir_foreach_instr(block, instr) {
1869 ntq_emit_instr(c, instr);
1870 }
1871 }
1872
1873 static void
1874 ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list)
1875 {
1876 foreach_list_typed(nir_cf_node, node, node, list) {
1877 switch (node->type) {
1878 /* case nir_cf_node_loop: */
1879 case nir_cf_node_block:
1880 ntq_emit_block(c, nir_cf_node_as_block(node));
1881 break;
1882
1883 case nir_cf_node_if:
1884 ntq_emit_if(c, nir_cf_node_as_if(node));
1885 break;
1886
1887 default:
1888 assert(0);
1889 }
1890 }
1891 }
1892
1893 static void
1894 ntq_emit_impl(struct vc4_compile *c, nir_function_impl *impl)
1895 {
1896 ntq_setup_registers(c, &impl->registers);
1897 ntq_emit_cf_list(c, &impl->body);
1898 }
1899
1900 static void
1901 nir_to_qir(struct vc4_compile *c)
1902 {
1903 ntq_setup_inputs(c);
1904 ntq_setup_outputs(c);
1905 ntq_setup_uniforms(c);
1906 ntq_setup_registers(c, &c->s->registers);
1907
1908 /* Find the main function and emit the body. */
1909 nir_foreach_overload(c->s, overload) {
1910 assert(strcmp(overload->function->name, "main") == 0);
1911 assert(overload->impl);
1912 ntq_emit_impl(c, overload->impl);
1913 }
1914 }
1915
1916 static const nir_shader_compiler_options nir_options = {
1917 .lower_ffma = true,
1918 .lower_flrp = true,
1919 .lower_fpow = true,
1920 .lower_fsat = true,
1921 .lower_fsqrt = true,
1922 .lower_negate = true,
1923 };
1924
1925 static bool
1926 count_nir_instrs_in_block(nir_block *block, void *state)
1927 {
1928 int *count = (int *) state;
1929 nir_foreach_instr(block, instr) {
1930 *count = *count + 1;
1931 }
1932 return true;
1933 }
1934
1935 static int
1936 count_nir_instrs(nir_shader *nir)
1937 {
1938 int count = 0;
1939 nir_foreach_overload(nir, overload) {
1940 if (!overload->impl)
1941 continue;
1942 nir_foreach_block(overload->impl, count_nir_instrs_in_block, &count);
1943 }
1944 return count;
1945 }
1946
1947 static struct vc4_compile *
1948 vc4_shader_ntq(struct vc4_context *vc4, enum qstage stage,
1949 struct vc4_key *key)
1950 {
1951 struct vc4_compile *c = qir_compile_init();
1952
1953 c->stage = stage;
1954 c->shader_state = &key->shader_state->base;
1955 c->program_id = key->shader_state->program_id;
1956 c->variant_id = key->shader_state->compiled_variant_count++;
1957
1958 c->key = key;
1959 switch (stage) {
1960 case QSTAGE_FRAG:
1961 c->fs_key = (struct vc4_fs_key *)key;
1962 if (c->fs_key->is_points) {
1963 c->point_x = emit_fragment_varying(c, ~0, ~0, 0);
1964 c->point_y = emit_fragment_varying(c, ~0, ~0, 0);
1965 } else if (c->fs_key->is_lines) {
1966 c->line_x = emit_fragment_varying(c, ~0, ~0, 0);
1967 }
1968 break;
1969 case QSTAGE_VERT:
1970 c->vs_key = (struct vc4_vs_key *)key;
1971 break;
1972 case QSTAGE_COORD:
1973 c->vs_key = (struct vc4_vs_key *)key;
1974 break;
1975 }
1976
1977 const struct tgsi_token *tokens = key->shader_state->base.tokens;
1978 if (c->fs_key && c->fs_key->light_twoside) {
1979 if (!key->shader_state->twoside_tokens) {
1980 const struct tgsi_lowering_config lowering_config = {
1981 .color_two_side = true,
1982 };
1983 struct tgsi_shader_info info;
1984 key->shader_state->twoside_tokens =
1985 tgsi_transform_lowering(&lowering_config,
1986 key->shader_state->base.tokens,
1987 &info);
1988
1989 /* If no transformation occurred, then NULL is
1990 * returned and we just use our original tokens.
1991 */
1992 if (!key->shader_state->twoside_tokens) {
1993 key->shader_state->twoside_tokens =
1994 key->shader_state->base.tokens;
1995 }
1996 }
1997 tokens = key->shader_state->twoside_tokens;
1998 }
1999
2000 if (vc4_debug & VC4_DEBUG_TGSI) {
2001 fprintf(stderr, "%s prog %d/%d TGSI:\n",
2002 qir_get_stage_name(c->stage),
2003 c->program_id, c->variant_id);
2004 tgsi_dump(tokens, 0);
2005 }
2006
2007 c->s = tgsi_to_nir(tokens, &nir_options);
2008 nir_opt_global_to_local(c->s);
2009 nir_convert_to_ssa(c->s);
2010 vc4_nir_lower_io(c);
2011 nir_lower_idiv(c->s);
2012
2013 vc4_optimize_nir(c->s);
2014
2015 nir_remove_dead_variables(c->s);
2016
2017 nir_convert_from_ssa(c->s, false);
2018
2019 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2020 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d NIR instructions\n",
2021 qir_get_stage_name(c->stage),
2022 c->program_id, c->variant_id,
2023 count_nir_instrs(c->s));
2024 }
2025
2026 if (vc4_debug & VC4_DEBUG_NIR) {
2027 fprintf(stderr, "%s prog %d/%d NIR:\n",
2028 qir_get_stage_name(c->stage),
2029 c->program_id, c->variant_id);
2030 nir_print_shader(c->s, stderr);
2031 }
2032
2033 nir_to_qir(c);
2034
2035 switch (stage) {
2036 case QSTAGE_FRAG:
2037 emit_frag_end(c);
2038 break;
2039 case QSTAGE_VERT:
2040 emit_vert_end(c,
2041 vc4->prog.fs->input_semantics,
2042 vc4->prog.fs->num_inputs);
2043 break;
2044 case QSTAGE_COORD:
2045 emit_coord_end(c);
2046 break;
2047 }
2048
2049 if (vc4_debug & VC4_DEBUG_QIR) {
2050 fprintf(stderr, "%s prog %d/%d pre-opt QIR:\n",
2051 qir_get_stage_name(c->stage),
2052 c->program_id, c->variant_id);
2053 qir_dump(c);
2054 }
2055
2056 qir_optimize(c);
2057 qir_lower_uniforms(c);
2058
2059 if (vc4_debug & VC4_DEBUG_QIR) {
2060 fprintf(stderr, "%s prog %d/%d QIR:\n",
2061 qir_get_stage_name(c->stage),
2062 c->program_id, c->variant_id);
2063 qir_dump(c);
2064 }
2065 qir_reorder_uniforms(c);
2066 vc4_generate_code(vc4, c);
2067
2068 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2069 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d instructions\n",
2070 qir_get_stage_name(c->stage),
2071 c->program_id, c->variant_id,
2072 c->qpu_inst_count);
2073 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d uniforms\n",
2074 qir_get_stage_name(c->stage),
2075 c->program_id, c->variant_id,
2076 c->num_uniforms);
2077 }
2078
2079 ralloc_free(c->s);
2080
2081 return c;
2082 }
2083
2084 static void *
2085 vc4_shader_state_create(struct pipe_context *pctx,
2086 const struct pipe_shader_state *cso)
2087 {
2088 struct vc4_context *vc4 = vc4_context(pctx);
2089 struct vc4_uncompiled_shader *so = CALLOC_STRUCT(vc4_uncompiled_shader);
2090 if (!so)
2091 return NULL;
2092
2093 so->base.tokens = tgsi_dup_tokens(cso->tokens);
2094 so->program_id = vc4->next_uncompiled_program_id++;
2095
2096 return so;
2097 }
2098
2099 static void
2100 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
2101 struct vc4_compile *c)
2102 {
2103 int count = c->num_uniforms;
2104 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
2105
2106 uinfo->count = count;
2107 uinfo->data = ralloc_array(shader, uint32_t, count);
2108 memcpy(uinfo->data, c->uniform_data,
2109 count * sizeof(*uinfo->data));
2110 uinfo->contents = ralloc_array(shader, enum quniform_contents, count);
2111 memcpy(uinfo->contents, c->uniform_contents,
2112 count * sizeof(*uinfo->contents));
2113 uinfo->num_texture_samples = c->num_texture_samples;
2114
2115 vc4_set_shader_uniform_dirty_flags(shader);
2116 }
2117
2118 static struct vc4_compiled_shader *
2119 vc4_get_compiled_shader(struct vc4_context *vc4, enum qstage stage,
2120 struct vc4_key *key)
2121 {
2122 struct hash_table *ht;
2123 uint32_t key_size;
2124 if (stage == QSTAGE_FRAG) {
2125 ht = vc4->fs_cache;
2126 key_size = sizeof(struct vc4_fs_key);
2127 } else {
2128 ht = vc4->vs_cache;
2129 key_size = sizeof(struct vc4_vs_key);
2130 }
2131
2132 struct vc4_compiled_shader *shader;
2133 struct hash_entry *entry = _mesa_hash_table_search(ht, key);
2134 if (entry)
2135 return entry->data;
2136
2137 struct vc4_compile *c = vc4_shader_ntq(vc4, stage, key);
2138 shader = rzalloc(NULL, struct vc4_compiled_shader);
2139
2140 shader->program_id = vc4->next_compiled_program_id++;
2141 if (stage == QSTAGE_FRAG) {
2142 bool input_live[c->num_input_semantics];
2143
2144 memset(input_live, 0, sizeof(input_live));
2145 list_for_each_entry(struct qinst, inst, &c->instructions, link) {
2146 for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) {
2147 if (inst->src[i].file == QFILE_VARY)
2148 input_live[inst->src[i].index] = true;
2149 }
2150 }
2151
2152 shader->input_semantics = ralloc_array(shader,
2153 struct vc4_varying_semantic,
2154 c->num_input_semantics);
2155
2156 for (int i = 0; i < c->num_input_semantics; i++) {
2157 struct vc4_varying_semantic *sem = &c->input_semantics[i];
2158
2159 if (!input_live[i])
2160 continue;
2161
2162 /* Skip non-VS-output inputs. */
2163 if (sem->semantic == (uint8_t)~0)
2164 continue;
2165
2166 if (sem->semantic == TGSI_SEMANTIC_COLOR ||
2167 sem->semantic == TGSI_SEMANTIC_BCOLOR) {
2168 shader->color_inputs |= (1 << shader->num_inputs);
2169 }
2170
2171 shader->input_semantics[shader->num_inputs] = *sem;
2172 shader->num_inputs++;
2173 }
2174 } else {
2175 shader->num_inputs = c->num_inputs;
2176
2177 shader->vattr_offsets[0] = 0;
2178 for (int i = 0; i < 8; i++) {
2179 shader->vattr_offsets[i + 1] =
2180 shader->vattr_offsets[i] + c->vattr_sizes[i];
2181
2182 if (c->vattr_sizes[i])
2183 shader->vattrs_live |= (1 << i);
2184 }
2185 }
2186
2187 copy_uniform_state_to_shader(shader, c);
2188 shader->bo = vc4_bo_alloc_shader(vc4->screen, c->qpu_insts,
2189 c->qpu_inst_count * sizeof(uint64_t));
2190
2191 /* Copy the compiler UBO range state to the compiled shader, dropping
2192 * out arrays that were never referenced by an indirect load.
2193 *
2194 * (Note that QIR dead code elimination of an array access still
2195 * leaves that array alive, though)
2196 */
2197 if (c->num_ubo_ranges) {
2198 shader->num_ubo_ranges = c->num_ubo_ranges;
2199 shader->ubo_ranges = ralloc_array(shader, struct vc4_ubo_range,
2200 c->num_ubo_ranges);
2201 uint32_t j = 0;
2202 for (int i = 0; i < c->num_uniform_ranges; i++) {
2203 struct vc4_compiler_ubo_range *range =
2204 &c->ubo_ranges[i];
2205 if (!range->used)
2206 continue;
2207
2208 shader->ubo_ranges[j].dst_offset = range->dst_offset;
2209 shader->ubo_ranges[j].src_offset = range->src_offset;
2210 shader->ubo_ranges[j].size = range->size;
2211 shader->ubo_size += c->ubo_ranges[i].size;
2212 j++;
2213 }
2214 }
2215 if (shader->ubo_size) {
2216 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2217 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d UBO uniforms\n",
2218 qir_get_stage_name(c->stage),
2219 c->program_id, c->variant_id,
2220 shader->ubo_size / 4);
2221 }
2222 }
2223
2224 qir_compile_destroy(c);
2225
2226 struct vc4_key *dup_key;
2227 dup_key = ralloc_size(shader, key_size);
2228 memcpy(dup_key, key, key_size);
2229 _mesa_hash_table_insert(ht, dup_key, shader);
2230
2231 return shader;
2232 }
2233
2234 static void
2235 vc4_setup_shared_key(struct vc4_context *vc4, struct vc4_key *key,
2236 struct vc4_texture_stateobj *texstate)
2237 {
2238 for (int i = 0; i < texstate->num_textures; i++) {
2239 struct pipe_sampler_view *sampler = texstate->textures[i];
2240 struct pipe_sampler_state *sampler_state =
2241 texstate->samplers[i];
2242
2243 if (sampler) {
2244 key->tex[i].format = sampler->format;
2245 key->tex[i].swizzle[0] = sampler->swizzle_r;
2246 key->tex[i].swizzle[1] = sampler->swizzle_g;
2247 key->tex[i].swizzle[2] = sampler->swizzle_b;
2248 key->tex[i].swizzle[3] = sampler->swizzle_a;
2249 key->tex[i].compare_mode = sampler_state->compare_mode;
2250 key->tex[i].compare_func = sampler_state->compare_func;
2251 key->tex[i].wrap_s = sampler_state->wrap_s;
2252 key->tex[i].wrap_t = sampler_state->wrap_t;
2253 }
2254 }
2255
2256 key->ucp_enables = vc4->rasterizer->base.clip_plane_enable;
2257 }
2258
2259 static void
2260 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
2261 {
2262 struct vc4_fs_key local_key;
2263 struct vc4_fs_key *key = &local_key;
2264
2265 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2266 VC4_DIRTY_BLEND |
2267 VC4_DIRTY_FRAMEBUFFER |
2268 VC4_DIRTY_ZSA |
2269 VC4_DIRTY_RASTERIZER |
2270 VC4_DIRTY_FRAGTEX |
2271 VC4_DIRTY_TEXSTATE |
2272 VC4_DIRTY_UNCOMPILED_FS))) {
2273 return;
2274 }
2275
2276 memset(key, 0, sizeof(*key));
2277 vc4_setup_shared_key(vc4, &key->base, &vc4->fragtex);
2278 key->base.shader_state = vc4->prog.bind_fs;
2279 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
2280 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
2281 prim_mode <= PIPE_PRIM_LINE_STRIP);
2282 key->blend = vc4->blend->rt[0];
2283 if (vc4->blend->logicop_enable) {
2284 key->logicop_func = vc4->blend->logicop_func;
2285 } else {
2286 key->logicop_func = PIPE_LOGICOP_COPY;
2287 }
2288 if (vc4->framebuffer.cbufs[0])
2289 key->color_format = vc4->framebuffer.cbufs[0]->format;
2290
2291 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
2292 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
2293 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
2294 key->depth_enabled = (vc4->zsa->base.depth.enabled ||
2295 key->stencil_enabled);
2296 if (vc4->zsa->base.alpha.enabled) {
2297 key->alpha_test = true;
2298 key->alpha_test_func = vc4->zsa->base.alpha.func;
2299 }
2300
2301 if (key->is_points) {
2302 key->point_sprite_mask =
2303 vc4->rasterizer->base.sprite_coord_enable;
2304 key->point_coord_upper_left =
2305 (vc4->rasterizer->base.sprite_coord_mode ==
2306 PIPE_SPRITE_COORD_UPPER_LEFT);
2307 }
2308
2309 key->light_twoside = vc4->rasterizer->base.light_twoside;
2310
2311 struct vc4_compiled_shader *old_fs = vc4->prog.fs;
2312 vc4->prog.fs = vc4_get_compiled_shader(vc4, QSTAGE_FRAG, &key->base);
2313 if (vc4->prog.fs == old_fs)
2314 return;
2315
2316 vc4->dirty |= VC4_DIRTY_COMPILED_FS;
2317 if (vc4->rasterizer->base.flatshade &&
2318 old_fs && vc4->prog.fs->color_inputs != old_fs->color_inputs) {
2319 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
2320 }
2321 }
2322
2323 static void
2324 vc4_update_compiled_vs(struct vc4_context *vc4, uint8_t prim_mode)
2325 {
2326 struct vc4_vs_key local_key;
2327 struct vc4_vs_key *key = &local_key;
2328
2329 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2330 VC4_DIRTY_RASTERIZER |
2331 VC4_DIRTY_VERTTEX |
2332 VC4_DIRTY_TEXSTATE |
2333 VC4_DIRTY_VTXSTATE |
2334 VC4_DIRTY_UNCOMPILED_VS |
2335 VC4_DIRTY_COMPILED_FS))) {
2336 return;
2337 }
2338
2339 memset(key, 0, sizeof(*key));
2340 vc4_setup_shared_key(vc4, &key->base, &vc4->verttex);
2341 key->base.shader_state = vc4->prog.bind_vs;
2342 key->compiled_fs_id = vc4->prog.fs->program_id;
2343
2344 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
2345 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
2346
2347 key->per_vertex_point_size =
2348 (prim_mode == PIPE_PRIM_POINTS &&
2349 vc4->rasterizer->base.point_size_per_vertex);
2350
2351 struct vc4_compiled_shader *vs =
2352 vc4_get_compiled_shader(vc4, QSTAGE_VERT, &key->base);
2353 if (vs != vc4->prog.vs) {
2354 vc4->prog.vs = vs;
2355 vc4->dirty |= VC4_DIRTY_COMPILED_VS;
2356 }
2357
2358 key->is_coord = true;
2359 struct vc4_compiled_shader *cs =
2360 vc4_get_compiled_shader(vc4, QSTAGE_COORD, &key->base);
2361 if (cs != vc4->prog.cs) {
2362 vc4->prog.cs = cs;
2363 vc4->dirty |= VC4_DIRTY_COMPILED_CS;
2364 }
2365 }
2366
2367 void
2368 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
2369 {
2370 vc4_update_compiled_fs(vc4, prim_mode);
2371 vc4_update_compiled_vs(vc4, prim_mode);
2372 }
2373
2374 static uint32_t
2375 fs_cache_hash(const void *key)
2376 {
2377 return _mesa_hash_data(key, sizeof(struct vc4_fs_key));
2378 }
2379
2380 static uint32_t
2381 vs_cache_hash(const void *key)
2382 {
2383 return _mesa_hash_data(key, sizeof(struct vc4_vs_key));
2384 }
2385
2386 static bool
2387 fs_cache_compare(const void *key1, const void *key2)
2388 {
2389 return memcmp(key1, key2, sizeof(struct vc4_fs_key)) == 0;
2390 }
2391
2392 static bool
2393 vs_cache_compare(const void *key1, const void *key2)
2394 {
2395 return memcmp(key1, key2, sizeof(struct vc4_vs_key)) == 0;
2396 }
2397
2398 static void
2399 delete_from_cache_if_matches(struct hash_table *ht,
2400 struct hash_entry *entry,
2401 struct vc4_uncompiled_shader *so)
2402 {
2403 const struct vc4_key *key = entry->key;
2404
2405 if (key->shader_state == so) {
2406 struct vc4_compiled_shader *shader = entry->data;
2407 _mesa_hash_table_remove(ht, entry);
2408 vc4_bo_unreference(&shader->bo);
2409 ralloc_free(shader);
2410 }
2411 }
2412
2413 static void
2414 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
2415 {
2416 struct vc4_context *vc4 = vc4_context(pctx);
2417 struct vc4_uncompiled_shader *so = hwcso;
2418
2419 struct hash_entry *entry;
2420 hash_table_foreach(vc4->fs_cache, entry)
2421 delete_from_cache_if_matches(vc4->fs_cache, entry, so);
2422 hash_table_foreach(vc4->vs_cache, entry)
2423 delete_from_cache_if_matches(vc4->vs_cache, entry, so);
2424
2425 if (so->twoside_tokens != so->base.tokens)
2426 free((void *)so->twoside_tokens);
2427 free((void *)so->base.tokens);
2428 free(so);
2429 }
2430
2431 static void
2432 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
2433 {
2434 struct vc4_context *vc4 = vc4_context(pctx);
2435 vc4->prog.bind_fs = hwcso;
2436 vc4->dirty |= VC4_DIRTY_UNCOMPILED_FS;
2437 }
2438
2439 static void
2440 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
2441 {
2442 struct vc4_context *vc4 = vc4_context(pctx);
2443 vc4->prog.bind_vs = hwcso;
2444 vc4->dirty |= VC4_DIRTY_UNCOMPILED_VS;
2445 }
2446
2447 void
2448 vc4_program_init(struct pipe_context *pctx)
2449 {
2450 struct vc4_context *vc4 = vc4_context(pctx);
2451
2452 pctx->create_vs_state = vc4_shader_state_create;
2453 pctx->delete_vs_state = vc4_shader_state_delete;
2454
2455 pctx->create_fs_state = vc4_shader_state_create;
2456 pctx->delete_fs_state = vc4_shader_state_delete;
2457
2458 pctx->bind_fs_state = vc4_fp_state_bind;
2459 pctx->bind_vs_state = vc4_vp_state_bind;
2460
2461 vc4->fs_cache = _mesa_hash_table_create(pctx, fs_cache_hash,
2462 fs_cache_compare);
2463 vc4->vs_cache = _mesa_hash_table_create(pctx, vs_cache_hash,
2464 vs_cache_compare);
2465 }
2466
2467 void
2468 vc4_program_fini(struct pipe_context *pctx)
2469 {
2470 struct vc4_context *vc4 = vc4_context(pctx);
2471
2472 struct hash_entry *entry;
2473 hash_table_foreach(vc4->fs_cache, entry) {
2474 struct vc4_compiled_shader *shader = entry->data;
2475 vc4_bo_unreference(&shader->bo);
2476 ralloc_free(shader);
2477 _mesa_hash_table_remove(vc4->fs_cache, entry);
2478 }
2479
2480 hash_table_foreach(vc4->vs_cache, entry) {
2481 struct vc4_compiled_shader *shader = entry->data;
2482 vc4_bo_unreference(&shader->bo);
2483 ralloc_free(shader);
2484 _mesa_hash_table_remove(vc4->vs_cache, entry);
2485 }
2486 }