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[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "pipe/p_state.h"
27 #include "util/u_format.h"
28 #include "util/u_hash_table.h"
29 #include "util/u_hash.h"
30 #include "util/u_memory.h"
31 #include "util/ralloc.h"
32 #include "tgsi/tgsi_dump.h"
33 #include "tgsi/tgsi_info.h"
34
35 #include "vc4_context.h"
36 #include "vc4_qpu.h"
37 #include "vc4_qir.h"
38 #ifdef USE_VC4_SIMULATOR
39 #include "simpenrose/simpenrose.h"
40 #endif
41
42 struct vc4_key {
43 struct pipe_shader_state *shader_state;
44 struct {
45 enum pipe_format format;
46 unsigned compare_mode:1;
47 unsigned compare_func:3;
48 uint8_t swizzle[4];
49 } tex[VC4_MAX_TEXTURE_SAMPLERS];
50 };
51
52 struct vc4_fs_key {
53 struct vc4_key base;
54 enum pipe_format color_format;
55 bool depth_enabled;
56 bool stencil_enabled;
57 bool stencil_twoside;
58 bool stencil_full_writemasks;
59 bool is_points;
60 bool is_lines;
61
62 struct pipe_rt_blend_state blend;
63 };
64
65 struct vc4_vs_key {
66 struct vc4_key base;
67 enum pipe_format attr_formats[8];
68 };
69
70 static void
71 resize_qreg_array(struct vc4_compile *c,
72 struct qreg **regs,
73 uint32_t *size,
74 uint32_t decl_size)
75 {
76 if (*size >= decl_size)
77 return;
78
79 uint32_t old_size = *size;
80 *size = MAX2(*size * 2, decl_size);
81 *regs = reralloc(c, *regs, struct qreg, *size);
82 if (!*regs) {
83 fprintf(stderr, "Malloc failure\n");
84 abort();
85 }
86
87 for (uint32_t i = old_size; i < *size; i++)
88 (*regs)[i] = c->undef;
89 }
90
91 static struct qreg
92 add_uniform(struct vc4_compile *c,
93 enum quniform_contents contents,
94 uint32_t data)
95 {
96 uint32_t uniform = c->num_uniforms++;
97 struct qreg u = { QFILE_UNIF, uniform };
98
99 c->uniform_contents[uniform] = contents;
100 c->uniform_data[uniform] = data;
101
102 return u;
103 }
104
105 static struct qreg
106 get_temp_for_uniform(struct vc4_compile *c, enum quniform_contents contents,
107 uint32_t data)
108 {
109 for (int i = 0; i < c->num_uniforms; i++) {
110 if (c->uniform_contents[i] == contents &&
111 c->uniform_data[i] == data)
112 return c->uniforms[i];
113 }
114
115 struct qreg u = add_uniform(c, contents, data);
116 struct qreg t = qir_MOV(c, u);
117
118 resize_qreg_array(c, &c->uniforms, &c->uniforms_array_size,
119 u.index + 1);
120
121 c->uniforms[u.index] = t;
122 return t;
123 }
124
125 static struct qreg
126 qir_uniform_ui(struct vc4_compile *c, uint32_t ui)
127 {
128 return get_temp_for_uniform(c, QUNIFORM_CONSTANT, ui);
129 }
130
131 static struct qreg
132 qir_uniform_f(struct vc4_compile *c, float f)
133 {
134 return qir_uniform_ui(c, fui(f));
135 }
136
137 static struct qreg
138 get_src(struct vc4_compile *c, unsigned tgsi_op,
139 struct tgsi_src_register *src, int i)
140 {
141 struct qreg r = c->undef;
142
143 uint32_t s = i;
144 switch (i) {
145 case TGSI_SWIZZLE_X:
146 s = src->SwizzleX;
147 break;
148 case TGSI_SWIZZLE_Y:
149 s = src->SwizzleY;
150 break;
151 case TGSI_SWIZZLE_Z:
152 s = src->SwizzleZ;
153 break;
154 case TGSI_SWIZZLE_W:
155 s = src->SwizzleW;
156 break;
157 default:
158 abort();
159 }
160
161 assert(!src->Indirect);
162
163 switch (src->File) {
164 case TGSI_FILE_NULL:
165 return r;
166 case TGSI_FILE_TEMPORARY:
167 r = c->temps[src->Index * 4 + s];
168 break;
169 case TGSI_FILE_IMMEDIATE:
170 r = c->consts[src->Index * 4 + s];
171 break;
172 case TGSI_FILE_CONSTANT:
173 r = get_temp_for_uniform(c, QUNIFORM_UNIFORM,
174 src->Index * 4 + s);
175 break;
176 case TGSI_FILE_INPUT:
177 r = c->inputs[src->Index * 4 + s];
178 break;
179 case TGSI_FILE_SAMPLER:
180 case TGSI_FILE_SAMPLER_VIEW:
181 r = c->undef;
182 break;
183 default:
184 fprintf(stderr, "unknown src file %d\n", src->File);
185 abort();
186 }
187
188 if (src->Absolute)
189 r = qir_FMAXABS(c, r, r);
190
191 if (src->Negate) {
192 switch (tgsi_opcode_infer_src_type(tgsi_op)) {
193 case TGSI_TYPE_SIGNED:
194 case TGSI_TYPE_UNSIGNED:
195 r = qir_SUB(c, qir_uniform_ui(c, 0), r);
196 break;
197 default:
198 r = qir_FSUB(c, qir_uniform_f(c, 0.0), r);
199 break;
200 }
201 }
202
203 return r;
204 };
205
206
207 static void
208 update_dst(struct vc4_compile *c, struct tgsi_full_instruction *tgsi_inst,
209 int i, struct qreg val)
210 {
211 struct tgsi_dst_register *tgsi_dst = &tgsi_inst->Dst[0].Register;
212
213 assert(!tgsi_dst->Indirect);
214
215 switch (tgsi_dst->File) {
216 case TGSI_FILE_TEMPORARY:
217 c->temps[tgsi_dst->Index * 4 + i] = val;
218 break;
219 case TGSI_FILE_OUTPUT:
220 c->outputs[tgsi_dst->Index * 4 + i] = val;
221 c->num_outputs = MAX2(c->num_outputs,
222 tgsi_dst->Index * 4 + i + 1);
223 break;
224 default:
225 fprintf(stderr, "unknown dst file %d\n", tgsi_dst->File);
226 abort();
227 }
228 };
229
230 static struct qreg
231 get_swizzled_channel(struct vc4_compile *c,
232 struct qreg *srcs, int swiz)
233 {
234 switch (swiz) {
235 default:
236 case UTIL_FORMAT_SWIZZLE_NONE:
237 fprintf(stderr, "warning: unknown swizzle\n");
238 /* FALLTHROUGH */
239 case UTIL_FORMAT_SWIZZLE_0:
240 return qir_uniform_f(c, 0.0);
241 case UTIL_FORMAT_SWIZZLE_1:
242 return qir_uniform_f(c, 1.0);
243 case UTIL_FORMAT_SWIZZLE_X:
244 case UTIL_FORMAT_SWIZZLE_Y:
245 case UTIL_FORMAT_SWIZZLE_Z:
246 case UTIL_FORMAT_SWIZZLE_W:
247 return srcs[swiz];
248 }
249 }
250
251 static struct qreg
252 tgsi_to_qir_alu(struct vc4_compile *c,
253 struct tgsi_full_instruction *tgsi_inst,
254 enum qop op, struct qreg *src, int i)
255 {
256 struct qreg dst = qir_get_temp(c);
257 qir_emit(c, qir_inst4(op, dst,
258 src[0 * 4 + i],
259 src[1 * 4 + i],
260 src[2 * 4 + i],
261 c->undef));
262 return dst;
263 }
264
265 static struct qreg
266 tgsi_to_qir_umul(struct vc4_compile *c,
267 struct tgsi_full_instruction *tgsi_inst,
268 enum qop op, struct qreg *src, int i)
269 {
270 struct qreg src0_hi = qir_SHR(c, src[0 * 4 + i],
271 qir_uniform_ui(c, 16));
272 struct qreg src0_lo = qir_AND(c, src[0 * 4 + i],
273 qir_uniform_ui(c, 0xffff));
274 struct qreg src1_hi = qir_SHR(c, src[1 * 4 + i],
275 qir_uniform_ui(c, 16));
276 struct qreg src1_lo = qir_AND(c, src[1 * 4 + i],
277 qir_uniform_ui(c, 0xffff));
278
279 struct qreg hilo = qir_MUL24(c, src0_hi, src1_lo);
280 struct qreg lohi = qir_MUL24(c, src0_lo, src1_hi);
281 struct qreg lolo = qir_MUL24(c, src0_lo, src1_lo);
282
283 return qir_ADD(c, lolo, qir_SHL(c,
284 qir_ADD(c, hilo, lohi),
285 qir_uniform_ui(c, 16)));
286 }
287
288 static struct qreg
289 tgsi_to_qir_idiv(struct vc4_compile *c,
290 struct tgsi_full_instruction *tgsi_inst,
291 enum qop op, struct qreg *src, int i)
292 {
293 return qir_FTOI(c, qir_FMUL(c,
294 qir_ITOF(c, src[0 * 4 + i]),
295 qir_RCP(c, qir_ITOF(c, src[1 * 4 + i]))));
296 }
297
298 static struct qreg
299 tgsi_to_qir_ineg(struct vc4_compile *c,
300 struct tgsi_full_instruction *tgsi_inst,
301 enum qop op, struct qreg *src, int i)
302 {
303 return qir_SUB(c, qir_uniform_ui(c, 0), src[0 * 4 + i]);
304 }
305
306 static struct qreg
307 tgsi_to_qir_seq(struct vc4_compile *c,
308 struct tgsi_full_instruction *tgsi_inst,
309 enum qop op, struct qreg *src, int i)
310 {
311 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
312 return qir_SEL_X_0_ZS(c, qir_uniform_f(c, 1.0));
313 }
314
315 static struct qreg
316 tgsi_to_qir_sne(struct vc4_compile *c,
317 struct tgsi_full_instruction *tgsi_inst,
318 enum qop op, struct qreg *src, int i)
319 {
320 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
321 return qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0));
322 }
323
324 static struct qreg
325 tgsi_to_qir_slt(struct vc4_compile *c,
326 struct tgsi_full_instruction *tgsi_inst,
327 enum qop op, struct qreg *src, int i)
328 {
329 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
330 return qir_SEL_X_0_NS(c, qir_uniform_f(c, 1.0));
331 }
332
333 static struct qreg
334 tgsi_to_qir_sge(struct vc4_compile *c,
335 struct tgsi_full_instruction *tgsi_inst,
336 enum qop op, struct qreg *src, int i)
337 {
338 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
339 return qir_SEL_X_0_NC(c, qir_uniform_f(c, 1.0));
340 }
341
342 static struct qreg
343 tgsi_to_qir_fseq(struct vc4_compile *c,
344 struct tgsi_full_instruction *tgsi_inst,
345 enum qop op, struct qreg *src, int i)
346 {
347 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
348 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
349 }
350
351 static struct qreg
352 tgsi_to_qir_fsne(struct vc4_compile *c,
353 struct tgsi_full_instruction *tgsi_inst,
354 enum qop op, struct qreg *src, int i)
355 {
356 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
357 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
358 }
359
360 static struct qreg
361 tgsi_to_qir_fslt(struct vc4_compile *c,
362 struct tgsi_full_instruction *tgsi_inst,
363 enum qop op, struct qreg *src, int i)
364 {
365 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
366 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
367 }
368
369 static struct qreg
370 tgsi_to_qir_fsge(struct vc4_compile *c,
371 struct tgsi_full_instruction *tgsi_inst,
372 enum qop op, struct qreg *src, int i)
373 {
374 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
375 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
376 }
377
378 static struct qreg
379 tgsi_to_qir_useq(struct vc4_compile *c,
380 struct tgsi_full_instruction *tgsi_inst,
381 enum qop op, struct qreg *src, int i)
382 {
383 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
384 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
385 }
386
387 static struct qreg
388 tgsi_to_qir_usne(struct vc4_compile *c,
389 struct tgsi_full_instruction *tgsi_inst,
390 enum qop op, struct qreg *src, int i)
391 {
392 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
393 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
394 }
395
396 static struct qreg
397 tgsi_to_qir_islt(struct vc4_compile *c,
398 struct tgsi_full_instruction *tgsi_inst,
399 enum qop op, struct qreg *src, int i)
400 {
401 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
402 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
403 }
404
405 static struct qreg
406 tgsi_to_qir_isge(struct vc4_compile *c,
407 struct tgsi_full_instruction *tgsi_inst,
408 enum qop op, struct qreg *src, int i)
409 {
410 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
411 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
412 }
413
414 static struct qreg
415 tgsi_to_qir_cmp(struct vc4_compile *c,
416 struct tgsi_full_instruction *tgsi_inst,
417 enum qop op, struct qreg *src, int i)
418 {
419 qir_SF(c, src[0 * 4 + i]);
420 return qir_SEL_X_Y_NS(c,
421 src[1 * 4 + i],
422 src[2 * 4 + i]);
423 }
424
425 static struct qreg
426 tgsi_to_qir_mad(struct vc4_compile *c,
427 struct tgsi_full_instruction *tgsi_inst,
428 enum qop op, struct qreg *src, int i)
429 {
430 return qir_FADD(c,
431 qir_FMUL(c,
432 src[0 * 4 + i],
433 src[1 * 4 + i]),
434 src[2 * 4 + i]);
435 }
436
437 static struct qreg
438 tgsi_to_qir_lit(struct vc4_compile *c,
439 struct tgsi_full_instruction *tgsi_inst,
440 enum qop op, struct qreg *src, int i)
441 {
442 struct qreg x = src[0 * 4 + 0];
443 struct qreg y = src[0 * 4 + 1];
444 struct qreg w = src[0 * 4 + 3];
445
446 switch (i) {
447 case 0:
448 case 3:
449 return qir_uniform_f(c, 1.0);
450 case 1:
451 return qir_FMAX(c, src[0 * 4 + 0], qir_uniform_f(c, 0.0));
452 case 2: {
453 struct qreg zero = qir_uniform_f(c, 0.0);
454
455 qir_SF(c, x);
456 /* XXX: Clamp w to -128..128 */
457 return qir_SEL_X_0_NC(c,
458 qir_EXP2(c, qir_FMUL(c,
459 w,
460 qir_LOG2(c,
461 qir_FMAX(c,
462 y,
463 zero)))));
464 }
465 default:
466 assert(!"not reached");
467 return c->undef;
468 }
469 }
470
471 static struct qreg
472 tgsi_to_qir_lrp(struct vc4_compile *c,
473 struct tgsi_full_instruction *tgsi_inst,
474 enum qop op, struct qreg *src, int i)
475 {
476 struct qreg src0 = src[0 * 4 + i];
477 struct qreg src1 = src[1 * 4 + i];
478 struct qreg src2 = src[2 * 4 + i];
479
480 /* LRP is:
481 * src0 * src1 + (1 - src0) * src2.
482 * -> src0 * src1 + src2 - src0 * src2
483 * -> src2 + src0 * (src1 - src2)
484 */
485 return qir_FADD(c, src2, qir_FMUL(c, src0, qir_FSUB(c, src1, src2)));
486
487 }
488
489 static void
490 tgsi_to_qir_tex(struct vc4_compile *c,
491 struct tgsi_full_instruction *tgsi_inst,
492 enum qop op, struct qreg *src)
493 {
494 assert(!tgsi_inst->Instruction.Saturate);
495
496 struct qreg s = src[0 * 4 + 0];
497 struct qreg t = src[0 * 4 + 1];
498 uint32_t unit = tgsi_inst->Src[1].Register.Index;
499
500 struct qreg proj = c->undef;
501 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
502 proj = qir_RCP(c, src[0 * 4 + 3]);
503 s = qir_FMUL(c, s, proj);
504 t = qir_FMUL(c, t, proj);
505 }
506
507 /* There is no native support for GL texture rectangle coordinates, so
508 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
509 * 1]).
510 */
511 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_RECT ||
512 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT) {
513 s = qir_FMUL(c, s,
514 get_temp_for_uniform(c,
515 QUNIFORM_TEXRECT_SCALE_X,
516 unit));
517 t = qir_FMUL(c, t,
518 get_temp_for_uniform(c,
519 QUNIFORM_TEXRECT_SCALE_Y,
520 unit));
521 }
522
523 qir_TEX_T(c, t, add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit));
524
525 struct qreg sampler_p1 = add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1,
526 unit);
527 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB) {
528 qir_TEX_B(c, src[0 * 4 + 3], sampler_p1);
529 qir_TEX_S(c, s, add_uniform(c, QUNIFORM_CONSTANT, 0));
530 } else {
531 qir_TEX_S(c, s, sampler_p1);
532 }
533
534 c->num_texture_samples++;
535 struct qreg r4 = qir_TEX_RESULT(c);
536
537 enum pipe_format format = c->key->tex[unit].format;
538
539 struct qreg unpacked[4];
540 if (util_format_is_depth_or_stencil(format)) {
541 struct qreg depthf = qir_ITOF(c, qir_SHR(c, r4,
542 qir_uniform_ui(c, 8)));
543 struct qreg normalized = qir_FMUL(c, depthf,
544 qir_uniform_f(c, 1.0f/0xffffff));
545
546 struct qreg depth_output;
547
548 struct qreg compare = src[0 * 4 + 2];
549
550 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP)
551 compare = qir_FMUL(c, compare, proj);
552
553 struct qreg one = qir_uniform_f(c, 1.0f);
554 if (c->key->tex[unit].compare_mode) {
555 switch (c->key->tex[unit].compare_func) {
556 case PIPE_FUNC_NEVER:
557 depth_output = qir_uniform_f(c, 0.0f);
558 break;
559 case PIPE_FUNC_ALWAYS:
560 depth_output = one;
561 break;
562 case PIPE_FUNC_EQUAL:
563 qir_SF(c, qir_FSUB(c, compare, normalized));
564 depth_output = qir_SEL_X_0_ZS(c, one);
565 break;
566 case PIPE_FUNC_NOTEQUAL:
567 qir_SF(c, qir_FSUB(c, compare, normalized));
568 depth_output = qir_SEL_X_0_ZC(c, one);
569 break;
570 case PIPE_FUNC_GREATER:
571 qir_SF(c, qir_FSUB(c, compare, normalized));
572 depth_output = qir_SEL_X_0_NC(c, one);
573 break;
574 case PIPE_FUNC_GEQUAL:
575 qir_SF(c, qir_FSUB(c, normalized, compare));
576 depth_output = qir_SEL_X_0_NS(c, one);
577 break;
578 case PIPE_FUNC_LESS:
579 qir_SF(c, qir_FSUB(c, compare, normalized));
580 depth_output = qir_SEL_X_0_NS(c, one);
581 break;
582 case PIPE_FUNC_LEQUAL:
583 qir_SF(c, qir_FSUB(c, normalized, compare));
584 depth_output = qir_SEL_X_0_NC(c, one);
585 break;
586 }
587 } else {
588 depth_output = normalized;
589 }
590
591 for (int i = 0; i < 4; i++)
592 unpacked[i] = depth_output;
593 } else {
594 for (int i = 0; i < 4; i++)
595 unpacked[i] = qir_R4_UNPACK(c, r4, i);
596 }
597
598 const uint8_t *format_swiz = vc4_get_format_swizzle(format);
599 uint8_t swiz[4];
600 util_format_compose_swizzles(format_swiz, c->key->tex[unit].swizzle, swiz);
601 for (int i = 0; i < 4; i++) {
602 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
603 continue;
604
605 update_dst(c, tgsi_inst, i,
606 get_swizzled_channel(c, unpacked, swiz[i]));
607 }
608 }
609
610 static struct qreg
611 tgsi_to_qir_pow(struct vc4_compile *c,
612 struct tgsi_full_instruction *tgsi_inst,
613 enum qop op, struct qreg *src, int i)
614 {
615 /* Note that this instruction replicates its result from the x channel
616 */
617 return qir_EXP2(c, qir_FMUL(c,
618 src[1 * 4 + 0],
619 qir_LOG2(c, src[0 * 4 + 0])));
620 }
621
622 static struct qreg
623 tgsi_to_qir_trunc(struct vc4_compile *c,
624 struct tgsi_full_instruction *tgsi_inst,
625 enum qop op, struct qreg *src, int i)
626 {
627 return qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
628 }
629
630 /**
631 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
632 * to zero).
633 */
634 static struct qreg
635 tgsi_to_qir_frc(struct vc4_compile *c,
636 struct tgsi_full_instruction *tgsi_inst,
637 enum qop op, struct qreg *src, int i)
638 {
639 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
640 struct qreg diff = qir_FSUB(c, src[0 * 4 + i], trunc);
641 qir_SF(c, diff);
642 return qir_SEL_X_Y_NS(c,
643 qir_FADD(c, diff, qir_uniform_f(c, 1.0)),
644 diff);
645 }
646
647 /**
648 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
649 * zero).
650 */
651 static struct qreg
652 tgsi_to_qir_flr(struct vc4_compile *c,
653 struct tgsi_full_instruction *tgsi_inst,
654 enum qop op, struct qreg *src, int i)
655 {
656 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
657
658 /* This will be < 0 if we truncated and the truncation was of a value
659 * that was < 0 in the first place.
660 */
661 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], trunc));
662
663 return qir_SEL_X_Y_NS(c,
664 qir_FSUB(c, trunc, qir_uniform_f(c, 1.0)),
665 trunc);
666 }
667
668 static struct qreg
669 tgsi_to_qir_dp(struct vc4_compile *c,
670 struct tgsi_full_instruction *tgsi_inst,
671 int num, struct qreg *src, int i)
672 {
673 struct qreg sum = qir_FMUL(c, src[0 * 4 + 0], src[1 * 4 + 0]);
674 for (int j = 1; j < num; j++) {
675 sum = qir_FADD(c, sum, qir_FMUL(c,
676 src[0 * 4 + j],
677 src[1 * 4 + j]));
678 }
679 return sum;
680 }
681
682 static struct qreg
683 tgsi_to_qir_dp2(struct vc4_compile *c,
684 struct tgsi_full_instruction *tgsi_inst,
685 enum qop op, struct qreg *src, int i)
686 {
687 return tgsi_to_qir_dp(c, tgsi_inst, 2, src, i);
688 }
689
690 static struct qreg
691 tgsi_to_qir_dp3(struct vc4_compile *c,
692 struct tgsi_full_instruction *tgsi_inst,
693 enum qop op, struct qreg *src, int i)
694 {
695 return tgsi_to_qir_dp(c, tgsi_inst, 3, src, i);
696 }
697
698 static struct qreg
699 tgsi_to_qir_dp4(struct vc4_compile *c,
700 struct tgsi_full_instruction *tgsi_inst,
701 enum qop op, struct qreg *src, int i)
702 {
703 return tgsi_to_qir_dp(c, tgsi_inst, 4, src, i);
704 }
705
706 static struct qreg
707 tgsi_to_qir_abs(struct vc4_compile *c,
708 struct tgsi_full_instruction *tgsi_inst,
709 enum qop op, struct qreg *src, int i)
710 {
711 struct qreg arg = src[0 * 4 + i];
712 return qir_FMAXABS(c, arg, arg);
713 }
714
715 /* Note that this instruction replicates its result from the x channel */
716 static struct qreg
717 tgsi_to_qir_sin(struct vc4_compile *c,
718 struct tgsi_full_instruction *tgsi_inst,
719 enum qop op, struct qreg *src, int i)
720 {
721 float coeff[] = {
722 2.0 * M_PI,
723 -pow(2.0 * M_PI, 3) / (3 * 2 * 1),
724 pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
725 -pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
726 };
727
728 struct qreg scaled_x =
729 qir_FMUL(c,
730 src[0 * 4 + 0],
731 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
732
733
734 struct qreg x = tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0);
735 struct qreg x2 = qir_FMUL(c, x, x);
736 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
737 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
738 x = qir_FMUL(c, x, x2);
739 sum = qir_FADD(c,
740 sum,
741 qir_FMUL(c,
742 x,
743 qir_uniform_f(c, coeff[i])));
744 }
745 return sum;
746 }
747
748 /* Note that this instruction replicates its result from the x channel */
749 static struct qreg
750 tgsi_to_qir_cos(struct vc4_compile *c,
751 struct tgsi_full_instruction *tgsi_inst,
752 enum qop op, struct qreg *src, int i)
753 {
754 float coeff[] = {
755 1.0f,
756 -pow(2.0 * M_PI, 2) / (2 * 1),
757 pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
758 -pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
759 };
760
761 struct qreg scaled_x =
762 qir_FMUL(c, src[0 * 4 + 0],
763 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
764 struct qreg x_frac = tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0);
765
766 struct qreg sum = qir_uniform_f(c, coeff[0]);
767 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
768 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
769 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
770 if (i != 1)
771 x = qir_FMUL(c, x, x2);
772
773 struct qreg mul = qir_FMUL(c,
774 x,
775 qir_uniform_f(c, coeff[i]));
776 if (i == 0)
777 sum = mul;
778 else
779 sum = qir_FADD(c, sum, mul);
780 }
781 return sum;
782 }
783
784 static void
785 emit_vertex_input(struct vc4_compile *c, int attr)
786 {
787 enum pipe_format format = c->vs_key->attr_formats[attr];
788 struct qreg vpm_reads[4];
789
790 /* Right now, we're setting the VPM offsets to be 16 bytes wide every
791 * time, so we always read 4 32-bit VPM entries.
792 */
793 for (int i = 0; i < 4; i++) {
794 vpm_reads[i] = qir_get_temp(c);
795 qir_emit(c, qir_inst(QOP_VPM_READ,
796 vpm_reads[i],
797 c->undef,
798 c->undef));
799 c->num_inputs++;
800 }
801
802 bool format_warned = false;
803 const struct util_format_description *desc =
804 util_format_description(format);
805
806 for (int i = 0; i < 4; i++) {
807 uint8_t swiz = desc->swizzle[i];
808
809 if (swiz <= UTIL_FORMAT_SWIZZLE_W &&
810 !format_warned &&
811 (desc->channel[swiz].type != UTIL_FORMAT_TYPE_FLOAT ||
812 desc->channel[swiz].size != 32)) {
813 fprintf(stderr,
814 "vtx element %d unsupported type: %s\n",
815 attr, util_format_name(format));
816 format_warned = true;
817 }
818
819 c->inputs[attr * 4 + i] =
820 get_swizzled_channel(c, vpm_reads, swiz);
821 }
822 }
823
824 static void
825 tgsi_to_qir_kill_if(struct vc4_compile *c, struct qreg *src, int i)
826 {
827 if (c->discard.file == QFILE_NULL)
828 c->discard = qir_uniform_f(c, 0.0);
829 qir_SF(c, src[0 * 4 + i]);
830 c->discard = qir_SEL_X_Y_NS(c, qir_uniform_f(c, 1.0),
831 c->discard);
832 }
833
834 static void
835 emit_fragcoord_input(struct vc4_compile *c, int attr)
836 {
837 c->inputs[attr * 4 + 0] = qir_FRAG_X(c);
838 c->inputs[attr * 4 + 1] = qir_FRAG_Y(c);
839 c->inputs[attr * 4 + 2] =
840 qir_FMUL(c,
841 qir_ITOF(c, qir_FRAG_Z(c)),
842 qir_uniform_f(c, 1.0 / 0xffffff));
843 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
844 }
845
846 static struct qreg
847 emit_fragment_varying(struct vc4_compile *c, int index)
848 {
849 struct qreg vary = {
850 QFILE_VARY,
851 index
852 };
853
854 /* XXX: multiply by W */
855 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
856 }
857
858 static void
859 emit_fragment_input(struct vc4_compile *c, int attr)
860 {
861 for (int i = 0; i < 4; i++) {
862 c->inputs[attr * 4 + i] =
863 emit_fragment_varying(c, attr * 4 + i);
864 c->num_inputs++;
865 }
866 }
867
868 static void
869 emit_tgsi_declaration(struct vc4_compile *c,
870 struct tgsi_full_declaration *decl)
871 {
872 switch (decl->Declaration.File) {
873 case TGSI_FILE_TEMPORARY:
874 resize_qreg_array(c, &c->temps, &c->temps_array_size,
875 (decl->Range.Last + 1) * 4);
876 break;
877
878 case TGSI_FILE_INPUT:
879 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
880 (decl->Range.Last + 1) * 4);
881
882 for (int i = decl->Range.First;
883 i <= decl->Range.Last;
884 i++) {
885 if (c->stage == QSTAGE_FRAG) {
886 if (decl->Semantic.Name ==
887 TGSI_SEMANTIC_POSITION) {
888 emit_fragcoord_input(c, i);
889 } else {
890 emit_fragment_input(c, i);
891 }
892 } else {
893 emit_vertex_input(c, i);
894 }
895 }
896 break;
897
898 case TGSI_FILE_OUTPUT:
899 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
900 (decl->Range.Last + 1) * 4);
901
902 switch (decl->Semantic.Name) {
903 case TGSI_SEMANTIC_POSITION:
904 c->output_position_index = decl->Range.First * 4;
905 break;
906 case TGSI_SEMANTIC_COLOR:
907 c->output_color_index = decl->Range.First * 4;
908 break;
909 }
910
911 break;
912 }
913 }
914
915 static void
916 emit_tgsi_instruction(struct vc4_compile *c,
917 struct tgsi_full_instruction *tgsi_inst)
918 {
919 struct {
920 enum qop op;
921 struct qreg (*func)(struct vc4_compile *c,
922 struct tgsi_full_instruction *tgsi_inst,
923 enum qop op,
924 struct qreg *src, int i);
925 } op_trans[] = {
926 [TGSI_OPCODE_MOV] = { QOP_MOV, tgsi_to_qir_alu },
927 [TGSI_OPCODE_ABS] = { 0, tgsi_to_qir_abs },
928 [TGSI_OPCODE_MUL] = { QOP_FMUL, tgsi_to_qir_alu },
929 [TGSI_OPCODE_ADD] = { QOP_FADD, tgsi_to_qir_alu },
930 [TGSI_OPCODE_SUB] = { QOP_FSUB, tgsi_to_qir_alu },
931 [TGSI_OPCODE_MIN] = { QOP_FMIN, tgsi_to_qir_alu },
932 [TGSI_OPCODE_MAX] = { QOP_FMAX, tgsi_to_qir_alu },
933 [TGSI_OPCODE_F2I] = { QOP_FTOI, tgsi_to_qir_alu },
934 [TGSI_OPCODE_I2F] = { QOP_ITOF, tgsi_to_qir_alu },
935 [TGSI_OPCODE_UADD] = { QOP_ADD, tgsi_to_qir_alu },
936 [TGSI_OPCODE_USHR] = { QOP_SHR, tgsi_to_qir_alu },
937 [TGSI_OPCODE_ISHR] = { QOP_ASR, tgsi_to_qir_alu },
938 [TGSI_OPCODE_SHL] = { QOP_SHL, tgsi_to_qir_alu },
939 [TGSI_OPCODE_IMIN] = { QOP_MIN, tgsi_to_qir_alu },
940 [TGSI_OPCODE_IMAX] = { QOP_MAX, tgsi_to_qir_alu },
941 [TGSI_OPCODE_AND] = { QOP_AND, tgsi_to_qir_alu },
942 [TGSI_OPCODE_OR] = { QOP_OR, tgsi_to_qir_alu },
943 [TGSI_OPCODE_XOR] = { QOP_XOR, tgsi_to_qir_alu },
944 [TGSI_OPCODE_NOT] = { QOP_NOT, tgsi_to_qir_alu },
945
946 [TGSI_OPCODE_UMUL] = { 0, tgsi_to_qir_umul },
947 [TGSI_OPCODE_IDIV] = { 0, tgsi_to_qir_idiv },
948 [TGSI_OPCODE_INEG] = { 0, tgsi_to_qir_ineg },
949
950 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_alu },
951 [TGSI_OPCODE_SEQ] = { 0, tgsi_to_qir_seq },
952 [TGSI_OPCODE_SNE] = { 0, tgsi_to_qir_sne },
953 [TGSI_OPCODE_SGE] = { 0, tgsi_to_qir_sge },
954 [TGSI_OPCODE_SLT] = { 0, tgsi_to_qir_slt },
955 [TGSI_OPCODE_FSEQ] = { 0, tgsi_to_qir_fseq },
956 [TGSI_OPCODE_FSNE] = { 0, tgsi_to_qir_fsne },
957 [TGSI_OPCODE_FSGE] = { 0, tgsi_to_qir_fsge },
958 [TGSI_OPCODE_FSLT] = { 0, tgsi_to_qir_fslt },
959 [TGSI_OPCODE_USEQ] = { 0, tgsi_to_qir_useq },
960 [TGSI_OPCODE_USNE] = { 0, tgsi_to_qir_usne },
961 [TGSI_OPCODE_ISGE] = { 0, tgsi_to_qir_isge },
962 [TGSI_OPCODE_ISLT] = { 0, tgsi_to_qir_islt },
963
964 [TGSI_OPCODE_CMP] = { 0, tgsi_to_qir_cmp },
965 [TGSI_OPCODE_MAD] = { 0, tgsi_to_qir_mad },
966 [TGSI_OPCODE_DP2] = { 0, tgsi_to_qir_dp2 },
967 [TGSI_OPCODE_DP3] = { 0, tgsi_to_qir_dp3 },
968 [TGSI_OPCODE_DP4] = { 0, tgsi_to_qir_dp4 },
969 [TGSI_OPCODE_RCP] = { QOP_RCP, tgsi_to_qir_alu },
970 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_alu },
971 [TGSI_OPCODE_EX2] = { QOP_EXP2, tgsi_to_qir_alu },
972 [TGSI_OPCODE_LG2] = { QOP_LOG2, tgsi_to_qir_alu },
973 [TGSI_OPCODE_LIT] = { 0, tgsi_to_qir_lit },
974 [TGSI_OPCODE_LRP] = { 0, tgsi_to_qir_lrp },
975 [TGSI_OPCODE_POW] = { 0, tgsi_to_qir_pow },
976 [TGSI_OPCODE_TRUNC] = { 0, tgsi_to_qir_trunc },
977 [TGSI_OPCODE_FRC] = { 0, tgsi_to_qir_frc },
978 [TGSI_OPCODE_FLR] = { 0, tgsi_to_qir_flr },
979 [TGSI_OPCODE_SIN] = { 0, tgsi_to_qir_sin },
980 [TGSI_OPCODE_COS] = { 0, tgsi_to_qir_cos },
981 };
982 static int asdf = 0;
983 uint32_t tgsi_op = tgsi_inst->Instruction.Opcode;
984
985 if (tgsi_op == TGSI_OPCODE_END)
986 return;
987
988 struct qreg src_regs[12];
989 for (int s = 0; s < 3; s++) {
990 for (int i = 0; i < 4; i++) {
991 src_regs[4 * s + i] =
992 get_src(c, tgsi_inst->Instruction.Opcode,
993 &tgsi_inst->Src[s].Register, i);
994 }
995 }
996
997 switch (tgsi_op) {
998 case TGSI_OPCODE_TEX:
999 case TGSI_OPCODE_TXP:
1000 case TGSI_OPCODE_TXB:
1001 tgsi_to_qir_tex(c, tgsi_inst,
1002 op_trans[tgsi_op].op, src_regs);
1003 return;
1004 case TGSI_OPCODE_KILL:
1005 c->discard = qir_uniform_f(c, 1.0);
1006 return;
1007 case TGSI_OPCODE_KILL_IF:
1008 for (int i = 0; i < 4; i++)
1009 tgsi_to_qir_kill_if(c, src_regs, i);
1010 return;
1011 default:
1012 break;
1013 }
1014
1015 if (tgsi_op > ARRAY_SIZE(op_trans) || !(op_trans[tgsi_op].func)) {
1016 fprintf(stderr, "unknown tgsi inst: ");
1017 tgsi_dump_instruction(tgsi_inst, asdf++);
1018 fprintf(stderr, "\n");
1019 abort();
1020 }
1021
1022 for (int i = 0; i < 4; i++) {
1023 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
1024 continue;
1025
1026 struct qreg result;
1027
1028 result = op_trans[tgsi_op].func(c, tgsi_inst,
1029 op_trans[tgsi_op].op,
1030 src_regs, i);
1031
1032 if (tgsi_inst->Instruction.Saturate) {
1033 float low = (tgsi_inst->Instruction.Saturate ==
1034 TGSI_SAT_MINUS_PLUS_ONE ? -1.0 : 0.0);
1035 result = qir_FMAX(c,
1036 qir_FMIN(c,
1037 result,
1038 qir_uniform_f(c, 1.0)),
1039 qir_uniform_f(c, low));
1040 }
1041
1042 update_dst(c, tgsi_inst, i, result);
1043 }
1044 }
1045
1046 static void
1047 parse_tgsi_immediate(struct vc4_compile *c, struct tgsi_full_immediate *imm)
1048 {
1049 for (int i = 0; i < 4; i++) {
1050 unsigned n = c->num_consts++;
1051 resize_qreg_array(c, &c->consts, &c->consts_array_size, n + 1);
1052 c->consts[n] = qir_uniform_ui(c, imm->u[i].Uint);
1053 }
1054 }
1055
1056 static struct qreg
1057 vc4_blend_channel(struct vc4_compile *c,
1058 struct qreg *dst,
1059 struct qreg *src,
1060 struct qreg val,
1061 unsigned factor,
1062 int channel)
1063 {
1064 switch(factor) {
1065 case PIPE_BLENDFACTOR_ONE:
1066 return val;
1067 case PIPE_BLENDFACTOR_SRC_COLOR:
1068 return qir_FMUL(c, val, src[channel]);
1069 case PIPE_BLENDFACTOR_SRC_ALPHA:
1070 return qir_FMUL(c, val, src[3]);
1071 case PIPE_BLENDFACTOR_DST_ALPHA:
1072 return qir_FMUL(c, val, dst[3]);
1073 case PIPE_BLENDFACTOR_DST_COLOR:
1074 return qir_FMUL(c, val, dst[channel]);
1075 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
1076 return qir_FMIN(c, src[3], qir_FSUB(c,
1077 qir_uniform_f(c, 1.0),
1078 dst[3]));
1079 case PIPE_BLENDFACTOR_CONST_COLOR:
1080 return qir_FMUL(c, val,
1081 get_temp_for_uniform(c,
1082 QUNIFORM_BLEND_CONST_COLOR,
1083 channel));
1084 case PIPE_BLENDFACTOR_CONST_ALPHA:
1085 return qir_FMUL(c, val,
1086 get_temp_for_uniform(c,
1087 QUNIFORM_BLEND_CONST_COLOR,
1088 3));
1089 case PIPE_BLENDFACTOR_ZERO:
1090 return qir_uniform_f(c, 0.0);
1091 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
1092 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1093 src[channel]));
1094 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
1095 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1096 src[3]));
1097 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
1098 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1099 dst[3]));
1100 case PIPE_BLENDFACTOR_INV_DST_COLOR:
1101 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1102 dst[channel]));
1103 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
1104 return qir_FMUL(c, val,
1105 qir_FSUB(c, qir_uniform_f(c, 1.0),
1106 get_temp_for_uniform(c,
1107 QUNIFORM_BLEND_CONST_COLOR,
1108 channel)));
1109 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
1110 return qir_FMUL(c, val,
1111 qir_FSUB(c, qir_uniform_f(c, 1.0),
1112 get_temp_for_uniform(c,
1113 QUNIFORM_BLEND_CONST_COLOR,
1114 3)));
1115
1116 default:
1117 case PIPE_BLENDFACTOR_SRC1_COLOR:
1118 case PIPE_BLENDFACTOR_SRC1_ALPHA:
1119 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
1120 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
1121 /* Unsupported. */
1122 fprintf(stderr, "Unknown blend factor %d\n", factor);
1123 return val;
1124 }
1125 }
1126
1127 static struct qreg
1128 vc4_blend_func(struct vc4_compile *c,
1129 struct qreg src, struct qreg dst,
1130 unsigned func)
1131 {
1132 switch (func) {
1133 case PIPE_BLEND_ADD:
1134 return qir_FADD(c, src, dst);
1135 case PIPE_BLEND_SUBTRACT:
1136 return qir_FSUB(c, src, dst);
1137 case PIPE_BLEND_REVERSE_SUBTRACT:
1138 return qir_FSUB(c, dst, src);
1139 case PIPE_BLEND_MIN:
1140 return qir_FMIN(c, src, dst);
1141 case PIPE_BLEND_MAX:
1142 return qir_FMAX(c, src, dst);
1143
1144 default:
1145 /* Unsupported. */
1146 fprintf(stderr, "Unknown blend func %d\n", func);
1147 return src;
1148
1149 }
1150 }
1151
1152 /**
1153 * Implements fixed function blending in shader code.
1154 *
1155 * VC4 doesn't have any hardware support for blending. Instead, you read the
1156 * current contents of the destination from the tile buffer after having
1157 * waited for the scoreboard (which is handled by vc4_qpu_emit.c), then do
1158 * math using your output color and that destination value, and update the
1159 * output color appropriately.
1160 */
1161 static void
1162 vc4_blend(struct vc4_compile *c, struct qreg *result,
1163 struct qreg *dst_color, struct qreg *src_color)
1164 {
1165 struct pipe_rt_blend_state *blend = &c->fs_key->blend;
1166
1167 if (!blend->blend_enable) {
1168 for (int i = 0; i < 4; i++)
1169 result[i] = src_color[i];
1170 return;
1171 }
1172
1173 struct qreg src_blend[4], dst_blend[4];
1174 for (int i = 0; i < 3; i++) {
1175 src_blend[i] = vc4_blend_channel(c,
1176 dst_color, src_color,
1177 src_color[i],
1178 blend->rgb_src_factor, i);
1179 dst_blend[i] = vc4_blend_channel(c,
1180 dst_color, src_color,
1181 dst_color[i],
1182 blend->rgb_dst_factor, i);
1183 }
1184 src_blend[3] = vc4_blend_channel(c,
1185 dst_color, src_color,
1186 src_color[3],
1187 blend->alpha_src_factor, 3);
1188 dst_blend[3] = vc4_blend_channel(c,
1189 dst_color, src_color,
1190 dst_color[3],
1191 blend->alpha_dst_factor, 3);
1192
1193 for (int i = 0; i < 3; i++) {
1194 result[i] = vc4_blend_func(c,
1195 src_blend[i], dst_blend[i],
1196 blend->rgb_func);
1197 }
1198 result[3] = vc4_blend_func(c,
1199 src_blend[3], dst_blend[3],
1200 blend->alpha_func);
1201 }
1202
1203 static void
1204 emit_frag_end(struct vc4_compile *c)
1205 {
1206 enum pipe_format color_format = c->fs_key->color_format;
1207 const uint8_t *format_swiz = vc4_get_format_swizzle(color_format);
1208 struct qreg tlb_read_color[4] = { c->undef, c->undef, c->undef, c->undef };
1209 struct qreg dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1210 if (c->fs_key->blend.blend_enable ||
1211 c->fs_key->blend.colormask != 0xf) {
1212 struct qreg r4 = qir_TLB_COLOR_READ(c);
1213 for (int i = 0; i < 4; i++)
1214 tlb_read_color[i] = qir_R4_UNPACK(c, r4, i);
1215 for (int i = 0; i < 4; i++)
1216 dst_color[i] = get_swizzled_channel(c,
1217 tlb_read_color,
1218 format_swiz[i]);
1219 }
1220
1221 struct qreg blend_color[4];
1222 struct qreg undef_array[4] = {
1223 c->undef, c->undef, c->undef, c->undef
1224 };
1225 vc4_blend(c, blend_color, dst_color,
1226 (c->output_color_index != -1 ?
1227 c->outputs + c->output_color_index :
1228 undef_array));
1229
1230 /* If the bit isn't set in the color mask, then just return the
1231 * original dst color, instead.
1232 */
1233 for (int i = 0; i < 4; i++) {
1234 if (!(c->fs_key->blend.colormask & (1 << i))) {
1235 blend_color[i] = dst_color[i];
1236 }
1237 }
1238
1239 /* Debug: Sometimes you're getting a black output and just want to see
1240 * if the FS is getting executed at all. Spam magenta into the color
1241 * output.
1242 */
1243 if (0) {
1244 blend_color[0] = qir_uniform_f(c, 1.0);
1245 blend_color[1] = qir_uniform_f(c, 0.0);
1246 blend_color[2] = qir_uniform_f(c, 1.0);
1247 blend_color[3] = qir_uniform_f(c, 0.5);
1248 }
1249
1250 struct qreg swizzled_outputs[4];
1251 for (int i = 0; i < 4; i++) {
1252 swizzled_outputs[i] = get_swizzled_channel(c, blend_color,
1253 format_swiz[i]);
1254 }
1255
1256 if (c->discard.file != QFILE_NULL)
1257 qir_TLB_DISCARD_SETUP(c, c->discard);
1258
1259 if (c->fs_key->stencil_enabled) {
1260 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 0));
1261 if (c->fs_key->stencil_twoside) {
1262 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 1));
1263 }
1264 if (c->fs_key->stencil_full_writemasks) {
1265 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 2));
1266 }
1267 }
1268
1269 if (c->fs_key->depth_enabled) {
1270 struct qreg z;
1271 if (c->output_position_index != -1) {
1272 z = qir_FTOI(c, qir_FMUL(c, c->outputs[c->output_position_index + 2],
1273 qir_uniform_f(c, 0xffffff)));
1274 } else {
1275 z = qir_FRAG_Z(c);
1276 }
1277 qir_TLB_Z_WRITE(c, z);
1278 }
1279
1280 bool color_written = false;
1281 for (int i = 0; i < 4; i++) {
1282 if (swizzled_outputs[i].file != QFILE_NULL)
1283 color_written = true;
1284 }
1285
1286 struct qreg packed_color;
1287 if (color_written) {
1288 /* Fill in any undefined colors. The simulator will assertion
1289 * fail if we read something that wasn't written, and I don't
1290 * know what hardware does.
1291 */
1292 for (int i = 0; i < 4; i++) {
1293 if (swizzled_outputs[i].file == QFILE_NULL)
1294 swizzled_outputs[i] = qir_uniform_f(c, 0.0);
1295 }
1296 packed_color = qir_get_temp(c);
1297 qir_emit(c, qir_inst4(QOP_PACK_COLORS, packed_color,
1298 swizzled_outputs[0],
1299 swizzled_outputs[1],
1300 swizzled_outputs[2],
1301 swizzled_outputs[3]));
1302 } else {
1303 packed_color = qir_uniform_ui(c, 0);
1304 }
1305
1306 qir_emit(c, qir_inst(QOP_TLB_COLOR_WRITE, c->undef,
1307 packed_color, c->undef));
1308 }
1309
1310 static void
1311 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1312 {
1313 struct qreg xyi[2];
1314
1315 for (int i = 0; i < 2; i++) {
1316 struct qreg scale =
1317 add_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1318
1319 xyi[i] = qir_FTOI(c, qir_FMUL(c,
1320 qir_FMUL(c,
1321 c->outputs[i],
1322 scale),
1323 rcp_w));
1324 }
1325
1326 qir_VPM_WRITE(c, qir_PACK_SCALED(c, xyi[0], xyi[1]));
1327 }
1328
1329 static void
1330 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1331 {
1332 struct qreg zscale = add_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1333 struct qreg zoffset = add_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1334
1335 qir_VPM_WRITE(c, qir_FMUL(c, qir_FADD(c, qir_FMUL(c,
1336 c->outputs[2],
1337 zscale),
1338 zoffset),
1339 rcp_w));
1340 }
1341
1342 static void
1343 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1344 {
1345 qir_VPM_WRITE(c, rcp_w);
1346 }
1347
1348 static void
1349 emit_vert_end(struct vc4_compile *c)
1350 {
1351 struct qreg rcp_w = qir_RCP(c, c->outputs[3]);
1352
1353 emit_scaled_viewport_write(c, rcp_w);
1354 emit_zs_write(c, rcp_w);
1355 emit_rcp_wc_write(c, rcp_w);
1356
1357 for (int i = 4; i < c->num_outputs; i++) {
1358 qir_VPM_WRITE(c, c->outputs[i]);
1359 }
1360 }
1361
1362 static void
1363 emit_coord_end(struct vc4_compile *c)
1364 {
1365 struct qreg rcp_w = qir_RCP(c, c->outputs[3]);
1366
1367 for (int i = 0; i < 4; i++)
1368 qir_VPM_WRITE(c, c->outputs[i]);
1369
1370 emit_scaled_viewport_write(c, rcp_w);
1371 emit_zs_write(c, rcp_w);
1372 emit_rcp_wc_write(c, rcp_w);
1373 }
1374
1375 static struct vc4_compile *
1376 vc4_shader_tgsi_to_qir(struct vc4_context *vc4,
1377 struct vc4_compiled_shader *shader, enum qstage stage,
1378 struct vc4_key *key)
1379 {
1380 struct vc4_compile *c = qir_compile_init();
1381 int ret;
1382
1383 c->stage = stage;
1384
1385 c->uniform_data = ralloc_array(c, uint32_t, 1024);
1386 c->uniform_contents = ralloc_array(c, enum quniform_contents, 1024);
1387
1388 c->shader_state = key->shader_state;
1389 ret = tgsi_parse_init(&c->parser, c->shader_state->tokens);
1390 assert(ret == TGSI_PARSE_OK);
1391
1392 if (vc4_debug & VC4_DEBUG_TGSI) {
1393 fprintf(stderr, "TGSI:\n");
1394 tgsi_dump(c->shader_state->tokens, 0);
1395 }
1396
1397 c->key = key;
1398 switch (stage) {
1399 case QSTAGE_FRAG:
1400 c->fs_key = (struct vc4_fs_key *)key;
1401 if (c->fs_key->is_points) {
1402 c->point_x = emit_fragment_varying(c, 0);
1403 c->point_y = emit_fragment_varying(c, 0);
1404 } else if (c->fs_key->is_lines) {
1405 c->line_x = emit_fragment_varying(c, 0);
1406 }
1407 break;
1408 case QSTAGE_VERT:
1409 c->vs_key = (struct vc4_vs_key *)key;
1410 break;
1411 case QSTAGE_COORD:
1412 c->vs_key = (struct vc4_vs_key *)key;
1413 break;
1414 }
1415
1416 while (!tgsi_parse_end_of_tokens(&c->parser)) {
1417 tgsi_parse_token(&c->parser);
1418
1419 switch (c->parser.FullToken.Token.Type) {
1420 case TGSI_TOKEN_TYPE_DECLARATION:
1421 emit_tgsi_declaration(c,
1422 &c->parser.FullToken.FullDeclaration);
1423 break;
1424
1425 case TGSI_TOKEN_TYPE_INSTRUCTION:
1426 emit_tgsi_instruction(c,
1427 &c->parser.FullToken.FullInstruction);
1428 break;
1429
1430 case TGSI_TOKEN_TYPE_IMMEDIATE:
1431 parse_tgsi_immediate(c,
1432 &c->parser.FullToken.FullImmediate);
1433 break;
1434 }
1435 }
1436
1437 switch (stage) {
1438 case QSTAGE_FRAG:
1439 emit_frag_end(c);
1440 break;
1441 case QSTAGE_VERT:
1442 emit_vert_end(c);
1443 break;
1444 case QSTAGE_COORD:
1445 emit_coord_end(c);
1446 break;
1447 }
1448
1449 tgsi_parse_free(&c->parser);
1450
1451 qir_optimize(c);
1452
1453 if (vc4_debug & VC4_DEBUG_QIR) {
1454 fprintf(stderr, "QIR:\n");
1455 qir_dump(c);
1456 }
1457 qir_reorder_uniforms(c);
1458 vc4_generate_code(vc4, c);
1459
1460 if (vc4_debug & VC4_DEBUG_SHADERDB) {
1461 fprintf(stderr, "SHADER-DB: %s: %d instructions\n",
1462 qir_get_stage_name(c->stage), c->qpu_inst_count);
1463 fprintf(stderr, "SHADER-DB: %s: %d uniforms\n",
1464 qir_get_stage_name(c->stage), c->num_uniforms);
1465 }
1466
1467 return c;
1468 }
1469
1470 static void *
1471 vc4_shader_state_create(struct pipe_context *pctx,
1472 const struct pipe_shader_state *cso)
1473 {
1474 struct pipe_shader_state *so = CALLOC_STRUCT(pipe_shader_state);
1475 if (!so)
1476 return NULL;
1477
1478 so->tokens = tgsi_dup_tokens(cso->tokens);
1479
1480 return so;
1481 }
1482
1483 static void
1484 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
1485 int shader_index,
1486 struct vc4_compile *c)
1487 {
1488 int count = c->num_uniforms;
1489 struct vc4_shader_uniform_info *uinfo = &shader->uniforms[shader_index];
1490
1491 uinfo->count = count;
1492 uinfo->data = malloc(count * sizeof(*uinfo->data));
1493 memcpy(uinfo->data, c->uniform_data,
1494 count * sizeof(*uinfo->data));
1495 uinfo->contents = malloc(count * sizeof(*uinfo->contents));
1496 memcpy(uinfo->contents, c->uniform_contents,
1497 count * sizeof(*uinfo->contents));
1498 uinfo->num_texture_samples = c->num_texture_samples;
1499 }
1500
1501 static void
1502 vc4_fs_compile(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1503 struct vc4_fs_key *key)
1504 {
1505 struct vc4_compile *c = vc4_shader_tgsi_to_qir(vc4, shader,
1506 QSTAGE_FRAG,
1507 &key->base);
1508 shader->num_inputs = c->num_inputs;
1509 copy_uniform_state_to_shader(shader, 0, c);
1510 shader->bo = vc4_bo_alloc_mem(vc4->screen, c->qpu_insts,
1511 c->qpu_inst_count * sizeof(uint64_t),
1512 "fs_code");
1513
1514 qir_compile_destroy(c);
1515 }
1516
1517 static void
1518 vc4_vs_compile(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1519 struct vc4_vs_key *key)
1520 {
1521 struct vc4_compile *vs_c = vc4_shader_tgsi_to_qir(vc4, shader,
1522 QSTAGE_VERT,
1523 &key->base);
1524 copy_uniform_state_to_shader(shader, 0, vs_c);
1525
1526 struct vc4_compile *cs_c = vc4_shader_tgsi_to_qir(vc4, shader,
1527 QSTAGE_COORD,
1528 &key->base);
1529 copy_uniform_state_to_shader(shader, 1, cs_c);
1530
1531 uint32_t vs_size = vs_c->qpu_inst_count * sizeof(uint64_t);
1532 uint32_t cs_size = cs_c->qpu_inst_count * sizeof(uint64_t);
1533 shader->coord_shader_offset = vs_size; /* XXX: alignment? */
1534 shader->bo = vc4_bo_alloc(vc4->screen,
1535 shader->coord_shader_offset + cs_size,
1536 "vs_code");
1537
1538 void *map = vc4_bo_map(shader->bo);
1539 memcpy(map, vs_c->qpu_insts, vs_size);
1540 memcpy(map + shader->coord_shader_offset,
1541 cs_c->qpu_insts, cs_size);
1542
1543 qir_compile_destroy(vs_c);
1544 qir_compile_destroy(cs_c);
1545 }
1546
1547 static void
1548 vc4_setup_shared_key(struct vc4_key *key, struct vc4_texture_stateobj *texstate)
1549 {
1550 for (int i = 0; i < texstate->num_textures; i++) {
1551 struct pipe_sampler_view *sampler = texstate->textures[i];
1552 struct pipe_sampler_state *sampler_state =
1553 texstate->samplers[i];
1554
1555 if (sampler) {
1556 struct pipe_resource *prsc = sampler->texture;
1557 key->tex[i].format = prsc->format;
1558 key->tex[i].swizzle[0] = sampler->swizzle_r;
1559 key->tex[i].swizzle[1] = sampler->swizzle_g;
1560 key->tex[i].swizzle[2] = sampler->swizzle_b;
1561 key->tex[i].swizzle[3] = sampler->swizzle_a;
1562 key->tex[i].compare_mode = sampler_state->compare_mode;
1563 key->tex[i].compare_func = sampler_state->compare_func;
1564 }
1565 }
1566 }
1567
1568 static void
1569 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
1570 {
1571 struct vc4_fs_key local_key;
1572 struct vc4_fs_key *key = &local_key;
1573
1574 memset(key, 0, sizeof(*key));
1575 vc4_setup_shared_key(&key->base, &vc4->fragtex);
1576 key->base.shader_state = vc4->prog.bind_fs;
1577 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
1578 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
1579 prim_mode <= PIPE_PRIM_LINE_STRIP);
1580 key->blend = vc4->blend->rt[0];
1581
1582 if (vc4->framebuffer.cbufs[0])
1583 key->color_format = vc4->framebuffer.cbufs[0]->format;
1584
1585 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
1586 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
1587 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
1588 key->depth_enabled = (vc4->zsa->base.depth.enabled ||
1589 key->stencil_enabled);
1590
1591 vc4->prog.fs = util_hash_table_get(vc4->fs_cache, key);
1592 if (vc4->prog.fs)
1593 return;
1594
1595 key = malloc(sizeof(*key));
1596 memcpy(key, &local_key, sizeof(*key));
1597
1598 struct vc4_compiled_shader *shader = CALLOC_STRUCT(vc4_compiled_shader);
1599 vc4_fs_compile(vc4, shader, key);
1600 util_hash_table_set(vc4->fs_cache, key, shader);
1601
1602 vc4->prog.fs = shader;
1603 }
1604
1605 static void
1606 vc4_update_compiled_vs(struct vc4_context *vc4)
1607 {
1608 struct vc4_vs_key local_key;
1609 struct vc4_vs_key *key = &local_key;
1610
1611 memset(key, 0, sizeof(*key));
1612 vc4_setup_shared_key(&key->base, &vc4->verttex);
1613 key->base.shader_state = vc4->prog.bind_vs;
1614
1615 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
1616 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
1617
1618 vc4->prog.vs = util_hash_table_get(vc4->vs_cache, key);
1619 if (vc4->prog.vs)
1620 return;
1621
1622 key = malloc(sizeof(*key));
1623 memcpy(key, &local_key, sizeof(*key));
1624
1625 struct vc4_compiled_shader *shader = CALLOC_STRUCT(vc4_compiled_shader);
1626 vc4_vs_compile(vc4, shader, key);
1627 util_hash_table_set(vc4->vs_cache, key, shader);
1628
1629 vc4->prog.vs = shader;
1630 }
1631
1632 void
1633 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
1634 {
1635 vc4_update_compiled_fs(vc4, prim_mode);
1636 vc4_update_compiled_vs(vc4);
1637 }
1638
1639 static unsigned
1640 fs_cache_hash(void *key)
1641 {
1642 return util_hash_crc32(key, sizeof(struct vc4_fs_key));
1643 }
1644
1645 static unsigned
1646 vs_cache_hash(void *key)
1647 {
1648 return util_hash_crc32(key, sizeof(struct vc4_vs_key));
1649 }
1650
1651 static int
1652 fs_cache_compare(void *key1, void *key2)
1653 {
1654 return memcmp(key1, key2, sizeof(struct vc4_fs_key));
1655 }
1656
1657 static int
1658 vs_cache_compare(void *key1, void *key2)
1659 {
1660 return memcmp(key1, key2, sizeof(struct vc4_vs_key));
1661 }
1662
1663 struct delete_state {
1664 struct vc4_context *vc4;
1665 struct pipe_shader_state *shader_state;
1666 };
1667
1668 static enum pipe_error
1669 fs_delete_from_cache(void *in_key, void *in_value, void *data)
1670 {
1671 struct delete_state *del = data;
1672 struct vc4_fs_key *key = in_key;
1673 struct vc4_compiled_shader *shader = in_value;
1674
1675 if (key->base.shader_state == data) {
1676 util_hash_table_remove(del->vc4->fs_cache, key);
1677 vc4_bo_unreference(&shader->bo);
1678 free(shader);
1679 }
1680
1681 return 0;
1682 }
1683
1684 static enum pipe_error
1685 vs_delete_from_cache(void *in_key, void *in_value, void *data)
1686 {
1687 struct delete_state *del = data;
1688 struct vc4_vs_key *key = in_key;
1689 struct vc4_compiled_shader *shader = in_value;
1690
1691 if (key->base.shader_state == data) {
1692 util_hash_table_remove(del->vc4->vs_cache, key);
1693 vc4_bo_unreference(&shader->bo);
1694 free(shader);
1695 }
1696
1697 return 0;
1698 }
1699
1700 static void
1701 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
1702 {
1703 struct vc4_context *vc4 = vc4_context(pctx);
1704 struct pipe_shader_state *so = hwcso;
1705 struct delete_state del;
1706
1707 del.vc4 = vc4;
1708 del.shader_state = so;
1709 util_hash_table_foreach(vc4->fs_cache, fs_delete_from_cache, &del);
1710 util_hash_table_foreach(vc4->vs_cache, vs_delete_from_cache, &del);
1711
1712 free((void *)so->tokens);
1713 free(so);
1714 }
1715
1716 static uint32_t translate_wrap(uint32_t p_wrap)
1717 {
1718 switch (p_wrap) {
1719 case PIPE_TEX_WRAP_REPEAT:
1720 return 0;
1721 case PIPE_TEX_WRAP_CLAMP:
1722 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1723 return 1;
1724 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1725 return 2;
1726 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1727 return 3;
1728 default:
1729 fprintf(stderr, "Unknown wrap mode %d\n", p_wrap);
1730 assert(!"not reached");
1731 return 0;
1732 }
1733 }
1734
1735 static void
1736 write_texture_p0(struct vc4_context *vc4,
1737 struct vc4_texture_stateobj *texstate,
1738 uint32_t unit)
1739 {
1740 struct pipe_sampler_view *texture = texstate->textures[unit];
1741 struct vc4_resource *rsc = vc4_resource(texture->texture);
1742
1743 cl_reloc(vc4, &vc4->uniforms, rsc->bo,
1744 rsc->slices[0].offset | texture->u.tex.last_level |
1745 ((rsc->vc4_format & 7) << 4));
1746 }
1747
1748 static void
1749 write_texture_p1(struct vc4_context *vc4,
1750 struct vc4_texture_stateobj *texstate,
1751 uint32_t unit)
1752 {
1753 struct pipe_sampler_view *texture = texstate->textures[unit];
1754 struct vc4_resource *rsc = vc4_resource(texture->texture);
1755 struct pipe_sampler_state *sampler = texstate->samplers[unit];
1756 static const uint32_t mipfilter_map[] = {
1757 [PIPE_TEX_MIPFILTER_NEAREST] = 2,
1758 [PIPE_TEX_MIPFILTER_LINEAR] = 4,
1759 [PIPE_TEX_MIPFILTER_NONE] = 0
1760 };
1761 static const uint32_t imgfilter_map[] = {
1762 [PIPE_TEX_FILTER_NEAREST] = 1,
1763 [PIPE_TEX_FILTER_LINEAR] = 0,
1764 };
1765
1766 cl_u32(&vc4->uniforms,
1767 ((rsc->vc4_format >> 4) << 31) |
1768 (texture->texture->height0 << 20) |
1769 (texture->texture->width0 << 8) |
1770 (imgfilter_map[sampler->mag_img_filter] << 7) |
1771 ((imgfilter_map[sampler->min_img_filter] +
1772 mipfilter_map[sampler->min_mip_filter]) << 4) |
1773 (translate_wrap(sampler->wrap_t) << 2) |
1774 (translate_wrap(sampler->wrap_s) << 0));
1775 }
1776
1777 static uint32_t
1778 get_texrect_scale(struct vc4_texture_stateobj *texstate,
1779 enum quniform_contents contents,
1780 uint32_t data)
1781 {
1782 struct pipe_sampler_view *texture = texstate->textures[data];
1783 uint32_t dim;
1784
1785 if (contents == QUNIFORM_TEXRECT_SCALE_X)
1786 dim = texture->texture->width0;
1787 else
1788 dim = texture->texture->height0;
1789
1790 return fui(1.0f / dim);
1791 }
1792
1793 void
1794 vc4_write_uniforms(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1795 struct vc4_constbuf_stateobj *cb,
1796 struct vc4_texture_stateobj *texstate,
1797 int shader_index)
1798 {
1799 struct vc4_shader_uniform_info *uinfo = &shader->uniforms[shader_index];
1800 const uint32_t *gallium_uniforms = cb->cb[0].user_buffer;
1801
1802 cl_start_shader_reloc(&vc4->uniforms, uinfo->num_texture_samples);
1803
1804 for (int i = 0; i < uinfo->count; i++) {
1805
1806 switch (uinfo->contents[i]) {
1807 case QUNIFORM_CONSTANT:
1808 cl_u32(&vc4->uniforms, uinfo->data[i]);
1809 break;
1810 case QUNIFORM_UNIFORM:
1811 cl_u32(&vc4->uniforms,
1812 gallium_uniforms[uinfo->data[i]]);
1813 break;
1814 case QUNIFORM_VIEWPORT_X_SCALE:
1815 cl_f(&vc4->uniforms, vc4->viewport.scale[0] * 16.0f);
1816 break;
1817 case QUNIFORM_VIEWPORT_Y_SCALE:
1818 cl_f(&vc4->uniforms, vc4->viewport.scale[1] * 16.0f);
1819 break;
1820
1821 case QUNIFORM_VIEWPORT_Z_OFFSET:
1822 cl_f(&vc4->uniforms, vc4->viewport.translate[2]);
1823 break;
1824 case QUNIFORM_VIEWPORT_Z_SCALE:
1825 cl_f(&vc4->uniforms, vc4->viewport.scale[2]);
1826 break;
1827
1828 case QUNIFORM_TEXTURE_CONFIG_P0:
1829 write_texture_p0(vc4, texstate, uinfo->data[i]);
1830 break;
1831
1832 case QUNIFORM_TEXTURE_CONFIG_P1:
1833 write_texture_p1(vc4, texstate, uinfo->data[i]);
1834 break;
1835
1836 case QUNIFORM_TEXRECT_SCALE_X:
1837 case QUNIFORM_TEXRECT_SCALE_Y:
1838 cl_u32(&vc4->uniforms,
1839 get_texrect_scale(texstate,
1840 uinfo->contents[i],
1841 uinfo->data[i]));
1842 break;
1843
1844 case QUNIFORM_BLEND_CONST_COLOR:
1845 cl_f(&vc4->uniforms,
1846 vc4->blend_color.color[uinfo->data[i]]);
1847 break;
1848
1849 case QUNIFORM_STENCIL:
1850 cl_u32(&vc4->uniforms,
1851 vc4->zsa->stencil_uniforms[uinfo->data[i]] |
1852 (uinfo->data[i] <= 1 ?
1853 (vc4->stencil_ref.ref_value[uinfo->data[i]] << 8) :
1854 0));
1855 break;
1856 }
1857 #if 0
1858 uint32_t written_val = *(uint32_t *)(vc4->uniforms.next - 4);
1859 fprintf(stderr, "%p/%d: %d: 0x%08x (%f)\n",
1860 shader, shader_index, i, written_val, uif(written_val));
1861 #endif
1862 }
1863 }
1864
1865 static void
1866 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
1867 {
1868 struct vc4_context *vc4 = vc4_context(pctx);
1869 vc4->prog.bind_fs = hwcso;
1870 vc4->prog.dirty |= VC4_SHADER_DIRTY_FP;
1871 vc4->dirty |= VC4_DIRTY_PROG;
1872 }
1873
1874 static void
1875 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
1876 {
1877 struct vc4_context *vc4 = vc4_context(pctx);
1878 vc4->prog.bind_vs = hwcso;
1879 vc4->prog.dirty |= VC4_SHADER_DIRTY_VP;
1880 vc4->dirty |= VC4_DIRTY_PROG;
1881 }
1882
1883 void
1884 vc4_program_init(struct pipe_context *pctx)
1885 {
1886 struct vc4_context *vc4 = vc4_context(pctx);
1887
1888 pctx->create_vs_state = vc4_shader_state_create;
1889 pctx->delete_vs_state = vc4_shader_state_delete;
1890
1891 pctx->create_fs_state = vc4_shader_state_create;
1892 pctx->delete_fs_state = vc4_shader_state_delete;
1893
1894 pctx->bind_fs_state = vc4_fp_state_bind;
1895 pctx->bind_vs_state = vc4_vp_state_bind;
1896
1897 vc4->fs_cache = util_hash_table_create(fs_cache_hash, fs_cache_compare);
1898 vc4->vs_cache = util_hash_table_create(vs_cache_hash, vs_cache_compare);
1899 }