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[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "pipe/p_state.h"
27 #include "util/u_format.h"
28 #include "util/u_hash_table.h"
29 #include "util/u_hash.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include "util/ralloc.h"
33 #include "tgsi/tgsi_dump.h"
34 #include "tgsi/tgsi_info.h"
35
36 #include "vc4_context.h"
37 #include "vc4_qpu.h"
38 #include "vc4_qir.h"
39 #ifdef USE_VC4_SIMULATOR
40 #include "simpenrose/simpenrose.h"
41 #endif
42
43 struct vc4_key {
44 struct pipe_shader_state *shader_state;
45 struct {
46 enum pipe_format format;
47 unsigned compare_mode:1;
48 unsigned compare_func:3;
49 unsigned wrap_s:3;
50 unsigned wrap_t:3;
51 uint8_t swizzle[4];
52 } tex[VC4_MAX_TEXTURE_SAMPLERS];
53 };
54
55 struct vc4_fs_key {
56 struct vc4_key base;
57 enum pipe_format color_format;
58 bool depth_enabled;
59 bool stencil_enabled;
60 bool stencil_twoside;
61 bool stencil_full_writemasks;
62 bool is_points;
63 bool is_lines;
64 bool alpha_test;
65 bool point_coord_upper_left;
66 uint8_t alpha_test_func;
67 uint32_t point_sprite_mask;
68
69 struct pipe_rt_blend_state blend;
70 };
71
72 struct vc4_vs_key {
73 struct vc4_key base;
74 enum pipe_format attr_formats[8];
75 bool per_vertex_point_size;
76 };
77
78 static void
79 resize_qreg_array(struct vc4_compile *c,
80 struct qreg **regs,
81 uint32_t *size,
82 uint32_t decl_size)
83 {
84 if (*size >= decl_size)
85 return;
86
87 uint32_t old_size = *size;
88 *size = MAX2(*size * 2, decl_size);
89 *regs = reralloc(c, *regs, struct qreg, *size);
90 if (!*regs) {
91 fprintf(stderr, "Malloc failure\n");
92 abort();
93 }
94
95 for (uint32_t i = old_size; i < *size; i++)
96 (*regs)[i] = c->undef;
97 }
98
99 static struct qreg
100 add_uniform(struct vc4_compile *c,
101 enum quniform_contents contents,
102 uint32_t data)
103 {
104 uint32_t uniform = c->num_uniforms++;
105 struct qreg u = { QFILE_UNIF, uniform };
106
107 c->uniform_contents[uniform] = contents;
108 c->uniform_data[uniform] = data;
109
110 return u;
111 }
112
113 static struct qreg
114 get_temp_for_uniform(struct vc4_compile *c, enum quniform_contents contents,
115 uint32_t data)
116 {
117 struct qreg u = add_uniform(c, contents, data);
118 struct qreg t = qir_MOV(c, u);
119 return t;
120 }
121
122 static struct qreg
123 qir_uniform_ui(struct vc4_compile *c, uint32_t ui)
124 {
125 return get_temp_for_uniform(c, QUNIFORM_CONSTANT, ui);
126 }
127
128 static struct qreg
129 qir_uniform_f(struct vc4_compile *c, float f)
130 {
131 return qir_uniform_ui(c, fui(f));
132 }
133
134 static struct qreg
135 get_src(struct vc4_compile *c, unsigned tgsi_op,
136 struct tgsi_src_register *src, int i)
137 {
138 struct qreg r = c->undef;
139
140 uint32_t s = i;
141 switch (i) {
142 case TGSI_SWIZZLE_X:
143 s = src->SwizzleX;
144 break;
145 case TGSI_SWIZZLE_Y:
146 s = src->SwizzleY;
147 break;
148 case TGSI_SWIZZLE_Z:
149 s = src->SwizzleZ;
150 break;
151 case TGSI_SWIZZLE_W:
152 s = src->SwizzleW;
153 break;
154 default:
155 abort();
156 }
157
158 assert(!src->Indirect);
159
160 switch (src->File) {
161 case TGSI_FILE_NULL:
162 return r;
163 case TGSI_FILE_TEMPORARY:
164 r = c->temps[src->Index * 4 + s];
165 break;
166 case TGSI_FILE_IMMEDIATE:
167 r = c->consts[src->Index * 4 + s];
168 break;
169 case TGSI_FILE_CONSTANT:
170 r = get_temp_for_uniform(c, QUNIFORM_UNIFORM,
171 src->Index * 4 + s);
172 break;
173 case TGSI_FILE_INPUT:
174 r = c->inputs[src->Index * 4 + s];
175 break;
176 case TGSI_FILE_SAMPLER:
177 case TGSI_FILE_SAMPLER_VIEW:
178 r = c->undef;
179 break;
180 default:
181 fprintf(stderr, "unknown src file %d\n", src->File);
182 abort();
183 }
184
185 if (src->Absolute)
186 r = qir_FMAXABS(c, r, r);
187
188 if (src->Negate) {
189 switch (tgsi_opcode_infer_src_type(tgsi_op)) {
190 case TGSI_TYPE_SIGNED:
191 case TGSI_TYPE_UNSIGNED:
192 r = qir_SUB(c, qir_uniform_ui(c, 0), r);
193 break;
194 default:
195 r = qir_FSUB(c, qir_uniform_f(c, 0.0), r);
196 break;
197 }
198 }
199
200 return r;
201 };
202
203
204 static void
205 update_dst(struct vc4_compile *c, struct tgsi_full_instruction *tgsi_inst,
206 int i, struct qreg val)
207 {
208 struct tgsi_dst_register *tgsi_dst = &tgsi_inst->Dst[0].Register;
209
210 assert(!tgsi_dst->Indirect);
211
212 switch (tgsi_dst->File) {
213 case TGSI_FILE_TEMPORARY:
214 c->temps[tgsi_dst->Index * 4 + i] = val;
215 break;
216 case TGSI_FILE_OUTPUT:
217 c->outputs[tgsi_dst->Index * 4 + i] = val;
218 c->num_outputs = MAX2(c->num_outputs,
219 tgsi_dst->Index * 4 + i + 1);
220 break;
221 default:
222 fprintf(stderr, "unknown dst file %d\n", tgsi_dst->File);
223 abort();
224 }
225 };
226
227 static struct qreg
228 get_swizzled_channel(struct vc4_compile *c,
229 struct qreg *srcs, int swiz)
230 {
231 switch (swiz) {
232 default:
233 case UTIL_FORMAT_SWIZZLE_NONE:
234 fprintf(stderr, "warning: unknown swizzle\n");
235 /* FALLTHROUGH */
236 case UTIL_FORMAT_SWIZZLE_0:
237 return qir_uniform_f(c, 0.0);
238 case UTIL_FORMAT_SWIZZLE_1:
239 return qir_uniform_f(c, 1.0);
240 case UTIL_FORMAT_SWIZZLE_X:
241 case UTIL_FORMAT_SWIZZLE_Y:
242 case UTIL_FORMAT_SWIZZLE_Z:
243 case UTIL_FORMAT_SWIZZLE_W:
244 return srcs[swiz];
245 }
246 }
247
248 static struct qreg
249 tgsi_to_qir_alu(struct vc4_compile *c,
250 struct tgsi_full_instruction *tgsi_inst,
251 enum qop op, struct qreg *src, int i)
252 {
253 struct qreg dst = qir_get_temp(c);
254 qir_emit(c, qir_inst4(op, dst,
255 src[0 * 4 + i],
256 src[1 * 4 + i],
257 src[2 * 4 + i],
258 c->undef));
259 return dst;
260 }
261
262 static struct qreg
263 tgsi_to_qir_umul(struct vc4_compile *c,
264 struct tgsi_full_instruction *tgsi_inst,
265 enum qop op, struct qreg *src, int i)
266 {
267 struct qreg src0_hi = qir_SHR(c, src[0 * 4 + i],
268 qir_uniform_ui(c, 16));
269 struct qreg src0_lo = qir_AND(c, src[0 * 4 + i],
270 qir_uniform_ui(c, 0xffff));
271 struct qreg src1_hi = qir_SHR(c, src[1 * 4 + i],
272 qir_uniform_ui(c, 16));
273 struct qreg src1_lo = qir_AND(c, src[1 * 4 + i],
274 qir_uniform_ui(c, 0xffff));
275
276 struct qreg hilo = qir_MUL24(c, src0_hi, src1_lo);
277 struct qreg lohi = qir_MUL24(c, src0_lo, src1_hi);
278 struct qreg lolo = qir_MUL24(c, src0_lo, src1_lo);
279
280 return qir_ADD(c, lolo, qir_SHL(c,
281 qir_ADD(c, hilo, lohi),
282 qir_uniform_ui(c, 16)));
283 }
284
285 static struct qreg
286 tgsi_to_qir_idiv(struct vc4_compile *c,
287 struct tgsi_full_instruction *tgsi_inst,
288 enum qop op, struct qreg *src, int i)
289 {
290 return qir_FTOI(c, qir_FMUL(c,
291 qir_ITOF(c, src[0 * 4 + i]),
292 qir_RCP(c, qir_ITOF(c, src[1 * 4 + i]))));
293 }
294
295 static struct qreg
296 tgsi_to_qir_ineg(struct vc4_compile *c,
297 struct tgsi_full_instruction *tgsi_inst,
298 enum qop op, struct qreg *src, int i)
299 {
300 return qir_SUB(c, qir_uniform_ui(c, 0), src[0 * 4 + i]);
301 }
302
303 static struct qreg
304 tgsi_to_qir_seq(struct vc4_compile *c,
305 struct tgsi_full_instruction *tgsi_inst,
306 enum qop op, struct qreg *src, int i)
307 {
308 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
309 return qir_SEL_X_0_ZS(c, qir_uniform_f(c, 1.0));
310 }
311
312 static struct qreg
313 tgsi_to_qir_sne(struct vc4_compile *c,
314 struct tgsi_full_instruction *tgsi_inst,
315 enum qop op, struct qreg *src, int i)
316 {
317 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
318 return qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0));
319 }
320
321 static struct qreg
322 tgsi_to_qir_slt(struct vc4_compile *c,
323 struct tgsi_full_instruction *tgsi_inst,
324 enum qop op, struct qreg *src, int i)
325 {
326 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
327 return qir_SEL_X_0_NS(c, qir_uniform_f(c, 1.0));
328 }
329
330 static struct qreg
331 tgsi_to_qir_sge(struct vc4_compile *c,
332 struct tgsi_full_instruction *tgsi_inst,
333 enum qop op, struct qreg *src, int i)
334 {
335 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
336 return qir_SEL_X_0_NC(c, qir_uniform_f(c, 1.0));
337 }
338
339 static struct qreg
340 tgsi_to_qir_fseq(struct vc4_compile *c,
341 struct tgsi_full_instruction *tgsi_inst,
342 enum qop op, struct qreg *src, int i)
343 {
344 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
345 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
346 }
347
348 static struct qreg
349 tgsi_to_qir_fsne(struct vc4_compile *c,
350 struct tgsi_full_instruction *tgsi_inst,
351 enum qop op, struct qreg *src, int i)
352 {
353 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
354 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
355 }
356
357 static struct qreg
358 tgsi_to_qir_fslt(struct vc4_compile *c,
359 struct tgsi_full_instruction *tgsi_inst,
360 enum qop op, struct qreg *src, int i)
361 {
362 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
363 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
364 }
365
366 static struct qreg
367 tgsi_to_qir_fsge(struct vc4_compile *c,
368 struct tgsi_full_instruction *tgsi_inst,
369 enum qop op, struct qreg *src, int i)
370 {
371 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
372 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
373 }
374
375 static struct qreg
376 tgsi_to_qir_useq(struct vc4_compile *c,
377 struct tgsi_full_instruction *tgsi_inst,
378 enum qop op, struct qreg *src, int i)
379 {
380 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
381 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
382 }
383
384 static struct qreg
385 tgsi_to_qir_usne(struct vc4_compile *c,
386 struct tgsi_full_instruction *tgsi_inst,
387 enum qop op, struct qreg *src, int i)
388 {
389 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
390 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
391 }
392
393 static struct qreg
394 tgsi_to_qir_islt(struct vc4_compile *c,
395 struct tgsi_full_instruction *tgsi_inst,
396 enum qop op, struct qreg *src, int i)
397 {
398 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
399 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
400 }
401
402 static struct qreg
403 tgsi_to_qir_isge(struct vc4_compile *c,
404 struct tgsi_full_instruction *tgsi_inst,
405 enum qop op, struct qreg *src, int i)
406 {
407 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
408 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
409 }
410
411 static struct qreg
412 tgsi_to_qir_cmp(struct vc4_compile *c,
413 struct tgsi_full_instruction *tgsi_inst,
414 enum qop op, struct qreg *src, int i)
415 {
416 qir_SF(c, src[0 * 4 + i]);
417 return qir_SEL_X_Y_NS(c,
418 src[1 * 4 + i],
419 src[2 * 4 + i]);
420 }
421
422 static struct qreg
423 tgsi_to_qir_mad(struct vc4_compile *c,
424 struct tgsi_full_instruction *tgsi_inst,
425 enum qop op, struct qreg *src, int i)
426 {
427 return qir_FADD(c,
428 qir_FMUL(c,
429 src[0 * 4 + i],
430 src[1 * 4 + i]),
431 src[2 * 4 + i]);
432 }
433
434 static struct qreg
435 tgsi_to_qir_lit(struct vc4_compile *c,
436 struct tgsi_full_instruction *tgsi_inst,
437 enum qop op, struct qreg *src, int i)
438 {
439 struct qreg x = src[0 * 4 + 0];
440 struct qreg y = src[0 * 4 + 1];
441 struct qreg w = src[0 * 4 + 3];
442
443 switch (i) {
444 case 0:
445 case 3:
446 return qir_uniform_f(c, 1.0);
447 case 1:
448 return qir_FMAX(c, src[0 * 4 + 0], qir_uniform_f(c, 0.0));
449 case 2: {
450 struct qreg zero = qir_uniform_f(c, 0.0);
451
452 qir_SF(c, x);
453 /* XXX: Clamp w to -128..128 */
454 return qir_SEL_X_0_NC(c,
455 qir_EXP2(c, qir_FMUL(c,
456 w,
457 qir_LOG2(c,
458 qir_FMAX(c,
459 y,
460 zero)))));
461 }
462 default:
463 assert(!"not reached");
464 return c->undef;
465 }
466 }
467
468 static struct qreg
469 tgsi_to_qir_lrp(struct vc4_compile *c,
470 struct tgsi_full_instruction *tgsi_inst,
471 enum qop op, struct qreg *src, int i)
472 {
473 struct qreg src0 = src[0 * 4 + i];
474 struct qreg src1 = src[1 * 4 + i];
475 struct qreg src2 = src[2 * 4 + i];
476
477 /* LRP is:
478 * src0 * src1 + (1 - src0) * src2.
479 * -> src0 * src1 + src2 - src0 * src2
480 * -> src2 + src0 * (src1 - src2)
481 */
482 return qir_FADD(c, src2, qir_FMUL(c, src0, qir_FSUB(c, src1, src2)));
483
484 }
485
486 static void
487 tgsi_to_qir_tex(struct vc4_compile *c,
488 struct tgsi_full_instruction *tgsi_inst,
489 enum qop op, struct qreg *src)
490 {
491 assert(!tgsi_inst->Instruction.Saturate);
492
493 struct qreg s = src[0 * 4 + 0];
494 struct qreg t = src[0 * 4 + 1];
495 struct qreg r = src[0 * 4 + 2];
496 uint32_t unit = tgsi_inst->Src[1].Register.Index;
497
498 struct qreg proj = c->undef;
499 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
500 proj = qir_RCP(c, src[0 * 4 + 3]);
501 s = qir_FMUL(c, s, proj);
502 t = qir_FMUL(c, t, proj);
503 }
504
505 struct qreg texture_u[] = {
506 add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit),
507 add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
508 add_uniform(c, QUNIFORM_CONSTANT, 0),
509 add_uniform(c, QUNIFORM_CONSTANT, 0),
510 };
511 uint32_t next_texture_u = 0;
512
513 /* There is no native support for GL texture rectangle coordinates, so
514 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
515 * 1]).
516 */
517 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_RECT ||
518 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT) {
519 s = qir_FMUL(c, s,
520 get_temp_for_uniform(c,
521 QUNIFORM_TEXRECT_SCALE_X,
522 unit));
523 t = qir_FMUL(c, t,
524 get_temp_for_uniform(c,
525 QUNIFORM_TEXRECT_SCALE_Y,
526 unit));
527 }
528
529 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
530 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE) {
531 struct qreg ma = qir_FMAXABS(c, qir_FMAXABS(c, s, t), r);
532 struct qreg rcp_ma = qir_RCP(c, ma);
533 s = qir_FMUL(c, s, rcp_ma);
534 t = qir_FMUL(c, t, rcp_ma);
535 r = qir_FMUL(c, r, rcp_ma);
536
537 texture_u[2] = add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P2, unit);
538
539 qir_TEX_R(c, r, texture_u[next_texture_u++]);
540 } else if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
541 c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP ||
542 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
543 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
544 qir_TEX_R(c, get_temp_for_uniform(c, QUNIFORM_TEXTURE_BORDER_COLOR, unit),
545 texture_u[next_texture_u++]);
546 }
547
548 if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP) {
549 s = qir_FMIN(c, qir_FMAX(c, s, qir_uniform_f(c, 0.0)),
550 qir_uniform_f(c, 1.0));
551 }
552
553 if (c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
554 t = qir_FMIN(c, qir_FMAX(c, t, qir_uniform_f(c, 0.0)),
555 qir_uniform_f(c, 1.0));
556 }
557
558 qir_TEX_T(c, t, texture_u[next_texture_u++]);
559
560 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB)
561 qir_TEX_B(c, src[0 * 4 + 3], texture_u[next_texture_u++]);
562
563 qir_TEX_S(c, s, texture_u[next_texture_u++]);
564
565 c->num_texture_samples++;
566 struct qreg r4 = qir_TEX_RESULT(c);
567
568 enum pipe_format format = c->key->tex[unit].format;
569
570 struct qreg unpacked[4];
571 if (util_format_is_depth_or_stencil(format)) {
572 struct qreg depthf = qir_ITOF(c, qir_SHR(c, r4,
573 qir_uniform_ui(c, 8)));
574 struct qreg normalized = qir_FMUL(c, depthf,
575 qir_uniform_f(c, 1.0f/0xffffff));
576
577 struct qreg depth_output;
578
579 struct qreg compare = src[0 * 4 + 2];
580
581 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP)
582 compare = qir_FMUL(c, compare, proj);
583
584 struct qreg one = qir_uniform_f(c, 1.0f);
585 if (c->key->tex[unit].compare_mode) {
586 switch (c->key->tex[unit].compare_func) {
587 case PIPE_FUNC_NEVER:
588 depth_output = qir_uniform_f(c, 0.0f);
589 break;
590 case PIPE_FUNC_ALWAYS:
591 depth_output = one;
592 break;
593 case PIPE_FUNC_EQUAL:
594 qir_SF(c, qir_FSUB(c, compare, normalized));
595 depth_output = qir_SEL_X_0_ZS(c, one);
596 break;
597 case PIPE_FUNC_NOTEQUAL:
598 qir_SF(c, qir_FSUB(c, compare, normalized));
599 depth_output = qir_SEL_X_0_ZC(c, one);
600 break;
601 case PIPE_FUNC_GREATER:
602 qir_SF(c, qir_FSUB(c, compare, normalized));
603 depth_output = qir_SEL_X_0_NC(c, one);
604 break;
605 case PIPE_FUNC_GEQUAL:
606 qir_SF(c, qir_FSUB(c, normalized, compare));
607 depth_output = qir_SEL_X_0_NS(c, one);
608 break;
609 case PIPE_FUNC_LESS:
610 qir_SF(c, qir_FSUB(c, compare, normalized));
611 depth_output = qir_SEL_X_0_NS(c, one);
612 break;
613 case PIPE_FUNC_LEQUAL:
614 qir_SF(c, qir_FSUB(c, normalized, compare));
615 depth_output = qir_SEL_X_0_NC(c, one);
616 break;
617 }
618 } else {
619 depth_output = normalized;
620 }
621
622 for (int i = 0; i < 4; i++)
623 unpacked[i] = depth_output;
624 } else {
625 for (int i = 0; i < 4; i++)
626 unpacked[i] = qir_R4_UNPACK(c, r4, i);
627 }
628
629 const uint8_t *format_swiz = vc4_get_format_swizzle(format);
630 uint8_t swiz[4];
631 util_format_compose_swizzles(format_swiz, c->key->tex[unit].swizzle, swiz);
632 for (int i = 0; i < 4; i++) {
633 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
634 continue;
635
636 update_dst(c, tgsi_inst, i,
637 get_swizzled_channel(c, unpacked, swiz[i]));
638 }
639 }
640
641 static struct qreg
642 tgsi_to_qir_pow(struct vc4_compile *c,
643 struct tgsi_full_instruction *tgsi_inst,
644 enum qop op, struct qreg *src, int i)
645 {
646 /* Note that this instruction replicates its result from the x channel
647 */
648 return qir_EXP2(c, qir_FMUL(c,
649 src[1 * 4 + 0],
650 qir_LOG2(c, src[0 * 4 + 0])));
651 }
652
653 static struct qreg
654 tgsi_to_qir_trunc(struct vc4_compile *c,
655 struct tgsi_full_instruction *tgsi_inst,
656 enum qop op, struct qreg *src, int i)
657 {
658 return qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
659 }
660
661 /**
662 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
663 * to zero).
664 */
665 static struct qreg
666 tgsi_to_qir_frc(struct vc4_compile *c,
667 struct tgsi_full_instruction *tgsi_inst,
668 enum qop op, struct qreg *src, int i)
669 {
670 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
671 struct qreg diff = qir_FSUB(c, src[0 * 4 + i], trunc);
672 qir_SF(c, diff);
673 return qir_SEL_X_Y_NS(c,
674 qir_FADD(c, diff, qir_uniform_f(c, 1.0)),
675 diff);
676 }
677
678 /**
679 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
680 * zero).
681 */
682 static struct qreg
683 tgsi_to_qir_flr(struct vc4_compile *c,
684 struct tgsi_full_instruction *tgsi_inst,
685 enum qop op, struct qreg *src, int i)
686 {
687 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
688
689 /* This will be < 0 if we truncated and the truncation was of a value
690 * that was < 0 in the first place.
691 */
692 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], trunc));
693
694 return qir_SEL_X_Y_NS(c,
695 qir_FSUB(c, trunc, qir_uniform_f(c, 1.0)),
696 trunc);
697 }
698
699 static struct qreg
700 tgsi_to_qir_dp(struct vc4_compile *c,
701 struct tgsi_full_instruction *tgsi_inst,
702 int num, struct qreg *src, int i)
703 {
704 struct qreg sum = qir_FMUL(c, src[0 * 4 + 0], src[1 * 4 + 0]);
705 for (int j = 1; j < num; j++) {
706 sum = qir_FADD(c, sum, qir_FMUL(c,
707 src[0 * 4 + j],
708 src[1 * 4 + j]));
709 }
710 return sum;
711 }
712
713 static struct qreg
714 tgsi_to_qir_dp2(struct vc4_compile *c,
715 struct tgsi_full_instruction *tgsi_inst,
716 enum qop op, struct qreg *src, int i)
717 {
718 return tgsi_to_qir_dp(c, tgsi_inst, 2, src, i);
719 }
720
721 static struct qreg
722 tgsi_to_qir_dp3(struct vc4_compile *c,
723 struct tgsi_full_instruction *tgsi_inst,
724 enum qop op, struct qreg *src, int i)
725 {
726 return tgsi_to_qir_dp(c, tgsi_inst, 3, src, i);
727 }
728
729 static struct qreg
730 tgsi_to_qir_dp4(struct vc4_compile *c,
731 struct tgsi_full_instruction *tgsi_inst,
732 enum qop op, struct qreg *src, int i)
733 {
734 return tgsi_to_qir_dp(c, tgsi_inst, 4, src, i);
735 }
736
737 static struct qreg
738 tgsi_to_qir_abs(struct vc4_compile *c,
739 struct tgsi_full_instruction *tgsi_inst,
740 enum qop op, struct qreg *src, int i)
741 {
742 struct qreg arg = src[0 * 4 + i];
743 return qir_FMAXABS(c, arg, arg);
744 }
745
746 /* Note that this instruction replicates its result from the x channel */
747 static struct qreg
748 tgsi_to_qir_sin(struct vc4_compile *c,
749 struct tgsi_full_instruction *tgsi_inst,
750 enum qop op, struct qreg *src, int i)
751 {
752 float coeff[] = {
753 2.0 * M_PI,
754 -pow(2.0 * M_PI, 3) / (3 * 2 * 1),
755 pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
756 -pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
757 };
758
759 struct qreg scaled_x =
760 qir_FMUL(c,
761 src[0 * 4 + 0],
762 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
763
764
765 struct qreg x = tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0);
766 struct qreg x2 = qir_FMUL(c, x, x);
767 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
768 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
769 x = qir_FMUL(c, x, x2);
770 sum = qir_FADD(c,
771 sum,
772 qir_FMUL(c,
773 x,
774 qir_uniform_f(c, coeff[i])));
775 }
776 return sum;
777 }
778
779 /* Note that this instruction replicates its result from the x channel */
780 static struct qreg
781 tgsi_to_qir_cos(struct vc4_compile *c,
782 struct tgsi_full_instruction *tgsi_inst,
783 enum qop op, struct qreg *src, int i)
784 {
785 float coeff[] = {
786 1.0f,
787 -pow(2.0 * M_PI, 2) / (2 * 1),
788 pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
789 -pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
790 };
791
792 struct qreg scaled_x =
793 qir_FMUL(c, src[0 * 4 + 0],
794 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
795 struct qreg x_frac = tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0);
796
797 struct qreg sum = qir_uniform_f(c, coeff[0]);
798 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
799 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
800 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
801 if (i != 1)
802 x = qir_FMUL(c, x, x2);
803
804 struct qreg mul = qir_FMUL(c,
805 x,
806 qir_uniform_f(c, coeff[i]));
807 if (i == 0)
808 sum = mul;
809 else
810 sum = qir_FADD(c, sum, mul);
811 }
812 return sum;
813 }
814
815 static void
816 emit_vertex_input(struct vc4_compile *c, int attr)
817 {
818 enum pipe_format format = c->vs_key->attr_formats[attr];
819 struct qreg vpm_reads[4];
820
821 /* Right now, we're setting the VPM offsets to be 16 bytes wide every
822 * time, so we always read 4 32-bit VPM entries.
823 */
824 for (int i = 0; i < 4; i++) {
825 vpm_reads[i] = qir_get_temp(c);
826 qir_emit(c, qir_inst(QOP_VPM_READ,
827 vpm_reads[i],
828 c->undef,
829 c->undef));
830 c->num_inputs++;
831 }
832
833 bool format_warned = false;
834 const struct util_format_description *desc =
835 util_format_description(format);
836
837 for (int i = 0; i < 4; i++) {
838 uint8_t swiz = desc->swizzle[i];
839 struct qreg result;
840
841 if (swiz > UTIL_FORMAT_SWIZZLE_W)
842 result = get_swizzled_channel(c, vpm_reads, swiz);
843 else if (desc->channel[swiz].size == 32 &&
844 desc->channel[swiz].type == UTIL_FORMAT_TYPE_FLOAT) {
845 result = get_swizzled_channel(c, vpm_reads, swiz);
846 } else if (desc->channel[swiz].size == 8 &&
847 (desc->channel[swiz].type == UTIL_FORMAT_TYPE_UNSIGNED ||
848 desc->channel[swiz].type == UTIL_FORMAT_TYPE_SIGNED) &&
849 desc->channel[swiz].normalized) {
850 struct qreg vpm = vpm_reads[0];
851 if (desc->channel[swiz].type == UTIL_FORMAT_TYPE_SIGNED)
852 vpm = qir_XOR(c, vpm, qir_uniform_ui(c, 0x80808080));
853 result = qir_UNPACK_8(c, vpm, swiz);
854 } else {
855 if (!format_warned) {
856 fprintf(stderr,
857 "vtx element %d unsupported type: %s\n",
858 attr, util_format_name(format));
859 format_warned = true;
860 }
861 result = qir_uniform_f(c, 0.0);
862 }
863
864 if (desc->channel[swiz].normalized &&
865 desc->channel[swiz].type == UTIL_FORMAT_TYPE_SIGNED) {
866 result = qir_FSUB(c,
867 qir_FMUL(c,
868 result,
869 qir_uniform_f(c, 2.0)),
870 qir_uniform_f(c, 1.0));
871 }
872
873 c->inputs[attr * 4 + i] = result;
874 }
875 }
876
877 static void
878 tgsi_to_qir_kill_if(struct vc4_compile *c, struct qreg *src, int i)
879 {
880 if (c->discard.file == QFILE_NULL)
881 c->discard = qir_uniform_f(c, 0.0);
882 qir_SF(c, src[0 * 4 + i]);
883 c->discard = qir_SEL_X_Y_NS(c, qir_uniform_f(c, 1.0),
884 c->discard);
885 }
886
887 static void
888 emit_fragcoord_input(struct vc4_compile *c, int attr)
889 {
890 c->inputs[attr * 4 + 0] = qir_FRAG_X(c);
891 c->inputs[attr * 4 + 1] = qir_FRAG_Y(c);
892 c->inputs[attr * 4 + 2] =
893 qir_FMUL(c,
894 qir_ITOF(c, qir_FRAG_Z(c)),
895 qir_uniform_f(c, 1.0 / 0xffffff));
896 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
897 }
898
899 static void
900 emit_point_coord_input(struct vc4_compile *c, int attr)
901 {
902 if (c->point_x.file == QFILE_NULL) {
903 c->point_x = qir_uniform_f(c, 0.0);
904 c->point_y = qir_uniform_f(c, 0.0);
905 }
906
907 c->inputs[attr * 4 + 0] = c->point_x;
908 if (c->fs_key->point_coord_upper_left) {
909 c->inputs[attr * 4 + 1] = qir_FSUB(c,
910 qir_uniform_f(c, 1.0),
911 c->point_y);
912 } else {
913 c->inputs[attr * 4 + 1] = c->point_y;
914 }
915 c->inputs[attr * 4 + 2] = qir_uniform_f(c, 0.0);
916 c->inputs[attr * 4 + 3] = qir_uniform_f(c, 1.0);
917 }
918
919 static struct qreg
920 emit_fragment_varying(struct vc4_compile *c, int index)
921 {
922 struct qreg vary = {
923 QFILE_VARY,
924 index
925 };
926
927 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
928 }
929
930 static void
931 emit_fragment_input(struct vc4_compile *c, int attr,
932 struct tgsi_full_declaration *decl)
933 {
934 for (int i = 0; i < 4; i++) {
935 c->inputs[attr * 4 + i] =
936 emit_fragment_varying(c, attr * 4 + i);
937 c->num_inputs++;
938
939 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR ||
940 decl->Semantic.Name == TGSI_SEMANTIC_BCOLOR)
941 c->color_inputs |= 1 << i;
942 }
943 }
944
945 static void
946 emit_tgsi_declaration(struct vc4_compile *c,
947 struct tgsi_full_declaration *decl)
948 {
949 switch (decl->Declaration.File) {
950 case TGSI_FILE_TEMPORARY:
951 resize_qreg_array(c, &c->temps, &c->temps_array_size,
952 (decl->Range.Last + 1) * 4);
953 break;
954
955 case TGSI_FILE_INPUT:
956 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
957 (decl->Range.Last + 1) * 4);
958
959 for (int i = decl->Range.First;
960 i <= decl->Range.Last;
961 i++) {
962 if (c->stage == QSTAGE_FRAG) {
963 if (decl->Semantic.Name ==
964 TGSI_SEMANTIC_POSITION) {
965 emit_fragcoord_input(c, i);
966 } else if (decl->Semantic.Name == TGSI_SEMANTIC_GENERIC &&
967 (c->fs_key->point_sprite_mask &
968 (1 << decl->Semantic.Index))) {
969 emit_point_coord_input(c, i);
970 } else {
971 emit_fragment_input(c, i, decl);
972 }
973 } else {
974 emit_vertex_input(c, i);
975 }
976 }
977 break;
978
979 case TGSI_FILE_OUTPUT:
980 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
981 (decl->Range.Last + 1) * 4);
982
983 switch (decl->Semantic.Name) {
984 case TGSI_SEMANTIC_POSITION:
985 c->output_position_index = decl->Range.First * 4;
986 break;
987 case TGSI_SEMANTIC_COLOR:
988 c->output_color_index = decl->Range.First * 4;
989 break;
990 case TGSI_SEMANTIC_PSIZE:
991 c->output_point_size_index = decl->Range.First * 4;
992 break;
993 }
994
995 break;
996 }
997 }
998
999 static void
1000 emit_tgsi_instruction(struct vc4_compile *c,
1001 struct tgsi_full_instruction *tgsi_inst)
1002 {
1003 struct {
1004 enum qop op;
1005 struct qreg (*func)(struct vc4_compile *c,
1006 struct tgsi_full_instruction *tgsi_inst,
1007 enum qop op,
1008 struct qreg *src, int i);
1009 } op_trans[] = {
1010 [TGSI_OPCODE_MOV] = { QOP_MOV, tgsi_to_qir_alu },
1011 [TGSI_OPCODE_ABS] = { 0, tgsi_to_qir_abs },
1012 [TGSI_OPCODE_MUL] = { QOP_FMUL, tgsi_to_qir_alu },
1013 [TGSI_OPCODE_ADD] = { QOP_FADD, tgsi_to_qir_alu },
1014 [TGSI_OPCODE_SUB] = { QOP_FSUB, tgsi_to_qir_alu },
1015 [TGSI_OPCODE_MIN] = { QOP_FMIN, tgsi_to_qir_alu },
1016 [TGSI_OPCODE_MAX] = { QOP_FMAX, tgsi_to_qir_alu },
1017 [TGSI_OPCODE_F2I] = { QOP_FTOI, tgsi_to_qir_alu },
1018 [TGSI_OPCODE_I2F] = { QOP_ITOF, tgsi_to_qir_alu },
1019 [TGSI_OPCODE_UADD] = { QOP_ADD, tgsi_to_qir_alu },
1020 [TGSI_OPCODE_USHR] = { QOP_SHR, tgsi_to_qir_alu },
1021 [TGSI_OPCODE_ISHR] = { QOP_ASR, tgsi_to_qir_alu },
1022 [TGSI_OPCODE_SHL] = { QOP_SHL, tgsi_to_qir_alu },
1023 [TGSI_OPCODE_IMIN] = { QOP_MIN, tgsi_to_qir_alu },
1024 [TGSI_OPCODE_IMAX] = { QOP_MAX, tgsi_to_qir_alu },
1025 [TGSI_OPCODE_AND] = { QOP_AND, tgsi_to_qir_alu },
1026 [TGSI_OPCODE_OR] = { QOP_OR, tgsi_to_qir_alu },
1027 [TGSI_OPCODE_XOR] = { QOP_XOR, tgsi_to_qir_alu },
1028 [TGSI_OPCODE_NOT] = { QOP_NOT, tgsi_to_qir_alu },
1029
1030 [TGSI_OPCODE_UMUL] = { 0, tgsi_to_qir_umul },
1031 [TGSI_OPCODE_IDIV] = { 0, tgsi_to_qir_idiv },
1032 [TGSI_OPCODE_INEG] = { 0, tgsi_to_qir_ineg },
1033
1034 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_alu },
1035 [TGSI_OPCODE_SEQ] = { 0, tgsi_to_qir_seq },
1036 [TGSI_OPCODE_SNE] = { 0, tgsi_to_qir_sne },
1037 [TGSI_OPCODE_SGE] = { 0, tgsi_to_qir_sge },
1038 [TGSI_OPCODE_SLT] = { 0, tgsi_to_qir_slt },
1039 [TGSI_OPCODE_FSEQ] = { 0, tgsi_to_qir_fseq },
1040 [TGSI_OPCODE_FSNE] = { 0, tgsi_to_qir_fsne },
1041 [TGSI_OPCODE_FSGE] = { 0, tgsi_to_qir_fsge },
1042 [TGSI_OPCODE_FSLT] = { 0, tgsi_to_qir_fslt },
1043 [TGSI_OPCODE_USEQ] = { 0, tgsi_to_qir_useq },
1044 [TGSI_OPCODE_USNE] = { 0, tgsi_to_qir_usne },
1045 [TGSI_OPCODE_ISGE] = { 0, tgsi_to_qir_isge },
1046 [TGSI_OPCODE_ISLT] = { 0, tgsi_to_qir_islt },
1047
1048 [TGSI_OPCODE_CMP] = { 0, tgsi_to_qir_cmp },
1049 [TGSI_OPCODE_MAD] = { 0, tgsi_to_qir_mad },
1050 [TGSI_OPCODE_DP2] = { 0, tgsi_to_qir_dp2 },
1051 [TGSI_OPCODE_DP3] = { 0, tgsi_to_qir_dp3 },
1052 [TGSI_OPCODE_DP4] = { 0, tgsi_to_qir_dp4 },
1053 [TGSI_OPCODE_RCP] = { QOP_RCP, tgsi_to_qir_alu },
1054 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_alu },
1055 [TGSI_OPCODE_EX2] = { QOP_EXP2, tgsi_to_qir_alu },
1056 [TGSI_OPCODE_LG2] = { QOP_LOG2, tgsi_to_qir_alu },
1057 [TGSI_OPCODE_LIT] = { 0, tgsi_to_qir_lit },
1058 [TGSI_OPCODE_LRP] = { 0, tgsi_to_qir_lrp },
1059 [TGSI_OPCODE_POW] = { 0, tgsi_to_qir_pow },
1060 [TGSI_OPCODE_TRUNC] = { 0, tgsi_to_qir_trunc },
1061 [TGSI_OPCODE_FRC] = { 0, tgsi_to_qir_frc },
1062 [TGSI_OPCODE_FLR] = { 0, tgsi_to_qir_flr },
1063 [TGSI_OPCODE_SIN] = { 0, tgsi_to_qir_sin },
1064 [TGSI_OPCODE_COS] = { 0, tgsi_to_qir_cos },
1065 };
1066 static int asdf = 0;
1067 uint32_t tgsi_op = tgsi_inst->Instruction.Opcode;
1068
1069 if (tgsi_op == TGSI_OPCODE_END)
1070 return;
1071
1072 struct qreg src_regs[12];
1073 for (int s = 0; s < 3; s++) {
1074 for (int i = 0; i < 4; i++) {
1075 src_regs[4 * s + i] =
1076 get_src(c, tgsi_inst->Instruction.Opcode,
1077 &tgsi_inst->Src[s].Register, i);
1078 }
1079 }
1080
1081 switch (tgsi_op) {
1082 case TGSI_OPCODE_TEX:
1083 case TGSI_OPCODE_TXP:
1084 case TGSI_OPCODE_TXB:
1085 tgsi_to_qir_tex(c, tgsi_inst,
1086 op_trans[tgsi_op].op, src_regs);
1087 return;
1088 case TGSI_OPCODE_KILL:
1089 c->discard = qir_uniform_f(c, 1.0);
1090 return;
1091 case TGSI_OPCODE_KILL_IF:
1092 for (int i = 0; i < 4; i++)
1093 tgsi_to_qir_kill_if(c, src_regs, i);
1094 return;
1095 default:
1096 break;
1097 }
1098
1099 if (tgsi_op > ARRAY_SIZE(op_trans) || !(op_trans[tgsi_op].func)) {
1100 fprintf(stderr, "unknown tgsi inst: ");
1101 tgsi_dump_instruction(tgsi_inst, asdf++);
1102 fprintf(stderr, "\n");
1103 abort();
1104 }
1105
1106 for (int i = 0; i < 4; i++) {
1107 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
1108 continue;
1109
1110 struct qreg result;
1111
1112 result = op_trans[tgsi_op].func(c, tgsi_inst,
1113 op_trans[tgsi_op].op,
1114 src_regs, i);
1115
1116 if (tgsi_inst->Instruction.Saturate) {
1117 float low = (tgsi_inst->Instruction.Saturate ==
1118 TGSI_SAT_MINUS_PLUS_ONE ? -1.0 : 0.0);
1119 result = qir_FMAX(c,
1120 qir_FMIN(c,
1121 result,
1122 qir_uniform_f(c, 1.0)),
1123 qir_uniform_f(c, low));
1124 }
1125
1126 update_dst(c, tgsi_inst, i, result);
1127 }
1128 }
1129
1130 static void
1131 parse_tgsi_immediate(struct vc4_compile *c, struct tgsi_full_immediate *imm)
1132 {
1133 for (int i = 0; i < 4; i++) {
1134 unsigned n = c->num_consts++;
1135 resize_qreg_array(c, &c->consts, &c->consts_array_size, n + 1);
1136 c->consts[n] = qir_uniform_ui(c, imm->u[i].Uint);
1137 }
1138 }
1139
1140 static struct qreg
1141 vc4_blend_channel(struct vc4_compile *c,
1142 struct qreg *dst,
1143 struct qreg *src,
1144 struct qreg val,
1145 unsigned factor,
1146 int channel)
1147 {
1148 switch(factor) {
1149 case PIPE_BLENDFACTOR_ONE:
1150 return val;
1151 case PIPE_BLENDFACTOR_SRC_COLOR:
1152 return qir_FMUL(c, val, src[channel]);
1153 case PIPE_BLENDFACTOR_SRC_ALPHA:
1154 return qir_FMUL(c, val, src[3]);
1155 case PIPE_BLENDFACTOR_DST_ALPHA:
1156 return qir_FMUL(c, val, dst[3]);
1157 case PIPE_BLENDFACTOR_DST_COLOR:
1158 return qir_FMUL(c, val, dst[channel]);
1159 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
1160 return qir_FMIN(c, src[3], qir_FSUB(c,
1161 qir_uniform_f(c, 1.0),
1162 dst[3]));
1163 case PIPE_BLENDFACTOR_CONST_COLOR:
1164 return qir_FMUL(c, val,
1165 get_temp_for_uniform(c,
1166 QUNIFORM_BLEND_CONST_COLOR,
1167 channel));
1168 case PIPE_BLENDFACTOR_CONST_ALPHA:
1169 return qir_FMUL(c, val,
1170 get_temp_for_uniform(c,
1171 QUNIFORM_BLEND_CONST_COLOR,
1172 3));
1173 case PIPE_BLENDFACTOR_ZERO:
1174 return qir_uniform_f(c, 0.0);
1175 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
1176 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1177 src[channel]));
1178 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
1179 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1180 src[3]));
1181 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
1182 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1183 dst[3]));
1184 case PIPE_BLENDFACTOR_INV_DST_COLOR:
1185 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1186 dst[channel]));
1187 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
1188 return qir_FMUL(c, val,
1189 qir_FSUB(c, qir_uniform_f(c, 1.0),
1190 get_temp_for_uniform(c,
1191 QUNIFORM_BLEND_CONST_COLOR,
1192 channel)));
1193 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
1194 return qir_FMUL(c, val,
1195 qir_FSUB(c, qir_uniform_f(c, 1.0),
1196 get_temp_for_uniform(c,
1197 QUNIFORM_BLEND_CONST_COLOR,
1198 3)));
1199
1200 default:
1201 case PIPE_BLENDFACTOR_SRC1_COLOR:
1202 case PIPE_BLENDFACTOR_SRC1_ALPHA:
1203 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
1204 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
1205 /* Unsupported. */
1206 fprintf(stderr, "Unknown blend factor %d\n", factor);
1207 return val;
1208 }
1209 }
1210
1211 static struct qreg
1212 vc4_blend_func(struct vc4_compile *c,
1213 struct qreg src, struct qreg dst,
1214 unsigned func)
1215 {
1216 switch (func) {
1217 case PIPE_BLEND_ADD:
1218 return qir_FADD(c, src, dst);
1219 case PIPE_BLEND_SUBTRACT:
1220 return qir_FSUB(c, src, dst);
1221 case PIPE_BLEND_REVERSE_SUBTRACT:
1222 return qir_FSUB(c, dst, src);
1223 case PIPE_BLEND_MIN:
1224 return qir_FMIN(c, src, dst);
1225 case PIPE_BLEND_MAX:
1226 return qir_FMAX(c, src, dst);
1227
1228 default:
1229 /* Unsupported. */
1230 fprintf(stderr, "Unknown blend func %d\n", func);
1231 return src;
1232
1233 }
1234 }
1235
1236 /**
1237 * Implements fixed function blending in shader code.
1238 *
1239 * VC4 doesn't have any hardware support for blending. Instead, you read the
1240 * current contents of the destination from the tile buffer after having
1241 * waited for the scoreboard (which is handled by vc4_qpu_emit.c), then do
1242 * math using your output color and that destination value, and update the
1243 * output color appropriately.
1244 */
1245 static void
1246 vc4_blend(struct vc4_compile *c, struct qreg *result,
1247 struct qreg *dst_color, struct qreg *src_color)
1248 {
1249 struct pipe_rt_blend_state *blend = &c->fs_key->blend;
1250
1251 if (!blend->blend_enable) {
1252 for (int i = 0; i < 4; i++)
1253 result[i] = src_color[i];
1254 return;
1255 }
1256
1257 struct qreg src_blend[4], dst_blend[4];
1258 for (int i = 0; i < 3; i++) {
1259 src_blend[i] = vc4_blend_channel(c,
1260 dst_color, src_color,
1261 src_color[i],
1262 blend->rgb_src_factor, i);
1263 dst_blend[i] = vc4_blend_channel(c,
1264 dst_color, src_color,
1265 dst_color[i],
1266 blend->rgb_dst_factor, i);
1267 }
1268 src_blend[3] = vc4_blend_channel(c,
1269 dst_color, src_color,
1270 src_color[3],
1271 blend->alpha_src_factor, 3);
1272 dst_blend[3] = vc4_blend_channel(c,
1273 dst_color, src_color,
1274 dst_color[3],
1275 blend->alpha_dst_factor, 3);
1276
1277 for (int i = 0; i < 3; i++) {
1278 result[i] = vc4_blend_func(c,
1279 src_blend[i], dst_blend[i],
1280 blend->rgb_func);
1281 }
1282 result[3] = vc4_blend_func(c,
1283 src_blend[3], dst_blend[3],
1284 blend->alpha_func);
1285 }
1286
1287 static void
1288 alpha_test_discard(struct vc4_compile *c)
1289 {
1290 struct qreg src_alpha;
1291 struct qreg alpha_ref = get_temp_for_uniform(c, QUNIFORM_ALPHA_REF, 0);
1292
1293 if (!c->fs_key->alpha_test)
1294 return;
1295
1296 if (c->output_color_index != -1)
1297 src_alpha = c->outputs[c->output_color_index + 3];
1298 else
1299 src_alpha = qir_uniform_f(c, 1.0);
1300
1301 if (c->discard.file == QFILE_NULL)
1302 c->discard = qir_uniform_f(c, 0.0);
1303
1304 switch (c->fs_key->alpha_test_func) {
1305 case PIPE_FUNC_NEVER:
1306 c->discard = qir_uniform_f(c, 1.0);
1307 break;
1308 case PIPE_FUNC_ALWAYS:
1309 break;
1310 case PIPE_FUNC_EQUAL:
1311 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1312 c->discard = qir_SEL_X_Y_ZS(c, c->discard,
1313 qir_uniform_f(c, 1.0));
1314 break;
1315 case PIPE_FUNC_NOTEQUAL:
1316 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1317 c->discard = qir_SEL_X_Y_ZC(c, c->discard,
1318 qir_uniform_f(c, 1.0));
1319 break;
1320 case PIPE_FUNC_GREATER:
1321 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1322 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1323 qir_uniform_f(c, 1.0));
1324 break;
1325 case PIPE_FUNC_GEQUAL:
1326 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1327 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1328 qir_uniform_f(c, 1.0));
1329 break;
1330 case PIPE_FUNC_LESS:
1331 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1332 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1333 qir_uniform_f(c, 1.0));
1334 break;
1335 case PIPE_FUNC_LEQUAL:
1336 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1337 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1338 qir_uniform_f(c, 1.0));
1339 break;
1340 }
1341 }
1342
1343 static void
1344 emit_frag_end(struct vc4_compile *c)
1345 {
1346 alpha_test_discard(c);
1347
1348 enum pipe_format color_format = c->fs_key->color_format;
1349 const uint8_t *format_swiz = vc4_get_format_swizzle(color_format);
1350 struct qreg tlb_read_color[4] = { c->undef, c->undef, c->undef, c->undef };
1351 struct qreg dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1352 if (c->fs_key->blend.blend_enable ||
1353 c->fs_key->blend.colormask != 0xf) {
1354 struct qreg r4 = qir_TLB_COLOR_READ(c);
1355 for (int i = 0; i < 4; i++)
1356 tlb_read_color[i] = qir_R4_UNPACK(c, r4, i);
1357 for (int i = 0; i < 4; i++)
1358 dst_color[i] = get_swizzled_channel(c,
1359 tlb_read_color,
1360 format_swiz[i]);
1361 }
1362
1363 struct qreg blend_color[4];
1364 struct qreg undef_array[4] = {
1365 c->undef, c->undef, c->undef, c->undef
1366 };
1367 vc4_blend(c, blend_color, dst_color,
1368 (c->output_color_index != -1 ?
1369 c->outputs + c->output_color_index :
1370 undef_array));
1371
1372 /* If the bit isn't set in the color mask, then just return the
1373 * original dst color, instead.
1374 */
1375 for (int i = 0; i < 4; i++) {
1376 if (!(c->fs_key->blend.colormask & (1 << i))) {
1377 blend_color[i] = dst_color[i];
1378 }
1379 }
1380
1381 /* Debug: Sometimes you're getting a black output and just want to see
1382 * if the FS is getting executed at all. Spam magenta into the color
1383 * output.
1384 */
1385 if (0) {
1386 blend_color[0] = qir_uniform_f(c, 1.0);
1387 blend_color[1] = qir_uniform_f(c, 0.0);
1388 blend_color[2] = qir_uniform_f(c, 1.0);
1389 blend_color[3] = qir_uniform_f(c, 0.5);
1390 }
1391
1392 struct qreg swizzled_outputs[4];
1393 for (int i = 0; i < 4; i++) {
1394 swizzled_outputs[i] = get_swizzled_channel(c, blend_color,
1395 format_swiz[i]);
1396 }
1397
1398 if (c->discard.file != QFILE_NULL)
1399 qir_TLB_DISCARD_SETUP(c, c->discard);
1400
1401 if (c->fs_key->stencil_enabled) {
1402 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 0));
1403 if (c->fs_key->stencil_twoside) {
1404 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 1));
1405 }
1406 if (c->fs_key->stencil_full_writemasks) {
1407 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 2));
1408 }
1409 }
1410
1411 if (c->fs_key->depth_enabled) {
1412 struct qreg z;
1413 if (c->output_position_index != -1) {
1414 z = qir_FTOI(c, qir_FMUL(c, c->outputs[c->output_position_index + 2],
1415 qir_uniform_f(c, 0xffffff)));
1416 } else {
1417 z = qir_FRAG_Z(c);
1418 }
1419 qir_TLB_Z_WRITE(c, z);
1420 }
1421
1422 bool color_written = false;
1423 for (int i = 0; i < 4; i++) {
1424 if (swizzled_outputs[i].file != QFILE_NULL)
1425 color_written = true;
1426 }
1427
1428 struct qreg packed_color;
1429 if (color_written) {
1430 /* Fill in any undefined colors. The simulator will assertion
1431 * fail if we read something that wasn't written, and I don't
1432 * know what hardware does.
1433 */
1434 for (int i = 0; i < 4; i++) {
1435 if (swizzled_outputs[i].file == QFILE_NULL)
1436 swizzled_outputs[i] = qir_uniform_f(c, 0.0);
1437 }
1438 packed_color = qir_get_temp(c);
1439 qir_emit(c, qir_inst4(QOP_PACK_COLORS, packed_color,
1440 swizzled_outputs[0],
1441 swizzled_outputs[1],
1442 swizzled_outputs[2],
1443 swizzled_outputs[3]));
1444 } else {
1445 packed_color = qir_uniform_ui(c, 0);
1446 }
1447
1448 qir_emit(c, qir_inst(QOP_TLB_COLOR_WRITE, c->undef,
1449 packed_color, c->undef));
1450 }
1451
1452 static void
1453 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1454 {
1455 struct qreg xyi[2];
1456
1457 for (int i = 0; i < 2; i++) {
1458 struct qreg scale =
1459 add_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1460
1461 xyi[i] = qir_FTOI(c, qir_FMUL(c,
1462 qir_FMUL(c,
1463 c->outputs[i],
1464 scale),
1465 rcp_w));
1466 }
1467
1468 qir_VPM_WRITE(c, qir_PACK_SCALED(c, xyi[0], xyi[1]));
1469 }
1470
1471 static void
1472 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1473 {
1474 struct qreg zscale = add_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1475 struct qreg zoffset = add_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1476
1477 qir_VPM_WRITE(c, qir_FMUL(c, qir_FADD(c, qir_FMUL(c,
1478 c->outputs[2],
1479 zscale),
1480 zoffset),
1481 rcp_w));
1482 }
1483
1484 static void
1485 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1486 {
1487 qir_VPM_WRITE(c, rcp_w);
1488 }
1489
1490 static void
1491 emit_point_size_write(struct vc4_compile *c)
1492 {
1493 struct qreg point_size;
1494
1495 if (c->output_point_size_index)
1496 point_size = c->outputs[c->output_point_size_index + 3];
1497 else
1498 point_size = qir_uniform_f(c, 1.0);
1499
1500 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1501 * BCM21553).
1502 */
1503 point_size = qir_FMAX(c, point_size, qir_uniform_f(c, .125));
1504
1505 qir_VPM_WRITE(c, point_size);
1506 }
1507
1508 static void
1509 emit_vert_end(struct vc4_compile *c)
1510 {
1511 struct qreg rcp_w = qir_RCP(c, c->outputs[3]);
1512
1513 emit_scaled_viewport_write(c, rcp_w);
1514 emit_zs_write(c, rcp_w);
1515 emit_rcp_wc_write(c, rcp_w);
1516 if (c->vs_key->per_vertex_point_size)
1517 emit_point_size_write(c);
1518
1519 for (int i = 4; i < c->num_outputs; i++) {
1520 qir_VPM_WRITE(c, c->outputs[i]);
1521 }
1522 }
1523
1524 static void
1525 emit_coord_end(struct vc4_compile *c)
1526 {
1527 struct qreg rcp_w = qir_RCP(c, c->outputs[3]);
1528
1529 for (int i = 0; i < 4; i++)
1530 qir_VPM_WRITE(c, c->outputs[i]);
1531
1532 emit_scaled_viewport_write(c, rcp_w);
1533 emit_zs_write(c, rcp_w);
1534 emit_rcp_wc_write(c, rcp_w);
1535 if (c->vs_key->per_vertex_point_size)
1536 emit_point_size_write(c);
1537 }
1538
1539 static struct vc4_compile *
1540 vc4_shader_tgsi_to_qir(struct vc4_context *vc4,
1541 struct vc4_compiled_shader *shader, enum qstage stage,
1542 struct vc4_key *key)
1543 {
1544 struct vc4_compile *c = qir_compile_init();
1545 int ret;
1546
1547 c->stage = stage;
1548
1549 c->uniform_data = ralloc_array(c, uint32_t, 1024);
1550 c->uniform_contents = ralloc_array(c, enum quniform_contents, 1024);
1551
1552 c->shader_state = key->shader_state;
1553 ret = tgsi_parse_init(&c->parser, c->shader_state->tokens);
1554 assert(ret == TGSI_PARSE_OK);
1555
1556 if (vc4_debug & VC4_DEBUG_TGSI) {
1557 fprintf(stderr, "TGSI:\n");
1558 tgsi_dump(c->shader_state->tokens, 0);
1559 }
1560
1561 c->key = key;
1562 switch (stage) {
1563 case QSTAGE_FRAG:
1564 c->fs_key = (struct vc4_fs_key *)key;
1565 if (c->fs_key->is_points) {
1566 c->point_x = emit_fragment_varying(c, 0);
1567 c->point_y = emit_fragment_varying(c, 0);
1568 } else if (c->fs_key->is_lines) {
1569 c->line_x = emit_fragment_varying(c, 0);
1570 }
1571 break;
1572 case QSTAGE_VERT:
1573 c->vs_key = (struct vc4_vs_key *)key;
1574 break;
1575 case QSTAGE_COORD:
1576 c->vs_key = (struct vc4_vs_key *)key;
1577 break;
1578 }
1579
1580 while (!tgsi_parse_end_of_tokens(&c->parser)) {
1581 tgsi_parse_token(&c->parser);
1582
1583 switch (c->parser.FullToken.Token.Type) {
1584 case TGSI_TOKEN_TYPE_DECLARATION:
1585 emit_tgsi_declaration(c,
1586 &c->parser.FullToken.FullDeclaration);
1587 break;
1588
1589 case TGSI_TOKEN_TYPE_INSTRUCTION:
1590 emit_tgsi_instruction(c,
1591 &c->parser.FullToken.FullInstruction);
1592 break;
1593
1594 case TGSI_TOKEN_TYPE_IMMEDIATE:
1595 parse_tgsi_immediate(c,
1596 &c->parser.FullToken.FullImmediate);
1597 break;
1598 }
1599 }
1600
1601 switch (stage) {
1602 case QSTAGE_FRAG:
1603 emit_frag_end(c);
1604 break;
1605 case QSTAGE_VERT:
1606 emit_vert_end(c);
1607 break;
1608 case QSTAGE_COORD:
1609 emit_coord_end(c);
1610 break;
1611 }
1612
1613 tgsi_parse_free(&c->parser);
1614
1615 qir_optimize(c);
1616
1617 if (vc4_debug & VC4_DEBUG_QIR) {
1618 fprintf(stderr, "QIR:\n");
1619 qir_dump(c);
1620 }
1621 qir_reorder_uniforms(c);
1622 vc4_generate_code(vc4, c);
1623
1624 if (vc4_debug & VC4_DEBUG_SHADERDB) {
1625 fprintf(stderr, "SHADER-DB: %s: %d instructions\n",
1626 qir_get_stage_name(c->stage), c->qpu_inst_count);
1627 fprintf(stderr, "SHADER-DB: %s: %d uniforms\n",
1628 qir_get_stage_name(c->stage), c->num_uniforms);
1629 }
1630
1631 return c;
1632 }
1633
1634 static void *
1635 vc4_shader_state_create(struct pipe_context *pctx,
1636 const struct pipe_shader_state *cso)
1637 {
1638 struct pipe_shader_state *so = CALLOC_STRUCT(pipe_shader_state);
1639 if (!so)
1640 return NULL;
1641
1642 so->tokens = tgsi_dup_tokens(cso->tokens);
1643
1644 return so;
1645 }
1646
1647 static void
1648 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
1649 int shader_index,
1650 struct vc4_compile *c)
1651 {
1652 int count = c->num_uniforms;
1653 struct vc4_shader_uniform_info *uinfo = &shader->uniforms[shader_index];
1654
1655 uinfo->count = count;
1656 uinfo->data = malloc(count * sizeof(*uinfo->data));
1657 memcpy(uinfo->data, c->uniform_data,
1658 count * sizeof(*uinfo->data));
1659 uinfo->contents = malloc(count * sizeof(*uinfo->contents));
1660 memcpy(uinfo->contents, c->uniform_contents,
1661 count * sizeof(*uinfo->contents));
1662 uinfo->num_texture_samples = c->num_texture_samples;
1663 }
1664
1665 static void
1666 vc4_fs_compile(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1667 struct vc4_fs_key *key)
1668 {
1669 struct vc4_compile *c = vc4_shader_tgsi_to_qir(vc4, shader,
1670 QSTAGE_FRAG,
1671 &key->base);
1672 shader->num_inputs = c->num_inputs;
1673 shader->color_inputs = c->color_inputs;
1674 copy_uniform_state_to_shader(shader, 0, c);
1675 shader->bo = vc4_bo_alloc_mem(vc4->screen, c->qpu_insts,
1676 c->qpu_inst_count * sizeof(uint64_t),
1677 "fs_code");
1678
1679 qir_compile_destroy(c);
1680 }
1681
1682 static void
1683 vc4_vs_compile(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1684 struct vc4_vs_key *key)
1685 {
1686 struct vc4_compile *vs_c = vc4_shader_tgsi_to_qir(vc4, shader,
1687 QSTAGE_VERT,
1688 &key->base);
1689 copy_uniform_state_to_shader(shader, 0, vs_c);
1690
1691 struct vc4_compile *cs_c = vc4_shader_tgsi_to_qir(vc4, shader,
1692 QSTAGE_COORD,
1693 &key->base);
1694 copy_uniform_state_to_shader(shader, 1, cs_c);
1695
1696 uint32_t vs_size = vs_c->qpu_inst_count * sizeof(uint64_t);
1697 uint32_t cs_size = cs_c->qpu_inst_count * sizeof(uint64_t);
1698 shader->coord_shader_offset = vs_size; /* XXX: alignment? */
1699 shader->bo = vc4_bo_alloc(vc4->screen,
1700 shader->coord_shader_offset + cs_size,
1701 "vs_code");
1702
1703 void *map = vc4_bo_map(shader->bo);
1704 memcpy(map, vs_c->qpu_insts, vs_size);
1705 memcpy(map + shader->coord_shader_offset,
1706 cs_c->qpu_insts, cs_size);
1707
1708 qir_compile_destroy(vs_c);
1709 qir_compile_destroy(cs_c);
1710 }
1711
1712 static void
1713 vc4_setup_shared_key(struct vc4_key *key, struct vc4_texture_stateobj *texstate)
1714 {
1715 for (int i = 0; i < texstate->num_textures; i++) {
1716 struct pipe_sampler_view *sampler = texstate->textures[i];
1717 struct pipe_sampler_state *sampler_state =
1718 texstate->samplers[i];
1719
1720 if (sampler) {
1721 struct pipe_resource *prsc = sampler->texture;
1722 key->tex[i].format = prsc->format;
1723 key->tex[i].swizzle[0] = sampler->swizzle_r;
1724 key->tex[i].swizzle[1] = sampler->swizzle_g;
1725 key->tex[i].swizzle[2] = sampler->swizzle_b;
1726 key->tex[i].swizzle[3] = sampler->swizzle_a;
1727 key->tex[i].compare_mode = sampler_state->compare_mode;
1728 key->tex[i].compare_func = sampler_state->compare_func;
1729 key->tex[i].wrap_s = sampler_state->wrap_s;
1730 key->tex[i].wrap_t = sampler_state->wrap_t;
1731 }
1732 }
1733 }
1734
1735 static void
1736 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
1737 {
1738 struct vc4_fs_key local_key;
1739 struct vc4_fs_key *key = &local_key;
1740
1741 memset(key, 0, sizeof(*key));
1742 vc4_setup_shared_key(&key->base, &vc4->fragtex);
1743 key->base.shader_state = vc4->prog.bind_fs;
1744 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
1745 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
1746 prim_mode <= PIPE_PRIM_LINE_STRIP);
1747 key->blend = vc4->blend->rt[0];
1748
1749 if (vc4->framebuffer.cbufs[0])
1750 key->color_format = vc4->framebuffer.cbufs[0]->format;
1751
1752 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
1753 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
1754 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
1755 key->depth_enabled = (vc4->zsa->base.depth.enabled ||
1756 key->stencil_enabled);
1757 if (vc4->zsa->base.alpha.enabled) {
1758 key->alpha_test = true;
1759 key->alpha_test_func = vc4->zsa->base.alpha.func;
1760 }
1761
1762 if (key->is_points) {
1763 key->point_sprite_mask =
1764 vc4->rasterizer->base.sprite_coord_enable;
1765 key->point_coord_upper_left =
1766 (vc4->rasterizer->base.sprite_coord_mode ==
1767 PIPE_SPRITE_COORD_UPPER_LEFT);
1768 }
1769
1770 vc4->prog.fs = util_hash_table_get(vc4->fs_cache, key);
1771 if (vc4->prog.fs)
1772 return;
1773
1774 key = malloc(sizeof(*key));
1775 memcpy(key, &local_key, sizeof(*key));
1776
1777 struct vc4_compiled_shader *shader = CALLOC_STRUCT(vc4_compiled_shader);
1778 vc4_fs_compile(vc4, shader, key);
1779 util_hash_table_set(vc4->fs_cache, key, shader);
1780
1781 if (vc4->rasterizer->base.flatshade &&
1782 vc4->prog.fs &&
1783 vc4->prog.fs->color_inputs != shader->color_inputs) {
1784 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
1785 }
1786
1787 vc4->prog.fs = shader;
1788 }
1789
1790 static void
1791 vc4_update_compiled_vs(struct vc4_context *vc4, uint8_t prim_mode)
1792 {
1793 struct vc4_vs_key local_key;
1794 struct vc4_vs_key *key = &local_key;
1795
1796 memset(key, 0, sizeof(*key));
1797 vc4_setup_shared_key(&key->base, &vc4->verttex);
1798 key->base.shader_state = vc4->prog.bind_vs;
1799
1800 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
1801 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
1802
1803 key->per_vertex_point_size =
1804 (prim_mode == PIPE_PRIM_POINTS &&
1805 vc4->rasterizer->base.point_size_per_vertex);
1806
1807 vc4->prog.vs = util_hash_table_get(vc4->vs_cache, key);
1808 if (vc4->prog.vs)
1809 return;
1810
1811 key = malloc(sizeof(*key));
1812 memcpy(key, &local_key, sizeof(*key));
1813
1814 struct vc4_compiled_shader *shader = CALLOC_STRUCT(vc4_compiled_shader);
1815 vc4_vs_compile(vc4, shader, key);
1816 util_hash_table_set(vc4->vs_cache, key, shader);
1817
1818 vc4->prog.vs = shader;
1819 }
1820
1821 void
1822 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
1823 {
1824 vc4_update_compiled_fs(vc4, prim_mode);
1825 vc4_update_compiled_vs(vc4, prim_mode);
1826 }
1827
1828 static unsigned
1829 fs_cache_hash(void *key)
1830 {
1831 return util_hash_crc32(key, sizeof(struct vc4_fs_key));
1832 }
1833
1834 static unsigned
1835 vs_cache_hash(void *key)
1836 {
1837 return util_hash_crc32(key, sizeof(struct vc4_vs_key));
1838 }
1839
1840 static int
1841 fs_cache_compare(void *key1, void *key2)
1842 {
1843 return memcmp(key1, key2, sizeof(struct vc4_fs_key));
1844 }
1845
1846 static int
1847 vs_cache_compare(void *key1, void *key2)
1848 {
1849 return memcmp(key1, key2, sizeof(struct vc4_vs_key));
1850 }
1851
1852 struct delete_state {
1853 struct vc4_context *vc4;
1854 struct pipe_shader_state *shader_state;
1855 };
1856
1857 static enum pipe_error
1858 fs_delete_from_cache(void *in_key, void *in_value, void *data)
1859 {
1860 struct delete_state *del = data;
1861 struct vc4_fs_key *key = in_key;
1862 struct vc4_compiled_shader *shader = in_value;
1863
1864 if (key->base.shader_state == data) {
1865 util_hash_table_remove(del->vc4->fs_cache, key);
1866 vc4_bo_unreference(&shader->bo);
1867 free(shader);
1868 }
1869
1870 return 0;
1871 }
1872
1873 static enum pipe_error
1874 vs_delete_from_cache(void *in_key, void *in_value, void *data)
1875 {
1876 struct delete_state *del = data;
1877 struct vc4_vs_key *key = in_key;
1878 struct vc4_compiled_shader *shader = in_value;
1879
1880 if (key->base.shader_state == data) {
1881 util_hash_table_remove(del->vc4->vs_cache, key);
1882 vc4_bo_unreference(&shader->bo);
1883 free(shader);
1884 }
1885
1886 return 0;
1887 }
1888
1889 static void
1890 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
1891 {
1892 struct vc4_context *vc4 = vc4_context(pctx);
1893 struct pipe_shader_state *so = hwcso;
1894 struct delete_state del;
1895
1896 del.vc4 = vc4;
1897 del.shader_state = so;
1898 util_hash_table_foreach(vc4->fs_cache, fs_delete_from_cache, &del);
1899 util_hash_table_foreach(vc4->vs_cache, vs_delete_from_cache, &del);
1900
1901 free((void *)so->tokens);
1902 free(so);
1903 }
1904
1905 static uint32_t translate_wrap(uint32_t p_wrap, bool using_nearest)
1906 {
1907 switch (p_wrap) {
1908 case PIPE_TEX_WRAP_REPEAT:
1909 return 0;
1910 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1911 return 1;
1912 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1913 return 2;
1914 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1915 return 3;
1916 case PIPE_TEX_WRAP_CLAMP:
1917 return (using_nearest ? 1 : 3);
1918 default:
1919 fprintf(stderr, "Unknown wrap mode %d\n", p_wrap);
1920 assert(!"not reached");
1921 return 0;
1922 }
1923 }
1924
1925 static void
1926 write_texture_p0(struct vc4_context *vc4,
1927 struct vc4_texture_stateobj *texstate,
1928 uint32_t unit)
1929 {
1930 struct pipe_sampler_view *texture = texstate->textures[unit];
1931 struct vc4_resource *rsc = vc4_resource(texture->texture);
1932
1933 bool is_cube = texture->target == PIPE_TEXTURE_CUBE;
1934
1935 cl_reloc(vc4, &vc4->uniforms, rsc->bo,
1936 rsc->slices[0].offset | texture->u.tex.last_level |
1937 is_cube << 9 |
1938 ((rsc->vc4_format & 7) << 4));
1939 }
1940
1941 static void
1942 write_texture_p1(struct vc4_context *vc4,
1943 struct vc4_texture_stateobj *texstate,
1944 uint32_t unit)
1945 {
1946 struct pipe_sampler_view *texture = texstate->textures[unit];
1947 struct vc4_resource *rsc = vc4_resource(texture->texture);
1948 struct pipe_sampler_state *sampler = texstate->samplers[unit];
1949 static const uint32_t mipfilter_map[] = {
1950 [PIPE_TEX_MIPFILTER_NEAREST] = 2,
1951 [PIPE_TEX_MIPFILTER_LINEAR] = 4,
1952 [PIPE_TEX_MIPFILTER_NONE] = 0
1953 };
1954 static const uint32_t imgfilter_map[] = {
1955 [PIPE_TEX_FILTER_NEAREST] = 1,
1956 [PIPE_TEX_FILTER_LINEAR] = 0,
1957 };
1958
1959 bool either_nearest =
1960 (sampler->mag_img_filter == PIPE_TEX_MIPFILTER_NEAREST ||
1961 sampler->min_img_filter == PIPE_TEX_MIPFILTER_NEAREST);
1962
1963 cl_u32(&vc4->uniforms,
1964 ((rsc->vc4_format >> 4) << 31) |
1965 (texture->texture->height0 << 20) |
1966 (texture->texture->width0 << 8) |
1967 (imgfilter_map[sampler->mag_img_filter] << 7) |
1968 ((imgfilter_map[sampler->min_img_filter] +
1969 mipfilter_map[sampler->min_mip_filter]) << 4) |
1970 (translate_wrap(sampler->wrap_t, either_nearest) << 2) |
1971 (translate_wrap(sampler->wrap_s, either_nearest) << 0));
1972 }
1973
1974 static void
1975 write_texture_p2(struct vc4_context *vc4,
1976 struct vc4_texture_stateobj *texstate,
1977 uint32_t unit)
1978 {
1979 struct pipe_sampler_view *texture = texstate->textures[unit];
1980 struct vc4_resource *rsc = vc4_resource(texture->texture);
1981
1982 cl_u32(&vc4->uniforms, (1 << 30) | rsc->cube_map_stride);
1983 }
1984
1985
1986 #define SWIZ(x,y,z,w) { \
1987 UTIL_FORMAT_SWIZZLE_##x, \
1988 UTIL_FORMAT_SWIZZLE_##y, \
1989 UTIL_FORMAT_SWIZZLE_##z, \
1990 UTIL_FORMAT_SWIZZLE_##w \
1991 }
1992
1993 static void
1994 write_texture_border_color(struct vc4_context *vc4,
1995 struct vc4_texture_stateobj *texstate,
1996 uint32_t unit)
1997 {
1998 struct pipe_sampler_state *sampler = texstate->samplers[unit];
1999 struct pipe_sampler_view *texture = texstate->textures[unit];
2000 struct vc4_resource *rsc = vc4_resource(texture->texture);
2001 union util_color uc;
2002
2003 const struct util_format_description *tex_format_desc =
2004 util_format_description(texture->format);
2005
2006 /* Turn the border color into the layout of channels that it would
2007 * have when stored as texture contents.
2008 */
2009 float storage_color[4];
2010 util_format_unswizzle_4f(storage_color,
2011 sampler->border_color.f,
2012 tex_format_desc->swizzle);
2013
2014 /* Now, pack so that when the vc4_format-sampled texture contents are
2015 * replaced with our border color, the vc4_get_format_swizzle()
2016 * swizzling will get the right channels.
2017 */
2018 if (util_format_is_depth_or_stencil(texture->format)) {
2019 uc.ui[0] = util_pack_z(PIPE_FORMAT_Z24X8_UNORM,
2020 sampler->border_color.f[0]) << 8;
2021 } else {
2022 switch (rsc->vc4_format) {
2023 default:
2024 case VC4_TEXTURE_TYPE_RGBA8888:
2025 util_pack_color(storage_color,
2026 PIPE_FORMAT_R8G8B8A8_UNORM, &uc);
2027 break;
2028 case VC4_TEXTURE_TYPE_RGBA4444:
2029 util_pack_color(storage_color,
2030 PIPE_FORMAT_A8B8G8R8_UNORM, &uc);
2031 break;
2032 case VC4_TEXTURE_TYPE_RGB565:
2033 util_pack_color(storage_color,
2034 PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
2035 break;
2036 case VC4_TEXTURE_TYPE_ALPHA:
2037 uc.ui[0] = float_to_ubyte(storage_color[0]) << 24;
2038 break;
2039 case VC4_TEXTURE_TYPE_LUMALPHA:
2040 uc.ui[0] = ((float_to_ubyte(storage_color[1]) << 24) |
2041 (float_to_ubyte(storage_color[0]) << 0));
2042 break;
2043 }
2044 }
2045
2046 cl_u32(&vc4->uniforms, uc.ui[0]);
2047 }
2048
2049 static uint32_t
2050 get_texrect_scale(struct vc4_texture_stateobj *texstate,
2051 enum quniform_contents contents,
2052 uint32_t data)
2053 {
2054 struct pipe_sampler_view *texture = texstate->textures[data];
2055 uint32_t dim;
2056
2057 if (contents == QUNIFORM_TEXRECT_SCALE_X)
2058 dim = texture->texture->width0;
2059 else
2060 dim = texture->texture->height0;
2061
2062 return fui(1.0f / dim);
2063 }
2064
2065 void
2066 vc4_write_uniforms(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
2067 struct vc4_constbuf_stateobj *cb,
2068 struct vc4_texture_stateobj *texstate,
2069 int shader_index)
2070 {
2071 struct vc4_shader_uniform_info *uinfo = &shader->uniforms[shader_index];
2072 const uint32_t *gallium_uniforms = cb->cb[0].user_buffer;
2073
2074 cl_start_shader_reloc(&vc4->uniforms, uinfo->num_texture_samples);
2075
2076 for (int i = 0; i < uinfo->count; i++) {
2077
2078 switch (uinfo->contents[i]) {
2079 case QUNIFORM_CONSTANT:
2080 cl_u32(&vc4->uniforms, uinfo->data[i]);
2081 break;
2082 case QUNIFORM_UNIFORM:
2083 cl_u32(&vc4->uniforms,
2084 gallium_uniforms[uinfo->data[i]]);
2085 break;
2086 case QUNIFORM_VIEWPORT_X_SCALE:
2087 cl_f(&vc4->uniforms, vc4->viewport.scale[0] * 16.0f);
2088 break;
2089 case QUNIFORM_VIEWPORT_Y_SCALE:
2090 cl_f(&vc4->uniforms, vc4->viewport.scale[1] * 16.0f);
2091 break;
2092
2093 case QUNIFORM_VIEWPORT_Z_OFFSET:
2094 cl_f(&vc4->uniforms, vc4->viewport.translate[2]);
2095 break;
2096 case QUNIFORM_VIEWPORT_Z_SCALE:
2097 cl_f(&vc4->uniforms, vc4->viewport.scale[2]);
2098 break;
2099
2100 case QUNIFORM_TEXTURE_CONFIG_P0:
2101 write_texture_p0(vc4, texstate, uinfo->data[i]);
2102 break;
2103
2104 case QUNIFORM_TEXTURE_CONFIG_P1:
2105 write_texture_p1(vc4, texstate, uinfo->data[i]);
2106 break;
2107
2108 case QUNIFORM_TEXTURE_CONFIG_P2:
2109 write_texture_p2(vc4, texstate, uinfo->data[i]);
2110 break;
2111
2112 case QUNIFORM_TEXTURE_BORDER_COLOR:
2113 write_texture_border_color(vc4, texstate, uinfo->data[i]);
2114 break;
2115
2116 case QUNIFORM_TEXRECT_SCALE_X:
2117 case QUNIFORM_TEXRECT_SCALE_Y:
2118 cl_u32(&vc4->uniforms,
2119 get_texrect_scale(texstate,
2120 uinfo->contents[i],
2121 uinfo->data[i]));
2122 break;
2123
2124 case QUNIFORM_BLEND_CONST_COLOR:
2125 cl_f(&vc4->uniforms,
2126 vc4->blend_color.color[uinfo->data[i]]);
2127 break;
2128
2129 case QUNIFORM_STENCIL:
2130 cl_u32(&vc4->uniforms,
2131 vc4->zsa->stencil_uniforms[uinfo->data[i]] |
2132 (uinfo->data[i] <= 1 ?
2133 (vc4->stencil_ref.ref_value[uinfo->data[i]] << 8) :
2134 0));
2135 break;
2136
2137 case QUNIFORM_ALPHA_REF:
2138 cl_f(&vc4->uniforms, vc4->zsa->base.alpha.ref_value);
2139 break;
2140 }
2141 #if 0
2142 uint32_t written_val = *(uint32_t *)(vc4->uniforms.next - 4);
2143 fprintf(stderr, "%p/%d: %d: 0x%08x (%f)\n",
2144 shader, shader_index, i, written_val, uif(written_val));
2145 #endif
2146 }
2147 }
2148
2149 static void
2150 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
2151 {
2152 struct vc4_context *vc4 = vc4_context(pctx);
2153 vc4->prog.bind_fs = hwcso;
2154 vc4->prog.dirty |= VC4_SHADER_DIRTY_FP;
2155 vc4->dirty |= VC4_DIRTY_PROG;
2156 }
2157
2158 static void
2159 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
2160 {
2161 struct vc4_context *vc4 = vc4_context(pctx);
2162 vc4->prog.bind_vs = hwcso;
2163 vc4->prog.dirty |= VC4_SHADER_DIRTY_VP;
2164 vc4->dirty |= VC4_DIRTY_PROG;
2165 }
2166
2167 void
2168 vc4_program_init(struct pipe_context *pctx)
2169 {
2170 struct vc4_context *vc4 = vc4_context(pctx);
2171
2172 pctx->create_vs_state = vc4_shader_state_create;
2173 pctx->delete_vs_state = vc4_shader_state_delete;
2174
2175 pctx->create_fs_state = vc4_shader_state_create;
2176 pctx->delete_fs_state = vc4_shader_state_delete;
2177
2178 pctx->bind_fs_state = vc4_fp_state_bind;
2179 pctx->bind_vs_state = vc4_vp_state_bind;
2180
2181 vc4->fs_cache = util_hash_table_create(fs_cache_hash, fs_cache_compare);
2182 vc4->vs_cache = util_hash_table_create(vs_cache_hash, vs_cache_compare);
2183 }