2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "util/u_format.h"
27 #include "util/u_hash.h"
28 #include "util/u_math.h"
29 #include "util/u_memory.h"
30 #include "util/ralloc.h"
31 #include "util/hash_table.h"
32 #include "tgsi/tgsi_dump.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "compiler/nir/nir.h"
35 #include "compiler/nir/nir_builder.h"
36 #include "nir/tgsi_to_nir.h"
37 #include "vc4_context.h"
40 #ifdef USE_VC4_SIMULATOR
41 #include "simpenrose/simpenrose.h"
45 ntq_get_src(struct vc4_compile
*c
, nir_src src
, int i
);
48 resize_qreg_array(struct vc4_compile
*c
,
53 if (*size
>= decl_size
)
56 uint32_t old_size
= *size
;
57 *size
= MAX2(*size
* 2, decl_size
);
58 *regs
= reralloc(c
, *regs
, struct qreg
, *size
);
60 fprintf(stderr
, "Malloc failure\n");
64 for (uint32_t i
= old_size
; i
< *size
; i
++)
65 (*regs
)[i
] = c
->undef
;
69 indirect_uniform_load(struct vc4_compile
*c
, nir_intrinsic_instr
*intr
)
71 struct qreg indirect_offset
= ntq_get_src(c
, intr
->src
[0], 0);
72 uint32_t offset
= intr
->const_index
[0];
73 struct vc4_compiler_ubo_range
*range
= NULL
;
75 for (i
= 0; i
< c
->num_uniform_ranges
; i
++) {
76 range
= &c
->ubo_ranges
[i
];
77 if (offset
>= range
->src_offset
&&
78 offset
< range
->src_offset
+ range
->size
) {
82 /* The driver-location-based offset always has to be within a declared
88 range
->dst_offset
= c
->next_ubo_dst_offset
;
89 c
->next_ubo_dst_offset
+= range
->size
;
93 offset
-= range
->src_offset
;
95 /* Adjust for where we stored the TGSI register base. */
96 indirect_offset
= qir_ADD(c
, indirect_offset
,
97 qir_uniform_ui(c
, (range
->dst_offset
+
100 /* Clamp to [0, array size). Note that MIN/MAX are signed. */
101 indirect_offset
= qir_MAX(c
, indirect_offset
, qir_uniform_ui(c
, 0));
102 indirect_offset
= qir_MIN(c
, indirect_offset
,
103 qir_uniform_ui(c
, (range
->dst_offset
+
106 qir_TEX_DIRECT(c
, indirect_offset
, qir_uniform(c
, QUNIFORM_UBO_ADDR
, 0));
107 c
->num_texture_samples
++;
108 return qir_TEX_RESULT(c
);
111 nir_ssa_def
*vc4_nir_get_state_uniform(struct nir_builder
*b
,
112 enum quniform_contents contents
)
114 nir_intrinsic_instr
*intr
=
115 nir_intrinsic_instr_create(b
->shader
,
116 nir_intrinsic_load_uniform
);
117 intr
->const_index
[0] = (VC4_NIR_STATE_UNIFORM_OFFSET
+ contents
) * 4;
118 intr
->num_components
= 1;
119 intr
->src
[0] = nir_src_for_ssa(nir_imm_int(b
, 0));
120 nir_ssa_dest_init(&intr
->instr
, &intr
->dest
, 1, 32, NULL
);
121 nir_builder_instr_insert(b
, &intr
->instr
);
122 return &intr
->dest
.ssa
;
126 vc4_nir_get_swizzled_channel(nir_builder
*b
, nir_ssa_def
**srcs
, int swiz
)
130 case PIPE_SWIZZLE_NONE
:
131 fprintf(stderr
, "warning: unknown swizzle\n");
134 return nir_imm_float(b
, 0.0);
136 return nir_imm_float(b
, 1.0);
146 ntq_init_ssa_def(struct vc4_compile
*c
, nir_ssa_def
*def
)
148 struct qreg
*qregs
= ralloc_array(c
->def_ht
, struct qreg
,
149 def
->num_components
);
150 _mesa_hash_table_insert(c
->def_ht
, def
, qregs
);
155 ntq_get_dest(struct vc4_compile
*c
, nir_dest
*dest
)
158 struct qreg
*qregs
= ntq_init_ssa_def(c
, &dest
->ssa
);
159 for (int i
= 0; i
< dest
->ssa
.num_components
; i
++)
163 nir_register
*reg
= dest
->reg
.reg
;
164 assert(dest
->reg
.base_offset
== 0);
165 assert(reg
->num_array_elems
== 0);
166 struct hash_entry
*entry
=
167 _mesa_hash_table_search(c
->def_ht
, reg
);
173 ntq_get_src(struct vc4_compile
*c
, nir_src src
, int i
)
175 struct hash_entry
*entry
;
177 entry
= _mesa_hash_table_search(c
->def_ht
, src
.ssa
);
178 assert(i
< src
.ssa
->num_components
);
180 nir_register
*reg
= src
.reg
.reg
;
181 entry
= _mesa_hash_table_search(c
->def_ht
, reg
);
182 assert(reg
->num_array_elems
== 0);
183 assert(src
.reg
.base_offset
== 0);
184 assert(i
< reg
->num_components
);
187 struct qreg
*qregs
= entry
->data
;
192 ntq_get_alu_src(struct vc4_compile
*c
, nir_alu_instr
*instr
,
195 assert(util_is_power_of_two(instr
->dest
.write_mask
));
196 unsigned chan
= ffs(instr
->dest
.write_mask
) - 1;
197 struct qreg r
= ntq_get_src(c
, instr
->src
[src
].src
,
198 instr
->src
[src
].swizzle
[chan
]);
200 assert(!instr
->src
[src
].abs
);
201 assert(!instr
->src
[src
].negate
);
206 static inline struct qreg
207 qir_SAT(struct vc4_compile
*c
, struct qreg val
)
210 qir_FMIN(c
, val
, qir_uniform_f(c
, 1.0)),
211 qir_uniform_f(c
, 0.0));
215 ntq_rcp(struct vc4_compile
*c
, struct qreg x
)
217 struct qreg r
= qir_RCP(c
, x
);
219 /* Apply a Newton-Raphson step to improve the accuracy. */
220 r
= qir_FMUL(c
, r
, qir_FSUB(c
,
221 qir_uniform_f(c
, 2.0),
228 ntq_rsq(struct vc4_compile
*c
, struct qreg x
)
230 struct qreg r
= qir_RSQ(c
, x
);
232 /* Apply a Newton-Raphson step to improve the accuracy. */
233 r
= qir_FMUL(c
, r
, qir_FSUB(c
,
234 qir_uniform_f(c
, 1.5),
236 qir_uniform_f(c
, 0.5),
238 qir_FMUL(c
, r
, r
)))));
244 ntq_umul(struct vc4_compile
*c
, struct qreg src0
, struct qreg src1
)
246 struct qreg src0_hi
= qir_SHR(c
, src0
,
247 qir_uniform_ui(c
, 24));
248 struct qreg src1_hi
= qir_SHR(c
, src1
,
249 qir_uniform_ui(c
, 24));
251 struct qreg hilo
= qir_MUL24(c
, src0_hi
, src1
);
252 struct qreg lohi
= qir_MUL24(c
, src0
, src1_hi
);
253 struct qreg lolo
= qir_MUL24(c
, src0
, src1
);
255 return qir_ADD(c
, lolo
, qir_SHL(c
,
256 qir_ADD(c
, hilo
, lohi
),
257 qir_uniform_ui(c
, 24)));
261 ntq_scale_depth_texture(struct vc4_compile
*c
, struct qreg src
)
263 struct qreg depthf
= qir_ITOF(c
, qir_SHR(c
, src
,
264 qir_uniform_ui(c
, 8)));
265 return qir_FMUL(c
, depthf
, qir_uniform_f(c
, 1.0f
/0xffffff));
269 * Emits a lowered TXF_MS from an MSAA texture.
271 * The addressing math has been lowered in NIR, and now we just need to read
275 ntq_emit_txf(struct vc4_compile
*c
, nir_tex_instr
*instr
)
277 uint32_t tile_width
= 32;
278 uint32_t tile_height
= 32;
279 uint32_t tile_size
= (tile_height
* tile_width
*
280 VC4_MAX_SAMPLES
* sizeof(uint32_t));
282 unsigned unit
= instr
->texture_index
;
283 uint32_t w
= align(c
->key
->tex
[unit
].msaa_width
, tile_width
);
284 uint32_t w_tiles
= w
/ tile_width
;
285 uint32_t h
= align(c
->key
->tex
[unit
].msaa_height
, tile_height
);
286 uint32_t h_tiles
= h
/ tile_height
;
287 uint32_t size
= w_tiles
* h_tiles
* tile_size
;
290 assert(instr
->num_srcs
== 1);
291 assert(instr
->src
[0].src_type
== nir_tex_src_coord
);
292 addr
= ntq_get_src(c
, instr
->src
[0].src
, 0);
294 /* Perform the clamping required by kernel validation. */
295 addr
= qir_MAX(c
, addr
, qir_uniform_ui(c
, 0));
296 addr
= qir_MIN(c
, addr
, qir_uniform_ui(c
, size
- 4));
298 qir_TEX_DIRECT(c
, addr
, qir_uniform(c
, QUNIFORM_TEXTURE_MSAA_ADDR
, unit
));
300 struct qreg tex
= qir_TEX_RESULT(c
);
301 c
->num_texture_samples
++;
303 struct qreg
*dest
= ntq_get_dest(c
, &instr
->dest
);
304 enum pipe_format format
= c
->key
->tex
[unit
].format
;
305 if (util_format_is_depth_or_stencil(format
)) {
306 struct qreg scaled
= ntq_scale_depth_texture(c
, tex
);
307 for (int i
= 0; i
< 4; i
++)
310 for (int i
= 0; i
< 4; i
++)
311 dest
[i
] = qir_UNPACK_8_F(c
, tex
, i
);
316 ntq_emit_tex(struct vc4_compile
*c
, nir_tex_instr
*instr
)
318 struct qreg s
, t
, r
, lod
, compare
;
319 bool is_txb
= false, is_txl
= false;
320 unsigned unit
= instr
->texture_index
;
322 if (instr
->op
== nir_texop_txf
) {
323 ntq_emit_txf(c
, instr
);
327 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
328 switch (instr
->src
[i
].src_type
) {
329 case nir_tex_src_coord
:
330 s
= ntq_get_src(c
, instr
->src
[i
].src
, 0);
331 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
)
332 t
= qir_uniform_f(c
, 0.5);
334 t
= ntq_get_src(c
, instr
->src
[i
].src
, 1);
335 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
336 r
= ntq_get_src(c
, instr
->src
[i
].src
, 2);
338 case nir_tex_src_bias
:
339 lod
= ntq_get_src(c
, instr
->src
[i
].src
, 0);
342 case nir_tex_src_lod
:
343 lod
= ntq_get_src(c
, instr
->src
[i
].src
, 0);
346 case nir_tex_src_comparitor
:
347 compare
= ntq_get_src(c
, instr
->src
[i
].src
, 0);
350 unreachable("unknown texture source");
354 struct qreg texture_u
[] = {
355 qir_uniform(c
, QUNIFORM_TEXTURE_CONFIG_P0
, unit
),
356 qir_uniform(c
, QUNIFORM_TEXTURE_CONFIG_P1
, unit
),
357 qir_uniform(c
, QUNIFORM_CONSTANT
, 0),
358 qir_uniform(c
, QUNIFORM_CONSTANT
, 0),
360 uint32_t next_texture_u
= 0;
362 /* There is no native support for GL texture rectangle coordinates, so
363 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
366 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_RECT
) {
368 qir_uniform(c
, QUNIFORM_TEXRECT_SCALE_X
, unit
));
370 qir_uniform(c
, QUNIFORM_TEXRECT_SCALE_Y
, unit
));
373 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
|| is_txl
) {
374 texture_u
[2] = qir_uniform(c
, QUNIFORM_TEXTURE_CONFIG_P2
,
375 unit
| (is_txl
<< 16));
378 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
379 qir_TEX_R(c
, r
, texture_u
[next_texture_u
++]);
380 } else if (c
->key
->tex
[unit
].wrap_s
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
381 c
->key
->tex
[unit
].wrap_s
== PIPE_TEX_WRAP_CLAMP
||
382 c
->key
->tex
[unit
].wrap_t
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
383 c
->key
->tex
[unit
].wrap_t
== PIPE_TEX_WRAP_CLAMP
) {
384 qir_TEX_R(c
, qir_uniform(c
, QUNIFORM_TEXTURE_BORDER_COLOR
, unit
),
385 texture_u
[next_texture_u
++]);
388 if (c
->key
->tex
[unit
].wrap_s
== PIPE_TEX_WRAP_CLAMP
) {
392 if (c
->key
->tex
[unit
].wrap_t
== PIPE_TEX_WRAP_CLAMP
) {
396 qir_TEX_T(c
, t
, texture_u
[next_texture_u
++]);
398 if (is_txl
|| is_txb
)
399 qir_TEX_B(c
, lod
, texture_u
[next_texture_u
++]);
401 qir_TEX_S(c
, s
, texture_u
[next_texture_u
++]);
403 c
->num_texture_samples
++;
404 struct qreg tex
= qir_TEX_RESULT(c
);
406 enum pipe_format format
= c
->key
->tex
[unit
].format
;
408 struct qreg
*dest
= ntq_get_dest(c
, &instr
->dest
);
409 if (util_format_is_depth_or_stencil(format
)) {
410 struct qreg normalized
= ntq_scale_depth_texture(c
, tex
);
411 struct qreg depth_output
;
413 struct qreg u0
= qir_uniform_f(c
, 0.0f
);
414 struct qreg u1
= qir_uniform_f(c
, 1.0f
);
415 if (c
->key
->tex
[unit
].compare_mode
) {
416 switch (c
->key
->tex
[unit
].compare_func
) {
417 case PIPE_FUNC_NEVER
:
418 depth_output
= qir_uniform_f(c
, 0.0f
);
420 case PIPE_FUNC_ALWAYS
:
423 case PIPE_FUNC_EQUAL
:
424 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
425 depth_output
= qir_SEL(c
, QPU_COND_ZS
, u1
, u0
);
427 case PIPE_FUNC_NOTEQUAL
:
428 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
429 depth_output
= qir_SEL(c
, QPU_COND_ZC
, u1
, u0
);
431 case PIPE_FUNC_GREATER
:
432 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
433 depth_output
= qir_SEL(c
, QPU_COND_NC
, u1
, u0
);
435 case PIPE_FUNC_GEQUAL
:
436 qir_SF(c
, qir_FSUB(c
, normalized
, compare
));
437 depth_output
= qir_SEL(c
, QPU_COND_NS
, u1
, u0
);
440 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
441 depth_output
= qir_SEL(c
, QPU_COND_NS
, u1
, u0
);
443 case PIPE_FUNC_LEQUAL
:
444 qir_SF(c
, qir_FSUB(c
, normalized
, compare
));
445 depth_output
= qir_SEL(c
, QPU_COND_NC
, u1
, u0
);
449 depth_output
= normalized
;
452 for (int i
= 0; i
< 4; i
++)
453 dest
[i
] = depth_output
;
455 for (int i
= 0; i
< 4; i
++)
456 dest
[i
] = qir_UNPACK_8_F(c
, tex
, i
);
461 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
465 ntq_ffract(struct vc4_compile
*c
, struct qreg src
)
467 struct qreg trunc
= qir_ITOF(c
, qir_FTOI(c
, src
));
468 struct qreg diff
= qir_FSUB(c
, src
, trunc
);
470 return qir_SEL(c
, QPU_COND_NS
,
471 qir_FADD(c
, diff
, qir_uniform_f(c
, 1.0)), diff
);
475 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
479 ntq_ffloor(struct vc4_compile
*c
, struct qreg src
)
481 struct qreg trunc
= qir_ITOF(c
, qir_FTOI(c
, src
));
483 /* This will be < 0 if we truncated and the truncation was of a value
484 * that was < 0 in the first place.
486 qir_SF(c
, qir_FSUB(c
, src
, trunc
));
488 return qir_SEL(c
, QPU_COND_NS
,
489 qir_FSUB(c
, trunc
, qir_uniform_f(c
, 1.0)), trunc
);
493 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
497 ntq_fceil(struct vc4_compile
*c
, struct qreg src
)
499 struct qreg trunc
= qir_ITOF(c
, qir_FTOI(c
, src
));
501 /* This will be < 0 if we truncated and the truncation was of a value
502 * that was > 0 in the first place.
504 qir_SF(c
, qir_FSUB(c
, trunc
, src
));
506 return qir_SEL(c
, QPU_COND_NS
,
507 qir_FADD(c
, trunc
, qir_uniform_f(c
, 1.0)), trunc
);
511 ntq_fsin(struct vc4_compile
*c
, struct qreg src
)
515 pow(2.0 * M_PI
, 3) / (3 * 2 * 1),
516 -pow(2.0 * M_PI
, 5) / (5 * 4 * 3 * 2 * 1),
517 pow(2.0 * M_PI
, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
518 -pow(2.0 * M_PI
, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
521 struct qreg scaled_x
=
524 qir_uniform_f(c
, 1.0 / (M_PI
* 2.0)));
526 struct qreg x
= qir_FADD(c
,
527 ntq_ffract(c
, scaled_x
),
528 qir_uniform_f(c
, -0.5));
529 struct qreg x2
= qir_FMUL(c
, x
, x
);
530 struct qreg sum
= qir_FMUL(c
, x
, qir_uniform_f(c
, coeff
[0]));
531 for (int i
= 1; i
< ARRAY_SIZE(coeff
); i
++) {
532 x
= qir_FMUL(c
, x
, x2
);
537 qir_uniform_f(c
, coeff
[i
])));
543 ntq_fcos(struct vc4_compile
*c
, struct qreg src
)
547 pow(2.0 * M_PI
, 2) / (2 * 1),
548 -pow(2.0 * M_PI
, 4) / (4 * 3 * 2 * 1),
549 pow(2.0 * M_PI
, 6) / (6 * 5 * 4 * 3 * 2 * 1),
550 -pow(2.0 * M_PI
, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
551 pow(2.0 * M_PI
, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
554 struct qreg scaled_x
=
556 qir_uniform_f(c
, 1.0f
/ (M_PI
* 2.0f
)));
557 struct qreg x_frac
= qir_FADD(c
,
558 ntq_ffract(c
, scaled_x
),
559 qir_uniform_f(c
, -0.5));
561 struct qreg sum
= qir_uniform_f(c
, coeff
[0]);
562 struct qreg x2
= qir_FMUL(c
, x_frac
, x_frac
);
563 struct qreg x
= x2
; /* Current x^2, x^4, or x^6 */
564 for (int i
= 1; i
< ARRAY_SIZE(coeff
); i
++) {
566 x
= qir_FMUL(c
, x
, x2
);
568 struct qreg mul
= qir_FMUL(c
,
570 qir_uniform_f(c
, coeff
[i
]));
574 sum
= qir_FADD(c
, sum
, mul
);
580 ntq_fsign(struct vc4_compile
*c
, struct qreg src
)
582 struct qreg t
= qir_get_temp(c
);
585 qir_MOV_dest(c
, t
, qir_uniform_f(c
, 0.0));
586 qir_MOV_dest(c
, t
, qir_uniform_f(c
, 1.0))->cond
= QPU_COND_ZC
;
587 qir_MOV_dest(c
, t
, qir_uniform_f(c
, -1.0))->cond
= QPU_COND_NS
;
592 emit_vertex_input(struct vc4_compile
*c
, int attr
)
594 enum pipe_format format
= c
->vs_key
->attr_formats
[attr
];
595 uint32_t attr_size
= util_format_get_blocksize(format
);
597 c
->vattr_sizes
[attr
] = align(attr_size
, 4);
598 for (int i
= 0; i
< align(attr_size
, 4) / 4; i
++) {
599 c
->inputs
[attr
* 4 + i
] =
600 qir_MOV(c
, qir_reg(QFILE_VPM
, attr
* 4 + i
));
606 emit_fragcoord_input(struct vc4_compile
*c
, int attr
)
608 c
->inputs
[attr
* 4 + 0] = qir_ITOF(c
, qir_reg(QFILE_FRAG_X
, 0));
609 c
->inputs
[attr
* 4 + 1] = qir_ITOF(c
, qir_reg(QFILE_FRAG_Y
, 0));
610 c
->inputs
[attr
* 4 + 2] =
612 qir_ITOF(c
, qir_FRAG_Z(c
)),
613 qir_uniform_f(c
, 1.0 / 0xffffff));
614 c
->inputs
[attr
* 4 + 3] = qir_RCP(c
, qir_FRAG_W(c
));
618 emit_fragment_varying(struct vc4_compile
*c
, gl_varying_slot slot
,
621 uint32_t i
= c
->num_input_slots
++;
627 if (c
->num_input_slots
>= c
->input_slots_array_size
) {
628 c
->input_slots_array_size
=
629 MAX2(4, c
->input_slots_array_size
* 2);
631 c
->input_slots
= reralloc(c
, c
->input_slots
,
632 struct vc4_varying_slot
,
633 c
->input_slots_array_size
);
636 c
->input_slots
[i
].slot
= slot
;
637 c
->input_slots
[i
].swizzle
= swizzle
;
639 return qir_VARY_ADD_C(c
, qir_FMUL(c
, vary
, qir_FRAG_W(c
)));
643 emit_fragment_input(struct vc4_compile
*c
, int attr
, gl_varying_slot slot
)
645 for (int i
= 0; i
< 4; i
++) {
646 c
->inputs
[attr
* 4 + i
] =
647 emit_fragment_varying(c
, slot
, i
);
653 add_output(struct vc4_compile
*c
,
654 uint32_t decl_offset
,
658 uint32_t old_array_size
= c
->outputs_array_size
;
659 resize_qreg_array(c
, &c
->outputs
, &c
->outputs_array_size
,
662 if (old_array_size
!= c
->outputs_array_size
) {
663 c
->output_slots
= reralloc(c
,
665 struct vc4_varying_slot
,
666 c
->outputs_array_size
);
669 c
->output_slots
[decl_offset
].slot
= slot
;
670 c
->output_slots
[decl_offset
].swizzle
= swizzle
;
674 declare_uniform_range(struct vc4_compile
*c
, uint32_t start
, uint32_t size
)
676 unsigned array_id
= c
->num_uniform_ranges
++;
677 if (array_id
>= c
->ubo_ranges_array_size
) {
678 c
->ubo_ranges_array_size
= MAX2(c
->ubo_ranges_array_size
* 2,
680 c
->ubo_ranges
= reralloc(c
, c
->ubo_ranges
,
681 struct vc4_compiler_ubo_range
,
682 c
->ubo_ranges_array_size
);
685 c
->ubo_ranges
[array_id
].dst_offset
= 0;
686 c
->ubo_ranges
[array_id
].src_offset
= start
;
687 c
->ubo_ranges
[array_id
].size
= size
;
688 c
->ubo_ranges
[array_id
].used
= false;
692 ntq_src_is_only_ssa_def_user(nir_src
*src
)
697 if (!list_empty(&src
->ssa
->if_uses
))
700 return (src
->ssa
->uses
.next
== &src
->use_link
&&
701 src
->ssa
->uses
.next
->next
== &src
->ssa
->uses
);
705 * In general, emits a nir_pack_unorm_4x8 as a series of MOVs with the pack
708 * However, as an optimization, it tries to find the instructions generating
709 * the sources to be packed and just emit the pack flag there, if possible.
712 ntq_emit_pack_unorm_4x8(struct vc4_compile
*c
, nir_alu_instr
*instr
)
714 struct qreg result
= qir_get_temp(c
);
715 struct nir_alu_instr
*vec4
= NULL
;
717 /* If packing from a vec4 op (as expected), identify it so that we can
718 * peek back at what generated its sources.
720 if (instr
->src
[0].src
.is_ssa
&&
721 instr
->src
[0].src
.ssa
->parent_instr
->type
== nir_instr_type_alu
&&
722 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
)->op
==
724 vec4
= nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
727 /* If the pack is replicating the same channel 4 times, use the 8888
728 * pack flag. This is common for blending using the alpha
731 if (instr
->src
[0].swizzle
[0] == instr
->src
[0].swizzle
[1] &&
732 instr
->src
[0].swizzle
[0] == instr
->src
[0].swizzle
[2] &&
733 instr
->src
[0].swizzle
[0] == instr
->src
[0].swizzle
[3]) {
734 struct qreg
*dest
= ntq_get_dest(c
, &instr
->dest
.dest
);
735 *dest
= qir_PACK_8888_F(c
,
736 ntq_get_src(c
, instr
->src
[0].src
,
737 instr
->src
[0].swizzle
[0]));
741 for (int i
= 0; i
< 4; i
++) {
742 int swiz
= instr
->src
[0].swizzle
[i
];
745 src
= ntq_get_src(c
, vec4
->src
[swiz
].src
,
746 vec4
->src
[swiz
].swizzle
[0]);
748 src
= ntq_get_src(c
, instr
->src
[0].src
, swiz
);
752 ntq_src_is_only_ssa_def_user(&vec4
->src
[swiz
].src
) &&
753 src
.file
== QFILE_TEMP
&&
754 c
->defs
[src
.index
] &&
755 qir_is_mul(c
->defs
[src
.index
]) &&
756 !c
->defs
[src
.index
]->dst
.pack
) {
757 struct qinst
*rewrite
= c
->defs
[src
.index
];
758 c
->defs
[src
.index
] = NULL
;
759 rewrite
->dst
= result
;
760 rewrite
->dst
.pack
= QPU_PACK_MUL_8A
+ i
;
764 qir_PACK_8_F(c
, result
, src
, i
);
767 struct qreg
*dest
= ntq_get_dest(c
, &instr
->dest
.dest
);
771 /** Handles sign-extended bitfield extracts for 16 bits. */
773 ntq_emit_ibfe(struct vc4_compile
*c
, struct qreg base
, struct qreg offset
,
776 assert(bits
.file
== QFILE_UNIF
&&
777 c
->uniform_contents
[bits
.index
] == QUNIFORM_CONSTANT
&&
778 c
->uniform_data
[bits
.index
] == 16);
780 assert(offset
.file
== QFILE_UNIF
&&
781 c
->uniform_contents
[offset
.index
] == QUNIFORM_CONSTANT
);
782 int offset_bit
= c
->uniform_data
[offset
.index
];
783 assert(offset_bit
% 16 == 0);
785 return qir_UNPACK_16_I(c
, base
, offset_bit
/ 16);
788 /** Handles unsigned bitfield extracts for 8 bits. */
790 ntq_emit_ubfe(struct vc4_compile
*c
, struct qreg base
, struct qreg offset
,
793 assert(bits
.file
== QFILE_UNIF
&&
794 c
->uniform_contents
[bits
.index
] == QUNIFORM_CONSTANT
&&
795 c
->uniform_data
[bits
.index
] == 8);
797 assert(offset
.file
== QFILE_UNIF
&&
798 c
->uniform_contents
[offset
.index
] == QUNIFORM_CONSTANT
);
799 int offset_bit
= c
->uniform_data
[offset
.index
];
800 assert(offset_bit
% 8 == 0);
802 return qir_UNPACK_8_I(c
, base
, offset_bit
/ 8);
806 * If compare_instr is a valid comparison instruction, emits the
807 * compare_instr's comparison and returns the sel_instr's return value based
808 * on the compare_instr's result.
811 ntq_emit_comparison(struct vc4_compile
*c
, struct qreg
*dest
,
812 nir_alu_instr
*compare_instr
,
813 nir_alu_instr
*sel_instr
)
817 switch (compare_instr
->op
) {
843 struct qreg src0
= ntq_get_alu_src(c
, compare_instr
, 0);
844 struct qreg src1
= ntq_get_alu_src(c
, compare_instr
, 1);
846 unsigned unsized_type
=
847 nir_alu_type_get_base_type(nir_op_infos
[compare_instr
->op
].input_types
[0]);
848 if (unsized_type
== nir_type_float
)
849 qir_SF(c
, qir_FSUB(c
, src0
, src1
));
851 qir_SF(c
, qir_SUB(c
, src0
, src1
));
853 switch (sel_instr
->op
) {
858 *dest
= qir_SEL(c
, cond
,
859 qir_uniform_f(c
, 1.0), qir_uniform_f(c
, 0.0));
863 *dest
= qir_SEL(c
, cond
,
864 ntq_get_alu_src(c
, sel_instr
, 1),
865 ntq_get_alu_src(c
, sel_instr
, 2));
869 *dest
= qir_SEL(c
, cond
,
870 qir_uniform_ui(c
, ~0), qir_uniform_ui(c
, 0));
878 * Attempts to fold a comparison generating a boolean result into the
879 * condition code for selecting between two values, instead of comparing the
880 * boolean result against 0 to generate the condition code.
882 static struct qreg
ntq_emit_bcsel(struct vc4_compile
*c
, nir_alu_instr
*instr
,
885 if (!instr
->src
[0].src
.is_ssa
)
887 nir_alu_instr
*compare
=
888 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
893 if (ntq_emit_comparison(c
, &dest
, compare
, instr
))
898 return qir_SEL(c
, QPU_COND_NS
, src
[1], src
[2]);
902 ntq_emit_alu(struct vc4_compile
*c
, nir_alu_instr
*instr
)
904 /* Vectors are special in that they have non-scalarized writemasks,
905 * and just take the first swizzle channel for each argument in order
906 * into each writemask channel.
908 if (instr
->op
== nir_op_vec2
||
909 instr
->op
== nir_op_vec3
||
910 instr
->op
== nir_op_vec4
) {
912 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
913 srcs
[i
] = ntq_get_src(c
, instr
->src
[i
].src
,
914 instr
->src
[i
].swizzle
[0]);
915 struct qreg
*dest
= ntq_get_dest(c
, &instr
->dest
.dest
);
916 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
921 if (instr
->op
== nir_op_pack_unorm_4x8
) {
922 ntq_emit_pack_unorm_4x8(c
, instr
);
926 if (instr
->op
== nir_op_unpack_unorm_4x8
) {
927 struct qreg src
= ntq_get_src(c
, instr
->src
[0].src
,
928 instr
->src
[0].swizzle
[0]);
929 struct qreg
*dest
= ntq_get_dest(c
, &instr
->dest
.dest
);
930 for (int i
= 0; i
< 4; i
++) {
931 if (instr
->dest
.write_mask
& (1 << i
))
932 dest
[i
] = qir_UNPACK_8_F(c
, src
, i
);
937 /* General case: We can just grab the one used channel per src. */
938 struct qreg src
[nir_op_infos
[instr
->op
].num_inputs
];
939 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
940 src
[i
] = ntq_get_alu_src(c
, instr
, i
);
943 /* Pick the channel to store the output in. */
944 assert(!instr
->dest
.saturate
);
945 struct qreg
*dest
= ntq_get_dest(c
, &instr
->dest
.dest
);
946 assert(util_is_power_of_two(instr
->dest
.write_mask
));
947 dest
+= ffs(instr
->dest
.write_mask
) - 1;
952 *dest
= qir_MOV(c
, src
[0]);
955 *dest
= qir_FMUL(c
, src
[0], src
[1]);
958 *dest
= qir_FADD(c
, src
[0], src
[1]);
961 *dest
= qir_FSUB(c
, src
[0], src
[1]);
964 *dest
= qir_FMIN(c
, src
[0], src
[1]);
967 *dest
= qir_FMAX(c
, src
[0], src
[1]);
972 *dest
= qir_FTOI(c
, src
[0]);
976 *dest
= qir_ITOF(c
, src
[0]);
979 *dest
= qir_AND(c
, src
[0], qir_uniform_f(c
, 1.0));
982 *dest
= qir_AND(c
, src
[0], qir_uniform_ui(c
, 1));
987 *dest
= qir_SEL(c
, QPU_COND_ZC
,
988 qir_uniform_ui(c
, ~0),
989 qir_uniform_ui(c
, 0));
993 *dest
= qir_ADD(c
, src
[0], src
[1]);
996 *dest
= qir_SHR(c
, src
[0], src
[1]);
999 *dest
= qir_SUB(c
, src
[0], src
[1]);
1002 *dest
= qir_ASR(c
, src
[0], src
[1]);
1005 *dest
= qir_SHL(c
, src
[0], src
[1]);
1008 *dest
= qir_MIN(c
, src
[0], src
[1]);
1011 *dest
= qir_MAX(c
, src
[0], src
[1]);
1014 *dest
= qir_AND(c
, src
[0], src
[1]);
1017 *dest
= qir_OR(c
, src
[0], src
[1]);
1020 *dest
= qir_XOR(c
, src
[0], src
[1]);
1023 *dest
= qir_NOT(c
, src
[0]);
1027 *dest
= ntq_umul(c
, src
[0], src
[1]);
1043 if (!ntq_emit_comparison(c
, dest
, instr
, instr
)) {
1044 fprintf(stderr
, "Bad comparison instruction\n");
1049 *dest
= ntq_emit_bcsel(c
, instr
, src
);
1053 *dest
= qir_SEL(c
, QPU_COND_ZC
, src
[1], src
[2]);
1057 *dest
= ntq_rcp(c
, src
[0]);
1060 *dest
= ntq_rsq(c
, src
[0]);
1063 *dest
= qir_EXP2(c
, src
[0]);
1066 *dest
= qir_LOG2(c
, src
[0]);
1070 *dest
= qir_ITOF(c
, qir_FTOI(c
, src
[0]));
1073 *dest
= ntq_fceil(c
, src
[0]);
1076 *dest
= ntq_ffract(c
, src
[0]);
1079 *dest
= ntq_ffloor(c
, src
[0]);
1083 *dest
= ntq_fsin(c
, src
[0]);
1086 *dest
= ntq_fcos(c
, src
[0]);
1090 *dest
= ntq_fsign(c
, src
[0]);
1094 *dest
= qir_FMAXABS(c
, src
[0], src
[0]);
1097 *dest
= qir_MAX(c
, src
[0],
1098 qir_SUB(c
, qir_uniform_ui(c
, 0), src
[0]));
1101 case nir_op_ibitfield_extract
:
1102 *dest
= ntq_emit_ibfe(c
, src
[0], src
[1], src
[2]);
1105 case nir_op_ubitfield_extract
:
1106 *dest
= ntq_emit_ubfe(c
, src
[0], src
[1], src
[2]);
1109 case nir_op_usadd_4x8
:
1110 *dest
= qir_V8ADDS(c
, src
[0], src
[1]);
1113 case nir_op_ussub_4x8
:
1114 *dest
= qir_V8SUBS(c
, src
[0], src
[1]);
1117 case nir_op_umin_4x8
:
1118 *dest
= qir_V8MIN(c
, src
[0], src
[1]);
1121 case nir_op_umax_4x8
:
1122 *dest
= qir_V8MAX(c
, src
[0], src
[1]);
1125 case nir_op_umul_unorm_4x8
:
1126 *dest
= qir_V8MULD(c
, src
[0], src
[1]);
1130 fprintf(stderr
, "unknown NIR ALU inst: ");
1131 nir_print_instr(&instr
->instr
, stderr
);
1132 fprintf(stderr
, "\n");
1138 emit_frag_end(struct vc4_compile
*c
)
1141 if (c
->output_color_index
!= -1) {
1142 color
= c
->outputs
[c
->output_color_index
];
1144 color
= qir_uniform_ui(c
, 0);
1147 uint32_t discard_cond
= QPU_COND_ALWAYS
;
1148 if (c
->discard
.file
!= QFILE_NULL
) {
1149 qir_SF(c
, c
->discard
);
1150 discard_cond
= QPU_COND_ZS
;
1153 if (c
->fs_key
->stencil_enabled
) {
1154 qir_MOV_dest(c
, qir_reg(QFILE_TLB_STENCIL_SETUP
, 0),
1155 qir_uniform(c
, QUNIFORM_STENCIL
, 0));
1156 if (c
->fs_key
->stencil_twoside
) {
1157 qir_MOV_dest(c
, qir_reg(QFILE_TLB_STENCIL_SETUP
, 0),
1158 qir_uniform(c
, QUNIFORM_STENCIL
, 1));
1160 if (c
->fs_key
->stencil_full_writemasks
) {
1161 qir_MOV_dest(c
, qir_reg(QFILE_TLB_STENCIL_SETUP
, 0),
1162 qir_uniform(c
, QUNIFORM_STENCIL
, 2));
1166 if (c
->output_sample_mask_index
!= -1) {
1167 qir_MS_MASK(c
, c
->outputs
[c
->output_sample_mask_index
]);
1170 if (c
->fs_key
->depth_enabled
) {
1171 if (c
->output_position_index
!= -1) {
1172 qir_FTOI_dest(c
, qir_reg(QFILE_TLB_Z_WRITE
, 0),
1174 c
->outputs
[c
->output_position_index
+ 2],
1175 qir_uniform_f(c
, 0xffffff)))->cond
= discard_cond
;
1177 qir_MOV_dest(c
, qir_reg(QFILE_TLB_Z_WRITE
, 0),
1178 qir_FRAG_Z(c
))->cond
= discard_cond
;
1182 if (!c
->msaa_per_sample_output
) {
1183 qir_MOV_dest(c
, qir_reg(QFILE_TLB_COLOR_WRITE
, 0),
1184 color
)->cond
= discard_cond
;
1186 for (int i
= 0; i
< VC4_MAX_SAMPLES
; i
++) {
1187 qir_MOV_dest(c
, qir_reg(QFILE_TLB_COLOR_WRITE_MS
, 0),
1188 c
->sample_colors
[i
])->cond
= discard_cond
;
1194 emit_scaled_viewport_write(struct vc4_compile
*c
, struct qreg rcp_w
)
1196 struct qreg packed
= qir_get_temp(c
);
1198 for (int i
= 0; i
< 2; i
++) {
1200 qir_uniform(c
, QUNIFORM_VIEWPORT_X_SCALE
+ i
, 0);
1202 struct qreg packed_chan
= packed
;
1203 packed_chan
.pack
= QPU_PACK_A_16A
+ i
;
1205 qir_FTOI_dest(c
, packed_chan
,
1208 c
->outputs
[c
->output_position_index
+ i
],
1213 qir_VPM_WRITE(c
, packed
);
1217 emit_zs_write(struct vc4_compile
*c
, struct qreg rcp_w
)
1219 struct qreg zscale
= qir_uniform(c
, QUNIFORM_VIEWPORT_Z_SCALE
, 0);
1220 struct qreg zoffset
= qir_uniform(c
, QUNIFORM_VIEWPORT_Z_OFFSET
, 0);
1222 qir_VPM_WRITE(c
, qir_FADD(c
, qir_FMUL(c
, qir_FMUL(c
,
1223 c
->outputs
[c
->output_position_index
+ 2],
1230 emit_rcp_wc_write(struct vc4_compile
*c
, struct qreg rcp_w
)
1232 qir_VPM_WRITE(c
, rcp_w
);
1236 emit_point_size_write(struct vc4_compile
*c
)
1238 struct qreg point_size
;
1240 if (c
->output_point_size_index
!= -1)
1241 point_size
= c
->outputs
[c
->output_point_size_index
];
1243 point_size
= qir_uniform_f(c
, 1.0);
1245 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1248 point_size
= qir_FMAX(c
, point_size
, qir_uniform_f(c
, .125));
1250 qir_VPM_WRITE(c
, point_size
);
1254 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1256 * The simulator insists that there be at least one vertex attribute, so
1257 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also
1258 * insists that all vertex attributes loaded get read by the VS/CS, so we have
1259 * to consume it here.
1262 emit_stub_vpm_read(struct vc4_compile
*c
)
1267 c
->vattr_sizes
[0] = 4;
1268 (void)qir_MOV(c
, qir_reg(QFILE_VPM
, 0));
1273 emit_vert_end(struct vc4_compile
*c
,
1274 struct vc4_varying_slot
*fs_inputs
,
1275 uint32_t num_fs_inputs
)
1277 struct qreg rcp_w
= qir_RCP(c
, c
->outputs
[c
->output_position_index
+ 3]);
1279 emit_stub_vpm_read(c
);
1281 emit_scaled_viewport_write(c
, rcp_w
);
1282 emit_zs_write(c
, rcp_w
);
1283 emit_rcp_wc_write(c
, rcp_w
);
1284 if (c
->vs_key
->per_vertex_point_size
)
1285 emit_point_size_write(c
);
1287 for (int i
= 0; i
< num_fs_inputs
; i
++) {
1288 struct vc4_varying_slot
*input
= &fs_inputs
[i
];
1291 for (j
= 0; j
< c
->num_outputs
; j
++) {
1292 struct vc4_varying_slot
*output
=
1293 &c
->output_slots
[j
];
1295 if (input
->slot
== output
->slot
&&
1296 input
->swizzle
== output
->swizzle
) {
1297 qir_VPM_WRITE(c
, c
->outputs
[j
]);
1301 /* Emit padding if we didn't find a declared VS output for
1304 if (j
== c
->num_outputs
)
1305 qir_VPM_WRITE(c
, qir_uniform_f(c
, 0.0));
1310 emit_coord_end(struct vc4_compile
*c
)
1312 struct qreg rcp_w
= qir_RCP(c
, c
->outputs
[c
->output_position_index
+ 3]);
1314 emit_stub_vpm_read(c
);
1316 for (int i
= 0; i
< 4; i
++)
1317 qir_VPM_WRITE(c
, c
->outputs
[c
->output_position_index
+ i
]);
1319 emit_scaled_viewport_write(c
, rcp_w
);
1320 emit_zs_write(c
, rcp_w
);
1321 emit_rcp_wc_write(c
, rcp_w
);
1322 if (c
->vs_key
->per_vertex_point_size
)
1323 emit_point_size_write(c
);
1327 vc4_optimize_nir(struct nir_shader
*s
)
1334 NIR_PASS_V(s
, nir_lower_vars_to_ssa
);
1335 NIR_PASS_V(s
, nir_lower_alu_to_scalar
);
1336 NIR_PASS_V(s
, nir_lower_phis_to_scalar
);
1338 NIR_PASS(progress
, s
, nir_copy_prop
);
1339 NIR_PASS(progress
, s
, nir_opt_dce
);
1340 NIR_PASS(progress
, s
, nir_opt_dead_cf
);
1341 NIR_PASS(progress
, s
, nir_opt_cse
);
1342 NIR_PASS(progress
, s
, nir_opt_peephole_select
);
1343 NIR_PASS(progress
, s
, nir_opt_algebraic
);
1344 NIR_PASS(progress
, s
, nir_opt_constant_folding
);
1345 NIR_PASS(progress
, s
, nir_opt_undef
);
1350 driver_location_compare(const void *in_a
, const void *in_b
)
1352 const nir_variable
*const *a
= in_a
;
1353 const nir_variable
*const *b
= in_b
;
1355 return (*a
)->data
.driver_location
- (*b
)->data
.driver_location
;
1359 ntq_setup_inputs(struct vc4_compile
*c
)
1361 unsigned num_entries
= 0;
1362 nir_foreach_variable(var
, &c
->s
->inputs
)
1365 nir_variable
*vars
[num_entries
];
1368 nir_foreach_variable(var
, &c
->s
->inputs
)
1371 /* Sort the variables so that we emit the input setup in
1372 * driver_location order. This is required for VPM reads, whose data
1373 * is fetched into the VPM in driver_location (TGSI register index)
1376 qsort(&vars
, num_entries
, sizeof(*vars
), driver_location_compare
);
1378 for (unsigned i
= 0; i
< num_entries
; i
++) {
1379 nir_variable
*var
= vars
[i
];
1380 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1381 unsigned loc
= var
->data
.driver_location
;
1383 assert(array_len
== 1);
1385 resize_qreg_array(c
, &c
->inputs
, &c
->inputs_array_size
,
1388 if (c
->stage
== QSTAGE_FRAG
) {
1389 if (var
->data
.location
== VARYING_SLOT_POS
) {
1390 emit_fragcoord_input(c
, loc
);
1391 } else if (var
->data
.location
>= VARYING_SLOT_VAR0
&&
1392 (c
->fs_key
->point_sprite_mask
&
1393 (1 << (var
->data
.location
-
1394 VARYING_SLOT_VAR0
)))) {
1395 c
->inputs
[loc
* 4 + 0] = c
->point_x
;
1396 c
->inputs
[loc
* 4 + 1] = c
->point_y
;
1398 emit_fragment_input(c
, loc
, var
->data
.location
);
1401 emit_vertex_input(c
, loc
);
1407 ntq_setup_outputs(struct vc4_compile
*c
)
1409 nir_foreach_variable(var
, &c
->s
->outputs
) {
1410 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1411 unsigned loc
= var
->data
.driver_location
* 4;
1413 assert(array_len
== 1);
1416 for (int i
= 0; i
< 4; i
++)
1417 add_output(c
, loc
+ i
, var
->data
.location
, i
);
1419 if (c
->stage
== QSTAGE_FRAG
) {
1420 switch (var
->data
.location
) {
1421 case FRAG_RESULT_COLOR
:
1422 case FRAG_RESULT_DATA0
:
1423 c
->output_color_index
= loc
;
1425 case FRAG_RESULT_DEPTH
:
1426 c
->output_position_index
= loc
;
1428 case FRAG_RESULT_SAMPLE_MASK
:
1429 c
->output_sample_mask_index
= loc
;
1433 switch (var
->data
.location
) {
1434 case VARYING_SLOT_POS
:
1435 c
->output_position_index
= loc
;
1437 case VARYING_SLOT_PSIZ
:
1438 c
->output_point_size_index
= loc
;
1446 ntq_setup_uniforms(struct vc4_compile
*c
)
1448 nir_foreach_variable(var
, &c
->s
->uniforms
) {
1449 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1450 unsigned array_elem_size
= 4 * sizeof(float);
1452 declare_uniform_range(c
, var
->data
.driver_location
* array_elem_size
,
1453 array_len
* array_elem_size
);
1459 * Sets up the mapping from nir_register to struct qreg *.
1461 * Each nir_register gets a struct qreg per 32-bit component being stored.
1464 ntq_setup_registers(struct vc4_compile
*c
, struct exec_list
*list
)
1466 foreach_list_typed(nir_register
, nir_reg
, node
, list
) {
1467 unsigned array_len
= MAX2(nir_reg
->num_array_elems
, 1);
1468 struct qreg
*qregs
= ralloc_array(c
->def_ht
, struct qreg
,
1470 nir_reg
->num_components
);
1472 _mesa_hash_table_insert(c
->def_ht
, nir_reg
, qregs
);
1474 for (int i
= 0; i
< array_len
* nir_reg
->num_components
; i
++)
1475 qregs
[i
] = qir_uniform_ui(c
, 0);
1480 ntq_emit_load_const(struct vc4_compile
*c
, nir_load_const_instr
*instr
)
1482 struct qreg
*qregs
= ntq_init_ssa_def(c
, &instr
->def
);
1483 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1484 qregs
[i
] = qir_uniform_ui(c
, instr
->value
.u32
[i
]);
1486 _mesa_hash_table_insert(c
->def_ht
, &instr
->def
, qregs
);
1490 ntq_emit_ssa_undef(struct vc4_compile
*c
, nir_ssa_undef_instr
*instr
)
1492 struct qreg
*qregs
= ntq_init_ssa_def(c
, &instr
->def
);
1494 /* QIR needs there to be *some* value, so pick 0 (same as for
1495 * ntq_setup_registers().
1497 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1498 qregs
[i
] = qir_uniform_ui(c
, 0);
1502 ntq_emit_intrinsic(struct vc4_compile
*c
, nir_intrinsic_instr
*instr
)
1504 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
1505 nir_const_value
*const_offset
;
1507 struct qreg
*dest
= NULL
;
1509 if (info
->has_dest
) {
1510 dest
= ntq_get_dest(c
, &instr
->dest
);
1513 switch (instr
->intrinsic
) {
1514 case nir_intrinsic_load_uniform
:
1515 assert(instr
->num_components
== 1);
1516 const_offset
= nir_src_as_const_value(instr
->src
[0]);
1518 offset
= instr
->const_index
[0] + const_offset
->u32
[0];
1519 assert(offset
% 4 == 0);
1520 /* We need dwords */
1521 offset
= offset
/ 4;
1522 if (offset
< VC4_NIR_STATE_UNIFORM_OFFSET
) {
1523 *dest
= qir_uniform(c
, QUNIFORM_UNIFORM
,
1526 *dest
= qir_uniform(c
, offset
-
1527 VC4_NIR_STATE_UNIFORM_OFFSET
,
1531 *dest
= indirect_uniform_load(c
, instr
);
1535 case nir_intrinsic_load_user_clip_plane
:
1536 for (int i
= 0; i
< instr
->num_components
; i
++) {
1537 dest
[i
] = qir_uniform(c
, QUNIFORM_USER_CLIP_PLANE
,
1538 instr
->const_index
[0] * 4 + i
);
1542 case nir_intrinsic_load_sample_mask_in
:
1543 *dest
= qir_uniform(c
, QUNIFORM_SAMPLE_MASK
, 0);
1546 case nir_intrinsic_load_front_face
:
1547 /* The register contains 0 (front) or 1 (back), and we need to
1548 * turn it into a NIR bool where true means front.
1551 qir_uniform_ui(c
, -1),
1552 qir_reg(QFILE_FRAG_REV_FLAG
, 0));
1555 case nir_intrinsic_load_input
:
1556 assert(instr
->num_components
== 1);
1557 const_offset
= nir_src_as_const_value(instr
->src
[0]);
1558 assert(const_offset
&& "vc4 doesn't support indirect inputs");
1559 if (instr
->const_index
[0] >= VC4_NIR_TLB_COLOR_READ_INPUT
) {
1560 assert(const_offset
->u32
[0] == 0);
1561 /* Reads of the per-sample color need to be done in
1564 int sample_index
= (instr
->const_index
[0] -
1565 VC4_NIR_TLB_COLOR_READ_INPUT
);
1566 for (int i
= 0; i
<= sample_index
; i
++) {
1567 if (c
->color_reads
[i
].file
== QFILE_NULL
) {
1569 qir_TLB_COLOR_READ(c
);
1572 *dest
= c
->color_reads
[sample_index
];
1574 offset
= instr
->const_index
[0] + const_offset
->u32
[0];
1575 *dest
= c
->inputs
[offset
];
1579 case nir_intrinsic_store_output
:
1580 const_offset
= nir_src_as_const_value(instr
->src
[1]);
1581 assert(const_offset
&& "vc4 doesn't support indirect outputs");
1582 offset
= instr
->const_index
[0] + const_offset
->u32
[0];
1584 /* MSAA color outputs are the only case where we have an
1585 * output that's not lowered to being a store of a single 32
1588 if (c
->stage
== QSTAGE_FRAG
&& instr
->num_components
== 4) {
1589 assert(offset
== c
->output_color_index
);
1590 for (int i
= 0; i
< 4; i
++) {
1591 c
->sample_colors
[i
] =
1592 qir_MOV(c
, ntq_get_src(c
, instr
->src
[0],
1596 assert(instr
->num_components
== 1);
1597 c
->outputs
[offset
] =
1598 qir_MOV(c
, ntq_get_src(c
, instr
->src
[0], 0));
1599 c
->num_outputs
= MAX2(c
->num_outputs
, offset
+ 1);
1603 case nir_intrinsic_discard
:
1604 c
->discard
= qir_uniform_ui(c
, ~0);
1607 case nir_intrinsic_discard_if
:
1608 if (c
->discard
.file
== QFILE_NULL
)
1609 c
->discard
= qir_uniform_ui(c
, 0);
1610 c
->discard
= qir_OR(c
, c
->discard
,
1611 ntq_get_src(c
, instr
->src
[0], 0));
1615 fprintf(stderr
, "Unknown intrinsic: ");
1616 nir_print_instr(&instr
->instr
, stderr
);
1617 fprintf(stderr
, "\n");
1623 ntq_emit_if(struct vc4_compile
*c
, nir_if
*if_stmt
)
1625 fprintf(stderr
, "general IF statements not handled.\n");
1629 ntq_emit_instr(struct vc4_compile
*c
, nir_instr
*instr
)
1631 switch (instr
->type
) {
1632 case nir_instr_type_alu
:
1633 ntq_emit_alu(c
, nir_instr_as_alu(instr
));
1636 case nir_instr_type_intrinsic
:
1637 ntq_emit_intrinsic(c
, nir_instr_as_intrinsic(instr
));
1640 case nir_instr_type_load_const
:
1641 ntq_emit_load_const(c
, nir_instr_as_load_const(instr
));
1644 case nir_instr_type_ssa_undef
:
1645 ntq_emit_ssa_undef(c
, nir_instr_as_ssa_undef(instr
));
1648 case nir_instr_type_tex
:
1649 ntq_emit_tex(c
, nir_instr_as_tex(instr
));
1653 fprintf(stderr
, "Unknown NIR instr type: ");
1654 nir_print_instr(instr
, stderr
);
1655 fprintf(stderr
, "\n");
1661 ntq_emit_block(struct vc4_compile
*c
, nir_block
*block
)
1663 nir_foreach_instr(instr
, block
) {
1664 ntq_emit_instr(c
, instr
);
1668 static void ntq_emit_cf_list(struct vc4_compile
*c
, struct exec_list
*list
);
1671 ntq_emit_loop(struct vc4_compile
*c
, nir_loop
*nloop
)
1673 fprintf(stderr
, "LOOPS not fully handled. Rendering errors likely.\n");
1674 ntq_emit_cf_list(c
, &nloop
->body
);
1678 ntq_emit_function(struct vc4_compile
*c
, nir_function_impl
*func
)
1680 fprintf(stderr
, "FUNCTIONS not handled.\n");
1685 ntq_emit_cf_list(struct vc4_compile
*c
, struct exec_list
*list
)
1687 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
1688 switch (node
->type
) {
1689 case nir_cf_node_block
:
1690 ntq_emit_block(c
, nir_cf_node_as_block(node
));
1693 case nir_cf_node_if
:
1694 ntq_emit_if(c
, nir_cf_node_as_if(node
));
1697 case nir_cf_node_loop
:
1698 ntq_emit_loop(c
, nir_cf_node_as_loop(node
));
1701 case nir_cf_node_function
:
1702 ntq_emit_function(c
, nir_cf_node_as_function(node
));
1706 fprintf(stderr
, "Unknown NIR node type\n");
1713 ntq_emit_impl(struct vc4_compile
*c
, nir_function_impl
*impl
)
1715 ntq_setup_registers(c
, &impl
->registers
);
1716 ntq_emit_cf_list(c
, &impl
->body
);
1720 nir_to_qir(struct vc4_compile
*c
)
1722 ntq_setup_inputs(c
);
1723 ntq_setup_outputs(c
);
1724 ntq_setup_uniforms(c
);
1725 ntq_setup_registers(c
, &c
->s
->registers
);
1727 /* Find the main function and emit the body. */
1728 nir_foreach_function(function
, c
->s
) {
1729 assert(strcmp(function
->name
, "main") == 0);
1730 assert(function
->impl
);
1731 ntq_emit_impl(c
, function
->impl
);
1735 static const nir_shader_compiler_options nir_options
= {
1736 .lower_extract_byte
= true,
1737 .lower_extract_word
= true,
1739 .lower_flrp32
= true,
1742 .lower_fsqrt
= true,
1743 .lower_negate
= true,
1747 count_nir_instrs(nir_shader
*nir
)
1750 nir_foreach_function(function
, nir
) {
1751 if (!function
->impl
)
1753 nir_foreach_block(block
, function
->impl
) {
1754 nir_foreach_instr(instr
, block
)
1761 static struct vc4_compile
*
1762 vc4_shader_ntq(struct vc4_context
*vc4
, enum qstage stage
,
1763 struct vc4_key
*key
)
1765 struct vc4_compile
*c
= qir_compile_init();
1768 c
->shader_state
= &key
->shader_state
->base
;
1769 c
->program_id
= key
->shader_state
->program_id
;
1771 p_atomic_inc_return(&key
->shader_state
->compiled_variant_count
);
1776 c
->fs_key
= (struct vc4_fs_key
*)key
;
1777 if (c
->fs_key
->is_points
) {
1778 c
->point_x
= emit_fragment_varying(c
, ~0, 0);
1779 c
->point_y
= emit_fragment_varying(c
, ~0, 0);
1780 } else if (c
->fs_key
->is_lines
) {
1781 c
->line_x
= emit_fragment_varying(c
, ~0, 0);
1785 c
->vs_key
= (struct vc4_vs_key
*)key
;
1788 c
->vs_key
= (struct vc4_vs_key
*)key
;
1792 c
->s
= nir_shader_clone(c
, key
->shader_state
->base
.ir
.nir
);
1793 NIR_PASS_V(c
->s
, nir_opt_global_to_local
);
1794 NIR_PASS_V(c
->s
, nir_convert_to_ssa
);
1796 if (stage
== QSTAGE_FRAG
)
1797 NIR_PASS_V(c
->s
, vc4_nir_lower_blend
, c
);
1799 struct nir_lower_tex_options tex_options
= {
1800 /* We would need to implement txs, but we don't want the
1801 * int/float conversions
1803 .lower_rect
= false,
1807 /* Apply swizzles to all samplers. */
1808 .swizzle_result
= ~0,
1811 /* Lower the format swizzle and ARB_texture_swizzle-style swizzle.
1812 * The format swizzling applies before sRGB decode, and
1813 * ARB_texture_swizzle is the last thing before returning the sample.
1815 for (int i
= 0; i
< ARRAY_SIZE(key
->tex
); i
++) {
1816 enum pipe_format format
= c
->key
->tex
[i
].format
;
1821 const uint8_t *format_swizzle
= vc4_get_format_swizzle(format
);
1823 for (int j
= 0; j
< 4; j
++) {
1824 uint8_t arb_swiz
= c
->key
->tex
[i
].swizzle
[j
];
1826 if (arb_swiz
<= 3) {
1827 tex_options
.swizzles
[i
][j
] =
1828 format_swizzle
[arb_swiz
];
1830 tex_options
.swizzles
[i
][j
] = arb_swiz
;
1834 if (util_format_is_srgb(format
))
1835 tex_options
.lower_srgb
|= (1 << i
);
1838 NIR_PASS_V(c
->s
, nir_normalize_cubemap_coords
);
1839 NIR_PASS_V(c
->s
, nir_lower_tex
, &tex_options
);
1841 if (c
->fs_key
&& c
->fs_key
->light_twoside
)
1842 NIR_PASS_V(c
->s
, nir_lower_two_sided_color
);
1844 if (c
->vs_key
&& c
->vs_key
->clamp_color
)
1845 NIR_PASS_V(c
->s
, nir_lower_clamp_color_outputs
);
1847 if (stage
== QSTAGE_FRAG
)
1848 NIR_PASS_V(c
->s
, nir_lower_clip_fs
, c
->key
->ucp_enables
);
1850 NIR_PASS_V(c
->s
, nir_lower_clip_vs
, c
->key
->ucp_enables
);
1852 NIR_PASS_V(c
->s
, vc4_nir_lower_io
, c
);
1853 NIR_PASS_V(c
->s
, vc4_nir_lower_txf_ms
, c
);
1854 NIR_PASS_V(c
->s
, nir_lower_idiv
);
1855 NIR_PASS_V(c
->s
, nir_lower_load_const_to_scalar
);
1857 vc4_optimize_nir(c
->s
);
1859 NIR_PASS_V(c
->s
, nir_remove_dead_variables
, nir_var_local
);
1860 NIR_PASS_V(c
->s
, nir_convert_from_ssa
, true);
1862 if (vc4_debug
& VC4_DEBUG_SHADERDB
) {
1863 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %d NIR instructions\n",
1864 qir_get_stage_name(c
->stage
),
1865 c
->program_id
, c
->variant_id
,
1866 count_nir_instrs(c
->s
));
1869 if (vc4_debug
& VC4_DEBUG_NIR
) {
1870 fprintf(stderr
, "%s prog %d/%d NIR:\n",
1871 qir_get_stage_name(c
->stage
),
1872 c
->program_id
, c
->variant_id
);
1873 nir_print_shader(c
->s
, stderr
);
1884 vc4
->prog
.fs
->input_slots
,
1885 vc4
->prog
.fs
->num_inputs
);
1892 if (vc4_debug
& VC4_DEBUG_QIR
) {
1893 fprintf(stderr
, "%s prog %d/%d pre-opt QIR:\n",
1894 qir_get_stage_name(c
->stage
),
1895 c
->program_id
, c
->variant_id
);
1897 fprintf(stderr
, "\n");
1901 qir_lower_uniforms(c
);
1903 qir_schedule_instructions(c
);
1905 if (vc4_debug
& VC4_DEBUG_QIR
) {
1906 fprintf(stderr
, "%s prog %d/%d QIR:\n",
1907 qir_get_stage_name(c
->stage
),
1908 c
->program_id
, c
->variant_id
);
1910 fprintf(stderr
, "\n");
1913 qir_reorder_uniforms(c
);
1914 vc4_generate_code(vc4
, c
);
1916 if (vc4_debug
& VC4_DEBUG_SHADERDB
) {
1917 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %d instructions\n",
1918 qir_get_stage_name(c
->stage
),
1919 c
->program_id
, c
->variant_id
,
1921 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %d uniforms\n",
1922 qir_get_stage_name(c
->stage
),
1923 c
->program_id
, c
->variant_id
,
1933 vc4_shader_state_create(struct pipe_context
*pctx
,
1934 const struct pipe_shader_state
*cso
)
1936 struct vc4_context
*vc4
= vc4_context(pctx
);
1937 struct vc4_uncompiled_shader
*so
= CALLOC_STRUCT(vc4_uncompiled_shader
);
1941 so
->program_id
= vc4
->next_uncompiled_program_id
++;
1943 nir_shader
*s
= tgsi_to_nir(cso
->tokens
, &nir_options
);
1945 if (vc4_debug
& VC4_DEBUG_TGSI
) {
1946 fprintf(stderr
, "%s prog %d TGSI:\n",
1947 gl_shader_stage_name(s
->stage
),
1949 tgsi_dump(cso
->tokens
, 0);
1950 fprintf(stderr
, "\n");
1953 so
->base
.type
= PIPE_SHADER_IR_NIR
;
1954 so
->base
.ir
.nir
= s
;
1960 copy_uniform_state_to_shader(struct vc4_compiled_shader
*shader
,
1961 struct vc4_compile
*c
)
1963 int count
= c
->num_uniforms
;
1964 struct vc4_shader_uniform_info
*uinfo
= &shader
->uniforms
;
1966 uinfo
->count
= count
;
1967 uinfo
->data
= ralloc_array(shader
, uint32_t, count
);
1968 memcpy(uinfo
->data
, c
->uniform_data
,
1969 count
* sizeof(*uinfo
->data
));
1970 uinfo
->contents
= ralloc_array(shader
, enum quniform_contents
, count
);
1971 memcpy(uinfo
->contents
, c
->uniform_contents
,
1972 count
* sizeof(*uinfo
->contents
));
1973 uinfo
->num_texture_samples
= c
->num_texture_samples
;
1975 vc4_set_shader_uniform_dirty_flags(shader
);
1978 static struct vc4_compiled_shader
*
1979 vc4_get_compiled_shader(struct vc4_context
*vc4
, enum qstage stage
,
1980 struct vc4_key
*key
)
1982 struct hash_table
*ht
;
1984 if (stage
== QSTAGE_FRAG
) {
1986 key_size
= sizeof(struct vc4_fs_key
);
1989 key_size
= sizeof(struct vc4_vs_key
);
1992 struct vc4_compiled_shader
*shader
;
1993 struct hash_entry
*entry
= _mesa_hash_table_search(ht
, key
);
1997 struct vc4_compile
*c
= vc4_shader_ntq(vc4
, stage
, key
);
1998 shader
= rzalloc(NULL
, struct vc4_compiled_shader
);
2000 shader
->program_id
= vc4
->next_compiled_program_id
++;
2001 if (stage
== QSTAGE_FRAG
) {
2002 bool input_live
[c
->num_input_slots
];
2004 memset(input_live
, 0, sizeof(input_live
));
2005 list_for_each_entry(struct qinst
, inst
, &c
->instructions
, link
) {
2006 for (int i
= 0; i
< qir_get_op_nsrc(inst
->op
); i
++) {
2007 if (inst
->src
[i
].file
== QFILE_VARY
)
2008 input_live
[inst
->src
[i
].index
] = true;
2012 shader
->input_slots
= ralloc_array(shader
,
2013 struct vc4_varying_slot
,
2014 c
->num_input_slots
);
2016 for (int i
= 0; i
< c
->num_input_slots
; i
++) {
2017 struct vc4_varying_slot
*slot
= &c
->input_slots
[i
];
2022 /* Skip non-VS-output inputs. */
2023 if (slot
->slot
== (uint8_t)~0)
2026 if (slot
->slot
== VARYING_SLOT_COL0
||
2027 slot
->slot
== VARYING_SLOT_COL1
||
2028 slot
->slot
== VARYING_SLOT_BFC0
||
2029 slot
->slot
== VARYING_SLOT_BFC1
) {
2030 shader
->color_inputs
|= (1 << shader
->num_inputs
);
2033 shader
->input_slots
[shader
->num_inputs
] = *slot
;
2034 shader
->num_inputs
++;
2037 shader
->num_inputs
= c
->num_inputs
;
2039 shader
->vattr_offsets
[0] = 0;
2040 for (int i
= 0; i
< 8; i
++) {
2041 shader
->vattr_offsets
[i
+ 1] =
2042 shader
->vattr_offsets
[i
] + c
->vattr_sizes
[i
];
2044 if (c
->vattr_sizes
[i
])
2045 shader
->vattrs_live
|= (1 << i
);
2049 copy_uniform_state_to_shader(shader
, c
);
2050 shader
->bo
= vc4_bo_alloc_shader(vc4
->screen
, c
->qpu_insts
,
2051 c
->qpu_inst_count
* sizeof(uint64_t));
2053 /* Copy the compiler UBO range state to the compiled shader, dropping
2054 * out arrays that were never referenced by an indirect load.
2056 * (Note that QIR dead code elimination of an array access still
2057 * leaves that array alive, though)
2059 if (c
->num_ubo_ranges
) {
2060 shader
->num_ubo_ranges
= c
->num_ubo_ranges
;
2061 shader
->ubo_ranges
= ralloc_array(shader
, struct vc4_ubo_range
,
2064 for (int i
= 0; i
< c
->num_uniform_ranges
; i
++) {
2065 struct vc4_compiler_ubo_range
*range
=
2070 shader
->ubo_ranges
[j
].dst_offset
= range
->dst_offset
;
2071 shader
->ubo_ranges
[j
].src_offset
= range
->src_offset
;
2072 shader
->ubo_ranges
[j
].size
= range
->size
;
2073 shader
->ubo_size
+= c
->ubo_ranges
[i
].size
;
2077 if (shader
->ubo_size
) {
2078 if (vc4_debug
& VC4_DEBUG_SHADERDB
) {
2079 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %d UBO uniforms\n",
2080 qir_get_stage_name(c
->stage
),
2081 c
->program_id
, c
->variant_id
,
2082 shader
->ubo_size
/ 4);
2086 qir_compile_destroy(c
);
2088 struct vc4_key
*dup_key
;
2089 dup_key
= ralloc_size(shader
, key_size
);
2090 memcpy(dup_key
, key
, key_size
);
2091 _mesa_hash_table_insert(ht
, dup_key
, shader
);
2097 vc4_setup_shared_key(struct vc4_context
*vc4
, struct vc4_key
*key
,
2098 struct vc4_texture_stateobj
*texstate
)
2100 for (int i
= 0; i
< texstate
->num_textures
; i
++) {
2101 struct pipe_sampler_view
*sampler
= texstate
->textures
[i
];
2102 struct pipe_sampler_state
*sampler_state
=
2103 texstate
->samplers
[i
];
2108 key
->tex
[i
].format
= sampler
->format
;
2109 key
->tex
[i
].swizzle
[0] = sampler
->swizzle_r
;
2110 key
->tex
[i
].swizzle
[1] = sampler
->swizzle_g
;
2111 key
->tex
[i
].swizzle
[2] = sampler
->swizzle_b
;
2112 key
->tex
[i
].swizzle
[3] = sampler
->swizzle_a
;
2114 if (sampler
->texture
->nr_samples
> 1) {
2115 key
->tex
[i
].msaa_width
= sampler
->texture
->width0
;
2116 key
->tex
[i
].msaa_height
= sampler
->texture
->height0
;
2117 } else if (sampler
){
2118 key
->tex
[i
].compare_mode
= sampler_state
->compare_mode
;
2119 key
->tex
[i
].compare_func
= sampler_state
->compare_func
;
2120 key
->tex
[i
].wrap_s
= sampler_state
->wrap_s
;
2121 key
->tex
[i
].wrap_t
= sampler_state
->wrap_t
;
2125 key
->ucp_enables
= vc4
->rasterizer
->base
.clip_plane_enable
;
2129 vc4_update_compiled_fs(struct vc4_context
*vc4
, uint8_t prim_mode
)
2131 struct vc4_fs_key local_key
;
2132 struct vc4_fs_key
*key
= &local_key
;
2134 if (!(vc4
->dirty
& (VC4_DIRTY_PRIM_MODE
|
2136 VC4_DIRTY_FRAMEBUFFER
|
2138 VC4_DIRTY_RASTERIZER
|
2139 VC4_DIRTY_SAMPLE_MASK
|
2141 VC4_DIRTY_TEXSTATE
|
2142 VC4_DIRTY_UNCOMPILED_FS
))) {
2146 memset(key
, 0, sizeof(*key
));
2147 vc4_setup_shared_key(vc4
, &key
->base
, &vc4
->fragtex
);
2148 key
->base
.shader_state
= vc4
->prog
.bind_fs
;
2149 key
->is_points
= (prim_mode
== PIPE_PRIM_POINTS
);
2150 key
->is_lines
= (prim_mode
>= PIPE_PRIM_LINES
&&
2151 prim_mode
<= PIPE_PRIM_LINE_STRIP
);
2152 key
->blend
= vc4
->blend
->rt
[0];
2153 if (vc4
->blend
->logicop_enable
) {
2154 key
->logicop_func
= vc4
->blend
->logicop_func
;
2156 key
->logicop_func
= PIPE_LOGICOP_COPY
;
2159 key
->msaa
= vc4
->rasterizer
->base
.multisample
;
2160 key
->sample_coverage
= (vc4
->rasterizer
->base
.multisample
&&
2161 vc4
->sample_mask
!= (1 << VC4_MAX_SAMPLES
) - 1);
2162 key
->sample_alpha_to_coverage
= vc4
->blend
->alpha_to_coverage
;
2163 key
->sample_alpha_to_one
= vc4
->blend
->alpha_to_one
;
2166 if (vc4
->framebuffer
.cbufs
[0])
2167 key
->color_format
= vc4
->framebuffer
.cbufs
[0]->format
;
2169 key
->stencil_enabled
= vc4
->zsa
->stencil_uniforms
[0] != 0;
2170 key
->stencil_twoside
= vc4
->zsa
->stencil_uniforms
[1] != 0;
2171 key
->stencil_full_writemasks
= vc4
->zsa
->stencil_uniforms
[2] != 0;
2172 key
->depth_enabled
= (vc4
->zsa
->base
.depth
.enabled
||
2173 key
->stencil_enabled
);
2174 if (vc4
->zsa
->base
.alpha
.enabled
) {
2175 key
->alpha_test
= true;
2176 key
->alpha_test_func
= vc4
->zsa
->base
.alpha
.func
;
2179 if (key
->is_points
) {
2180 key
->point_sprite_mask
=
2181 vc4
->rasterizer
->base
.sprite_coord_enable
;
2182 key
->point_coord_upper_left
=
2183 (vc4
->rasterizer
->base
.sprite_coord_mode
==
2184 PIPE_SPRITE_COORD_UPPER_LEFT
);
2187 key
->light_twoside
= vc4
->rasterizer
->base
.light_twoside
;
2189 struct vc4_compiled_shader
*old_fs
= vc4
->prog
.fs
;
2190 vc4
->prog
.fs
= vc4_get_compiled_shader(vc4
, QSTAGE_FRAG
, &key
->base
);
2191 if (vc4
->prog
.fs
== old_fs
)
2194 vc4
->dirty
|= VC4_DIRTY_COMPILED_FS
;
2195 if (vc4
->rasterizer
->base
.flatshade
&&
2196 old_fs
&& vc4
->prog
.fs
->color_inputs
!= old_fs
->color_inputs
) {
2197 vc4
->dirty
|= VC4_DIRTY_FLAT_SHADE_FLAGS
;
2202 vc4_update_compiled_vs(struct vc4_context
*vc4
, uint8_t prim_mode
)
2204 struct vc4_vs_key local_key
;
2205 struct vc4_vs_key
*key
= &local_key
;
2207 if (!(vc4
->dirty
& (VC4_DIRTY_PRIM_MODE
|
2208 VC4_DIRTY_RASTERIZER
|
2210 VC4_DIRTY_TEXSTATE
|
2211 VC4_DIRTY_VTXSTATE
|
2212 VC4_DIRTY_UNCOMPILED_VS
|
2213 VC4_DIRTY_COMPILED_FS
))) {
2217 memset(key
, 0, sizeof(*key
));
2218 vc4_setup_shared_key(vc4
, &key
->base
, &vc4
->verttex
);
2219 key
->base
.shader_state
= vc4
->prog
.bind_vs
;
2220 key
->compiled_fs_id
= vc4
->prog
.fs
->program_id
;
2221 key
->clamp_color
= vc4
->rasterizer
->base
.clamp_vertex_color
;
2223 for (int i
= 0; i
< ARRAY_SIZE(key
->attr_formats
); i
++)
2224 key
->attr_formats
[i
] = vc4
->vtx
->pipe
[i
].src_format
;
2226 key
->per_vertex_point_size
=
2227 (prim_mode
== PIPE_PRIM_POINTS
&&
2228 vc4
->rasterizer
->base
.point_size_per_vertex
);
2230 struct vc4_compiled_shader
*vs
=
2231 vc4_get_compiled_shader(vc4
, QSTAGE_VERT
, &key
->base
);
2232 if (vs
!= vc4
->prog
.vs
) {
2234 vc4
->dirty
|= VC4_DIRTY_COMPILED_VS
;
2237 key
->is_coord
= true;
2238 struct vc4_compiled_shader
*cs
=
2239 vc4_get_compiled_shader(vc4
, QSTAGE_COORD
, &key
->base
);
2240 if (cs
!= vc4
->prog
.cs
) {
2242 vc4
->dirty
|= VC4_DIRTY_COMPILED_CS
;
2247 vc4_update_compiled_shaders(struct vc4_context
*vc4
, uint8_t prim_mode
)
2249 vc4_update_compiled_fs(vc4
, prim_mode
);
2250 vc4_update_compiled_vs(vc4
, prim_mode
);
2254 fs_cache_hash(const void *key
)
2256 return _mesa_hash_data(key
, sizeof(struct vc4_fs_key
));
2260 vs_cache_hash(const void *key
)
2262 return _mesa_hash_data(key
, sizeof(struct vc4_vs_key
));
2266 fs_cache_compare(const void *key1
, const void *key2
)
2268 return memcmp(key1
, key2
, sizeof(struct vc4_fs_key
)) == 0;
2272 vs_cache_compare(const void *key1
, const void *key2
)
2274 return memcmp(key1
, key2
, sizeof(struct vc4_vs_key
)) == 0;
2278 delete_from_cache_if_matches(struct hash_table
*ht
,
2279 struct hash_entry
*entry
,
2280 struct vc4_uncompiled_shader
*so
)
2282 const struct vc4_key
*key
= entry
->key
;
2284 if (key
->shader_state
== so
) {
2285 struct vc4_compiled_shader
*shader
= entry
->data
;
2286 _mesa_hash_table_remove(ht
, entry
);
2287 vc4_bo_unreference(&shader
->bo
);
2288 ralloc_free(shader
);
2293 vc4_shader_state_delete(struct pipe_context
*pctx
, void *hwcso
)
2295 struct vc4_context
*vc4
= vc4_context(pctx
);
2296 struct vc4_uncompiled_shader
*so
= hwcso
;
2298 struct hash_entry
*entry
;
2299 hash_table_foreach(vc4
->fs_cache
, entry
)
2300 delete_from_cache_if_matches(vc4
->fs_cache
, entry
, so
);
2301 hash_table_foreach(vc4
->vs_cache
, entry
)
2302 delete_from_cache_if_matches(vc4
->vs_cache
, entry
, so
);
2304 ralloc_free(so
->base
.ir
.nir
);
2309 vc4_fp_state_bind(struct pipe_context
*pctx
, void *hwcso
)
2311 struct vc4_context
*vc4
= vc4_context(pctx
);
2312 vc4
->prog
.bind_fs
= hwcso
;
2313 vc4
->dirty
|= VC4_DIRTY_UNCOMPILED_FS
;
2317 vc4_vp_state_bind(struct pipe_context
*pctx
, void *hwcso
)
2319 struct vc4_context
*vc4
= vc4_context(pctx
);
2320 vc4
->prog
.bind_vs
= hwcso
;
2321 vc4
->dirty
|= VC4_DIRTY_UNCOMPILED_VS
;
2325 vc4_program_init(struct pipe_context
*pctx
)
2327 struct vc4_context
*vc4
= vc4_context(pctx
);
2329 pctx
->create_vs_state
= vc4_shader_state_create
;
2330 pctx
->delete_vs_state
= vc4_shader_state_delete
;
2332 pctx
->create_fs_state
= vc4_shader_state_create
;
2333 pctx
->delete_fs_state
= vc4_shader_state_delete
;
2335 pctx
->bind_fs_state
= vc4_fp_state_bind
;
2336 pctx
->bind_vs_state
= vc4_vp_state_bind
;
2338 vc4
->fs_cache
= _mesa_hash_table_create(pctx
, fs_cache_hash
,
2340 vc4
->vs_cache
= _mesa_hash_table_create(pctx
, vs_cache_hash
,
2345 vc4_program_fini(struct pipe_context
*pctx
)
2347 struct vc4_context
*vc4
= vc4_context(pctx
);
2349 struct hash_entry
*entry
;
2350 hash_table_foreach(vc4
->fs_cache
, entry
) {
2351 struct vc4_compiled_shader
*shader
= entry
->data
;
2352 vc4_bo_unreference(&shader
->bo
);
2353 ralloc_free(shader
);
2354 _mesa_hash_table_remove(vc4
->fs_cache
, entry
);
2357 hash_table_foreach(vc4
->vs_cache
, entry
) {
2358 struct vc4_compiled_shader
*shader
= entry
->data
;
2359 vc4_bo_unreference(&shader
->bo
);
2360 ralloc_free(shader
);
2361 _mesa_hash_table_remove(vc4
->vs_cache
, entry
);