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c0d956c276b7ea9c8d4a60a6f43517dbc17b5a34
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "util/u_format.h"
27 #include "util/u_hash.h"
28 #include "util/u_math.h"
29 #include "util/u_memory.h"
30 #include "util/ralloc.h"
31 #include "util/hash_table.h"
32 #include "tgsi/tgsi_dump.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "compiler/nir/nir.h"
35 #include "compiler/nir/nir_builder.h"
36 #include "nir/tgsi_to_nir.h"
37 #include "vc4_context.h"
38 #include "vc4_qpu.h"
39 #include "vc4_qir.h"
40 #include "mesa/state_tracker/st_glsl_types.h"
41
42 static struct qreg
43 ntq_get_src(struct vc4_compile *c, nir_src src, int i);
44 static void
45 ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list);
46
47 static void
48 resize_qreg_array(struct vc4_compile *c,
49 struct qreg **regs,
50 uint32_t *size,
51 uint32_t decl_size)
52 {
53 if (*size >= decl_size)
54 return;
55
56 uint32_t old_size = *size;
57 *size = MAX2(*size * 2, decl_size);
58 *regs = reralloc(c, *regs, struct qreg, *size);
59 if (!*regs) {
60 fprintf(stderr, "Malloc failure\n");
61 abort();
62 }
63
64 for (uint32_t i = old_size; i < *size; i++)
65 (*regs)[i] = c->undef;
66 }
67
68 static struct qreg
69 indirect_uniform_load(struct vc4_compile *c, nir_intrinsic_instr *intr)
70 {
71 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0);
72 uint32_t offset = nir_intrinsic_base(intr);
73 struct vc4_compiler_ubo_range *range = NULL;
74 unsigned i;
75 for (i = 0; i < c->num_uniform_ranges; i++) {
76 range = &c->ubo_ranges[i];
77 if (offset >= range->src_offset &&
78 offset < range->src_offset + range->size) {
79 break;
80 }
81 }
82 /* The driver-location-based offset always has to be within a declared
83 * uniform range.
84 */
85 assert(range);
86 if (!range->used) {
87 range->used = true;
88 range->dst_offset = c->next_ubo_dst_offset;
89 c->next_ubo_dst_offset += range->size;
90 c->num_ubo_ranges++;
91 }
92
93 offset -= range->src_offset;
94
95 /* Adjust for where we stored the TGSI register base. */
96 indirect_offset = qir_ADD(c, indirect_offset,
97 qir_uniform_ui(c, (range->dst_offset +
98 offset)));
99
100 /* Clamp to [0, array size). Note that MIN/MAX are signed. */
101 indirect_offset = qir_MAX(c, indirect_offset, qir_uniform_ui(c, 0));
102 indirect_offset = qir_MIN(c, indirect_offset,
103 qir_uniform_ui(c, (range->dst_offset +
104 range->size - 4)));
105
106 qir_TEX_DIRECT(c, indirect_offset, qir_uniform(c, QUNIFORM_UBO_ADDR, 0));
107 c->num_texture_samples++;
108 return qir_TEX_RESULT(c);
109 }
110
111 nir_ssa_def *
112 vc4_nir_get_swizzled_channel(nir_builder *b, nir_ssa_def **srcs, int swiz)
113 {
114 switch (swiz) {
115 default:
116 case PIPE_SWIZZLE_NONE:
117 fprintf(stderr, "warning: unknown swizzle\n");
118 /* FALLTHROUGH */
119 case PIPE_SWIZZLE_0:
120 return nir_imm_float(b, 0.0);
121 case PIPE_SWIZZLE_1:
122 return nir_imm_float(b, 1.0);
123 case PIPE_SWIZZLE_X:
124 case PIPE_SWIZZLE_Y:
125 case PIPE_SWIZZLE_Z:
126 case PIPE_SWIZZLE_W:
127 return srcs[swiz];
128 }
129 }
130
131 static struct qreg *
132 ntq_init_ssa_def(struct vc4_compile *c, nir_ssa_def *def)
133 {
134 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
135 def->num_components);
136 _mesa_hash_table_insert(c->def_ht, def, qregs);
137 return qregs;
138 }
139
140 static void
141 ntq_store_dest(struct vc4_compile *c, nir_dest *dest, int chan,
142 struct qreg result)
143 {
144 if (dest->is_ssa) {
145 assert(chan < dest->ssa.num_components);
146
147 struct qreg *qregs;
148 struct hash_entry *entry =
149 _mesa_hash_table_search(c->def_ht, &dest->ssa);
150
151 if (entry)
152 qregs = entry->data;
153 else
154 qregs = ntq_init_ssa_def(c, &dest->ssa);
155
156 qregs[chan] = result;
157 } else {
158 nir_register *reg = dest->reg.reg;
159 assert(dest->reg.base_offset == 0);
160 assert(reg->num_array_elems == 0);
161 struct hash_entry *entry =
162 _mesa_hash_table_search(c->def_ht, reg);
163 struct qreg *qregs = entry->data;
164
165 /* Conditionally move the result to the destination if the
166 * channel is active.
167 */
168 if (c->execute.file != QFILE_NULL) {
169 struct qinst *mov;
170
171 qir_SF(c, c->execute);
172 mov = qir_MOV_cond(c, QPU_COND_ZS, qregs[chan], result);
173 mov->cond_is_exec_mask = true;
174 } else {
175 qir_MOV_dest(c, qregs[chan], result);
176 }
177 }
178 }
179
180 static struct qreg *
181 ntq_get_dest(struct vc4_compile *c, nir_dest *dest)
182 {
183 if (dest->is_ssa) {
184 struct qreg *qregs = ntq_init_ssa_def(c, &dest->ssa);
185 for (int i = 0; i < dest->ssa.num_components; i++)
186 qregs[i] = c->undef;
187 return qregs;
188 } else {
189 nir_register *reg = dest->reg.reg;
190 assert(dest->reg.base_offset == 0);
191 assert(reg->num_array_elems == 0);
192 struct hash_entry *entry =
193 _mesa_hash_table_search(c->def_ht, reg);
194 return entry->data;
195 }
196 }
197
198 static struct qreg
199 ntq_get_src(struct vc4_compile *c, nir_src src, int i)
200 {
201 struct hash_entry *entry;
202 if (src.is_ssa) {
203 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
204 assert(i < src.ssa->num_components);
205 } else {
206 nir_register *reg = src.reg.reg;
207 entry = _mesa_hash_table_search(c->def_ht, reg);
208 assert(reg->num_array_elems == 0);
209 assert(src.reg.base_offset == 0);
210 assert(i < reg->num_components);
211 }
212
213 struct qreg *qregs = entry->data;
214 return qregs[i];
215 }
216
217 static struct qreg
218 ntq_get_alu_src(struct vc4_compile *c, nir_alu_instr *instr,
219 unsigned src)
220 {
221 assert(util_is_power_of_two(instr->dest.write_mask));
222 unsigned chan = ffs(instr->dest.write_mask) - 1;
223 struct qreg r = ntq_get_src(c, instr->src[src].src,
224 instr->src[src].swizzle[chan]);
225
226 assert(!instr->src[src].abs);
227 assert(!instr->src[src].negate);
228
229 return r;
230 };
231
232 static inline struct qreg
233 qir_SAT(struct vc4_compile *c, struct qreg val)
234 {
235 return qir_FMAX(c,
236 qir_FMIN(c, val, qir_uniform_f(c, 1.0)),
237 qir_uniform_f(c, 0.0));
238 }
239
240 static struct qreg
241 ntq_rcp(struct vc4_compile *c, struct qreg x)
242 {
243 struct qreg r = qir_RCP(c, x);
244
245 /* Apply a Newton-Raphson step to improve the accuracy. */
246 r = qir_FMUL(c, r, qir_FSUB(c,
247 qir_uniform_f(c, 2.0),
248 qir_FMUL(c, x, r)));
249
250 return r;
251 }
252
253 static struct qreg
254 ntq_rsq(struct vc4_compile *c, struct qreg x)
255 {
256 struct qreg r = qir_RSQ(c, x);
257
258 /* Apply a Newton-Raphson step to improve the accuracy. */
259 r = qir_FMUL(c, r, qir_FSUB(c,
260 qir_uniform_f(c, 1.5),
261 qir_FMUL(c,
262 qir_uniform_f(c, 0.5),
263 qir_FMUL(c, x,
264 qir_FMUL(c, r, r)))));
265
266 return r;
267 }
268
269 static struct qreg
270 ntq_umul(struct vc4_compile *c, struct qreg src0, struct qreg src1)
271 {
272 struct qreg src0_hi = qir_SHR(c, src0,
273 qir_uniform_ui(c, 24));
274 struct qreg src1_hi = qir_SHR(c, src1,
275 qir_uniform_ui(c, 24));
276
277 struct qreg hilo = qir_MUL24(c, src0_hi, src1);
278 struct qreg lohi = qir_MUL24(c, src0, src1_hi);
279 struct qreg lolo = qir_MUL24(c, src0, src1);
280
281 return qir_ADD(c, lolo, qir_SHL(c,
282 qir_ADD(c, hilo, lohi),
283 qir_uniform_ui(c, 24)));
284 }
285
286 static struct qreg
287 ntq_scale_depth_texture(struct vc4_compile *c, struct qreg src)
288 {
289 struct qreg depthf = qir_ITOF(c, qir_SHR(c, src,
290 qir_uniform_ui(c, 8)));
291 return qir_FMUL(c, depthf, qir_uniform_f(c, 1.0f/0xffffff));
292 }
293
294 /**
295 * Emits a lowered TXF_MS from an MSAA texture.
296 *
297 * The addressing math has been lowered in NIR, and now we just need to read
298 * it like a UBO.
299 */
300 static void
301 ntq_emit_txf(struct vc4_compile *c, nir_tex_instr *instr)
302 {
303 uint32_t tile_width = 32;
304 uint32_t tile_height = 32;
305 uint32_t tile_size = (tile_height * tile_width *
306 VC4_MAX_SAMPLES * sizeof(uint32_t));
307
308 unsigned unit = instr->texture_index;
309 uint32_t w = align(c->key->tex[unit].msaa_width, tile_width);
310 uint32_t w_tiles = w / tile_width;
311 uint32_t h = align(c->key->tex[unit].msaa_height, tile_height);
312 uint32_t h_tiles = h / tile_height;
313 uint32_t size = w_tiles * h_tiles * tile_size;
314
315 struct qreg addr;
316 assert(instr->num_srcs == 1);
317 assert(instr->src[0].src_type == nir_tex_src_coord);
318 addr = ntq_get_src(c, instr->src[0].src, 0);
319
320 /* Perform the clamping required by kernel validation. */
321 addr = qir_MAX(c, addr, qir_uniform_ui(c, 0));
322 addr = qir_MIN(c, addr, qir_uniform_ui(c, size - 4));
323
324 qir_TEX_DIRECT(c, addr, qir_uniform(c, QUNIFORM_TEXTURE_MSAA_ADDR, unit));
325
326 struct qreg tex = qir_TEX_RESULT(c);
327 c->num_texture_samples++;
328
329 struct qreg dest[4];
330 enum pipe_format format = c->key->tex[unit].format;
331 if (util_format_is_depth_or_stencil(format)) {
332 struct qreg scaled = ntq_scale_depth_texture(c, tex);
333 for (int i = 0; i < 4; i++)
334 dest[i] = scaled;
335 } else {
336 for (int i = 0; i < 4; i++)
337 dest[i] = qir_UNPACK_8_F(c, tex, i);
338 }
339
340 for (int i = 0; i < 4; i++)
341 ntq_store_dest(c, &instr->dest, i, dest[i]);
342 }
343
344 static void
345 ntq_emit_tex(struct vc4_compile *c, nir_tex_instr *instr)
346 {
347 struct qreg s, t, r, lod, compare;
348 bool is_txb = false, is_txl = false;
349 unsigned unit = instr->texture_index;
350
351 if (instr->op == nir_texop_txf) {
352 ntq_emit_txf(c, instr);
353 return;
354 }
355
356 for (unsigned i = 0; i < instr->num_srcs; i++) {
357 switch (instr->src[i].src_type) {
358 case nir_tex_src_coord:
359 s = ntq_get_src(c, instr->src[i].src, 0);
360 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D)
361 t = qir_uniform_f(c, 0.5);
362 else
363 t = ntq_get_src(c, instr->src[i].src, 1);
364 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
365 r = ntq_get_src(c, instr->src[i].src, 2);
366 break;
367 case nir_tex_src_bias:
368 lod = ntq_get_src(c, instr->src[i].src, 0);
369 is_txb = true;
370 break;
371 case nir_tex_src_lod:
372 lod = ntq_get_src(c, instr->src[i].src, 0);
373 is_txl = true;
374 break;
375 case nir_tex_src_comparitor:
376 compare = ntq_get_src(c, instr->src[i].src, 0);
377 break;
378 default:
379 unreachable("unknown texture source");
380 }
381 }
382
383 if (c->key->tex[unit].force_first_level) {
384 lod = qir_uniform(c, QUNIFORM_TEXTURE_FIRST_LEVEL, unit);
385 is_txl = true;
386 is_txb = false;
387 }
388
389 struct qreg texture_u[] = {
390 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit),
391 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
392 qir_uniform(c, QUNIFORM_CONSTANT, 0),
393 qir_uniform(c, QUNIFORM_CONSTANT, 0),
394 };
395 uint32_t next_texture_u = 0;
396
397 /* There is no native support for GL texture rectangle coordinates, so
398 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
399 * 1]).
400 */
401 if (instr->sampler_dim == GLSL_SAMPLER_DIM_RECT) {
402 s = qir_FMUL(c, s,
403 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_X, unit));
404 t = qir_FMUL(c, t,
405 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_Y, unit));
406 }
407
408 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE || is_txl) {
409 texture_u[2] = qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P2,
410 unit | (is_txl << 16));
411 }
412
413 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
414 qir_TEX_R(c, r, texture_u[next_texture_u++]);
415 } else if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
416 c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP ||
417 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
418 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
419 qir_TEX_R(c, qir_uniform(c, QUNIFORM_TEXTURE_BORDER_COLOR, unit),
420 texture_u[next_texture_u++]);
421 }
422
423 if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP) {
424 s = qir_SAT(c, s);
425 }
426
427 if (c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
428 t = qir_SAT(c, t);
429 }
430
431 qir_TEX_T(c, t, texture_u[next_texture_u++]);
432
433 if (is_txl || is_txb)
434 qir_TEX_B(c, lod, texture_u[next_texture_u++]);
435
436 qir_TEX_S(c, s, texture_u[next_texture_u++]);
437
438 c->num_texture_samples++;
439 struct qreg tex = qir_TEX_RESULT(c);
440
441 enum pipe_format format = c->key->tex[unit].format;
442
443 struct qreg *dest = ntq_get_dest(c, &instr->dest);
444 if (util_format_is_depth_or_stencil(format)) {
445 struct qreg normalized = ntq_scale_depth_texture(c, tex);
446 struct qreg depth_output;
447
448 struct qreg u0 = qir_uniform_f(c, 0.0f);
449 struct qreg u1 = qir_uniform_f(c, 1.0f);
450 if (c->key->tex[unit].compare_mode) {
451 switch (c->key->tex[unit].compare_func) {
452 case PIPE_FUNC_NEVER:
453 depth_output = qir_uniform_f(c, 0.0f);
454 break;
455 case PIPE_FUNC_ALWAYS:
456 depth_output = u1;
457 break;
458 case PIPE_FUNC_EQUAL:
459 qir_SF(c, qir_FSUB(c, compare, normalized));
460 depth_output = qir_SEL(c, QPU_COND_ZS, u1, u0);
461 break;
462 case PIPE_FUNC_NOTEQUAL:
463 qir_SF(c, qir_FSUB(c, compare, normalized));
464 depth_output = qir_SEL(c, QPU_COND_ZC, u1, u0);
465 break;
466 case PIPE_FUNC_GREATER:
467 qir_SF(c, qir_FSUB(c, compare, normalized));
468 depth_output = qir_SEL(c, QPU_COND_NC, u1, u0);
469 break;
470 case PIPE_FUNC_GEQUAL:
471 qir_SF(c, qir_FSUB(c, normalized, compare));
472 depth_output = qir_SEL(c, QPU_COND_NS, u1, u0);
473 break;
474 case PIPE_FUNC_LESS:
475 qir_SF(c, qir_FSUB(c, compare, normalized));
476 depth_output = qir_SEL(c, QPU_COND_NS, u1, u0);
477 break;
478 case PIPE_FUNC_LEQUAL:
479 qir_SF(c, qir_FSUB(c, normalized, compare));
480 depth_output = qir_SEL(c, QPU_COND_NC, u1, u0);
481 break;
482 }
483 } else {
484 depth_output = normalized;
485 }
486
487 for (int i = 0; i < 4; i++)
488 dest[i] = depth_output;
489 } else {
490 for (int i = 0; i < 4; i++)
491 dest[i] = qir_UNPACK_8_F(c, tex, i);
492 }
493 }
494
495 /**
496 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
497 * to zero).
498 */
499 static struct qreg
500 ntq_ffract(struct vc4_compile *c, struct qreg src)
501 {
502 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
503 struct qreg diff = qir_FSUB(c, src, trunc);
504 qir_SF(c, diff);
505 return qir_SEL(c, QPU_COND_NS,
506 qir_FADD(c, diff, qir_uniform_f(c, 1.0)), diff);
507 }
508
509 /**
510 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
511 * zero).
512 */
513 static struct qreg
514 ntq_ffloor(struct vc4_compile *c, struct qreg src)
515 {
516 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
517
518 /* This will be < 0 if we truncated and the truncation was of a value
519 * that was < 0 in the first place.
520 */
521 qir_SF(c, qir_FSUB(c, src, trunc));
522
523 return qir_SEL(c, QPU_COND_NS,
524 qir_FSUB(c, trunc, qir_uniform_f(c, 1.0)), trunc);
525 }
526
527 /**
528 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
529 * zero).
530 */
531 static struct qreg
532 ntq_fceil(struct vc4_compile *c, struct qreg src)
533 {
534 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
535
536 /* This will be < 0 if we truncated and the truncation was of a value
537 * that was > 0 in the first place.
538 */
539 qir_SF(c, qir_FSUB(c, trunc, src));
540
541 return qir_SEL(c, QPU_COND_NS,
542 qir_FADD(c, trunc, qir_uniform_f(c, 1.0)), trunc);
543 }
544
545 static struct qreg
546 ntq_fsin(struct vc4_compile *c, struct qreg src)
547 {
548 float coeff[] = {
549 -2.0 * M_PI,
550 pow(2.0 * M_PI, 3) / (3 * 2 * 1),
551 -pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
552 pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
553 -pow(2.0 * M_PI, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
554 };
555
556 struct qreg scaled_x =
557 qir_FMUL(c,
558 src,
559 qir_uniform_f(c, 1.0 / (M_PI * 2.0)));
560
561 struct qreg x = qir_FADD(c,
562 ntq_ffract(c, scaled_x),
563 qir_uniform_f(c, -0.5));
564 struct qreg x2 = qir_FMUL(c, x, x);
565 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
566 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
567 x = qir_FMUL(c, x, x2);
568 sum = qir_FADD(c,
569 sum,
570 qir_FMUL(c,
571 x,
572 qir_uniform_f(c, coeff[i])));
573 }
574 return sum;
575 }
576
577 static struct qreg
578 ntq_fcos(struct vc4_compile *c, struct qreg src)
579 {
580 float coeff[] = {
581 -1.0f,
582 pow(2.0 * M_PI, 2) / (2 * 1),
583 -pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
584 pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
585 -pow(2.0 * M_PI, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
586 pow(2.0 * M_PI, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
587 };
588
589 struct qreg scaled_x =
590 qir_FMUL(c, src,
591 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
592 struct qreg x_frac = qir_FADD(c,
593 ntq_ffract(c, scaled_x),
594 qir_uniform_f(c, -0.5));
595
596 struct qreg sum = qir_uniform_f(c, coeff[0]);
597 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
598 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
599 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
600 if (i != 1)
601 x = qir_FMUL(c, x, x2);
602
603 struct qreg mul = qir_FMUL(c,
604 x,
605 qir_uniform_f(c, coeff[i]));
606 if (i == 0)
607 sum = mul;
608 else
609 sum = qir_FADD(c, sum, mul);
610 }
611 return sum;
612 }
613
614 static struct qreg
615 ntq_fsign(struct vc4_compile *c, struct qreg src)
616 {
617 struct qreg t = qir_get_temp(c);
618
619 qir_SF(c, src);
620 qir_MOV_dest(c, t, qir_uniform_f(c, 0.0));
621 qir_MOV_dest(c, t, qir_uniform_f(c, 1.0))->cond = QPU_COND_ZC;
622 qir_MOV_dest(c, t, qir_uniform_f(c, -1.0))->cond = QPU_COND_NS;
623 return t;
624 }
625
626 static void
627 emit_vertex_input(struct vc4_compile *c, int attr)
628 {
629 enum pipe_format format = c->vs_key->attr_formats[attr];
630 uint32_t attr_size = util_format_get_blocksize(format);
631
632 c->vattr_sizes[attr] = align(attr_size, 4);
633 for (int i = 0; i < align(attr_size, 4) / 4; i++) {
634 c->inputs[attr * 4 + i] =
635 qir_MOV(c, qir_reg(QFILE_VPM, attr * 4 + i));
636 c->num_inputs++;
637 }
638 }
639
640 static void
641 emit_fragcoord_input(struct vc4_compile *c, int attr)
642 {
643 c->inputs[attr * 4 + 0] = qir_ITOF(c, qir_reg(QFILE_FRAG_X, 0));
644 c->inputs[attr * 4 + 1] = qir_ITOF(c, qir_reg(QFILE_FRAG_Y, 0));
645 c->inputs[attr * 4 + 2] =
646 qir_FMUL(c,
647 qir_ITOF(c, qir_FRAG_Z(c)),
648 qir_uniform_f(c, 1.0 / 0xffffff));
649 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
650 }
651
652 static struct qreg
653 emit_fragment_varying(struct vc4_compile *c, gl_varying_slot slot,
654 uint8_t swizzle)
655 {
656 uint32_t i = c->num_input_slots++;
657 struct qreg vary = {
658 QFILE_VARY,
659 i
660 };
661
662 if (c->num_input_slots >= c->input_slots_array_size) {
663 c->input_slots_array_size =
664 MAX2(4, c->input_slots_array_size * 2);
665
666 c->input_slots = reralloc(c, c->input_slots,
667 struct vc4_varying_slot,
668 c->input_slots_array_size);
669 }
670
671 c->input_slots[i].slot = slot;
672 c->input_slots[i].swizzle = swizzle;
673
674 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
675 }
676
677 static void
678 emit_fragment_input(struct vc4_compile *c, int attr, gl_varying_slot slot)
679 {
680 for (int i = 0; i < 4; i++) {
681 c->inputs[attr * 4 + i] =
682 emit_fragment_varying(c, slot, i);
683 c->num_inputs++;
684 }
685 }
686
687 static void
688 add_output(struct vc4_compile *c,
689 uint32_t decl_offset,
690 uint8_t slot,
691 uint8_t swizzle)
692 {
693 uint32_t old_array_size = c->outputs_array_size;
694 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
695 decl_offset + 1);
696
697 if (old_array_size != c->outputs_array_size) {
698 c->output_slots = reralloc(c,
699 c->output_slots,
700 struct vc4_varying_slot,
701 c->outputs_array_size);
702 }
703
704 c->output_slots[decl_offset].slot = slot;
705 c->output_slots[decl_offset].swizzle = swizzle;
706 }
707
708 static void
709 declare_uniform_range(struct vc4_compile *c, uint32_t start, uint32_t size)
710 {
711 unsigned array_id = c->num_uniform_ranges++;
712 if (array_id >= c->ubo_ranges_array_size) {
713 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
714 array_id + 1);
715 c->ubo_ranges = reralloc(c, c->ubo_ranges,
716 struct vc4_compiler_ubo_range,
717 c->ubo_ranges_array_size);
718 }
719
720 c->ubo_ranges[array_id].dst_offset = 0;
721 c->ubo_ranges[array_id].src_offset = start;
722 c->ubo_ranges[array_id].size = size;
723 c->ubo_ranges[array_id].used = false;
724 }
725
726 static bool
727 ntq_src_is_only_ssa_def_user(nir_src *src)
728 {
729 if (!src->is_ssa)
730 return false;
731
732 if (!list_empty(&src->ssa->if_uses))
733 return false;
734
735 return (src->ssa->uses.next == &src->use_link &&
736 src->ssa->uses.next->next == &src->ssa->uses);
737 }
738
739 /**
740 * In general, emits a nir_pack_unorm_4x8 as a series of MOVs with the pack
741 * bit set.
742 *
743 * However, as an optimization, it tries to find the instructions generating
744 * the sources to be packed and just emit the pack flag there, if possible.
745 */
746 static void
747 ntq_emit_pack_unorm_4x8(struct vc4_compile *c, nir_alu_instr *instr)
748 {
749 struct qreg result = qir_get_temp(c);
750 struct nir_alu_instr *vec4 = NULL;
751
752 /* If packing from a vec4 op (as expected), identify it so that we can
753 * peek back at what generated its sources.
754 */
755 if (instr->src[0].src.is_ssa &&
756 instr->src[0].src.ssa->parent_instr->type == nir_instr_type_alu &&
757 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr)->op ==
758 nir_op_vec4) {
759 vec4 = nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
760 }
761
762 /* If the pack is replicating the same channel 4 times, use the 8888
763 * pack flag. This is common for blending using the alpha
764 * channel.
765 */
766 if (instr->src[0].swizzle[0] == instr->src[0].swizzle[1] &&
767 instr->src[0].swizzle[0] == instr->src[0].swizzle[2] &&
768 instr->src[0].swizzle[0] == instr->src[0].swizzle[3]) {
769 struct qreg rep = ntq_get_src(c,
770 instr->src[0].src,
771 instr->src[0].swizzle[0]);
772 ntq_store_dest(c, &instr->dest.dest, 0, qir_PACK_8888_F(c, rep));
773 return;
774 }
775
776 for (int i = 0; i < 4; i++) {
777 int swiz = instr->src[0].swizzle[i];
778 struct qreg src;
779 if (vec4) {
780 src = ntq_get_src(c, vec4->src[swiz].src,
781 vec4->src[swiz].swizzle[0]);
782 } else {
783 src = ntq_get_src(c, instr->src[0].src, swiz);
784 }
785
786 if (vec4 &&
787 ntq_src_is_only_ssa_def_user(&vec4->src[swiz].src) &&
788 src.file == QFILE_TEMP &&
789 c->defs[src.index] &&
790 qir_is_mul(c->defs[src.index]) &&
791 !c->defs[src.index]->dst.pack) {
792 struct qinst *rewrite = c->defs[src.index];
793 c->defs[src.index] = NULL;
794 rewrite->dst = result;
795 rewrite->dst.pack = QPU_PACK_MUL_8A + i;
796 continue;
797 }
798
799 qir_PACK_8_F(c, result, src, i);
800 }
801
802 ntq_store_dest(c, &instr->dest.dest, 0, result);
803 }
804
805 /** Handles sign-extended bitfield extracts for 16 bits. */
806 static struct qreg
807 ntq_emit_ibfe(struct vc4_compile *c, struct qreg base, struct qreg offset,
808 struct qreg bits)
809 {
810 assert(bits.file == QFILE_UNIF &&
811 c->uniform_contents[bits.index] == QUNIFORM_CONSTANT &&
812 c->uniform_data[bits.index] == 16);
813
814 assert(offset.file == QFILE_UNIF &&
815 c->uniform_contents[offset.index] == QUNIFORM_CONSTANT);
816 int offset_bit = c->uniform_data[offset.index];
817 assert(offset_bit % 16 == 0);
818
819 return qir_UNPACK_16_I(c, base, offset_bit / 16);
820 }
821
822 /** Handles unsigned bitfield extracts for 8 bits. */
823 static struct qreg
824 ntq_emit_ubfe(struct vc4_compile *c, struct qreg base, struct qreg offset,
825 struct qreg bits)
826 {
827 assert(bits.file == QFILE_UNIF &&
828 c->uniform_contents[bits.index] == QUNIFORM_CONSTANT &&
829 c->uniform_data[bits.index] == 8);
830
831 assert(offset.file == QFILE_UNIF &&
832 c->uniform_contents[offset.index] == QUNIFORM_CONSTANT);
833 int offset_bit = c->uniform_data[offset.index];
834 assert(offset_bit % 8 == 0);
835
836 return qir_UNPACK_8_I(c, base, offset_bit / 8);
837 }
838
839 /**
840 * If compare_instr is a valid comparison instruction, emits the
841 * compare_instr's comparison and returns the sel_instr's return value based
842 * on the compare_instr's result.
843 */
844 static bool
845 ntq_emit_comparison(struct vc4_compile *c, struct qreg *dest,
846 nir_alu_instr *compare_instr,
847 nir_alu_instr *sel_instr)
848 {
849 enum qpu_cond cond;
850
851 switch (compare_instr->op) {
852 case nir_op_feq:
853 case nir_op_ieq:
854 case nir_op_seq:
855 cond = QPU_COND_ZS;
856 break;
857 case nir_op_fne:
858 case nir_op_ine:
859 case nir_op_sne:
860 cond = QPU_COND_ZC;
861 break;
862 case nir_op_fge:
863 case nir_op_ige:
864 case nir_op_uge:
865 case nir_op_sge:
866 cond = QPU_COND_NC;
867 break;
868 case nir_op_flt:
869 case nir_op_ilt:
870 case nir_op_slt:
871 cond = QPU_COND_NS;
872 break;
873 default:
874 return false;
875 }
876
877 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
878 struct qreg src1 = ntq_get_alu_src(c, compare_instr, 1);
879
880 unsigned unsized_type =
881 nir_alu_type_get_base_type(nir_op_infos[compare_instr->op].input_types[0]);
882 if (unsized_type == nir_type_float)
883 qir_SF(c, qir_FSUB(c, src0, src1));
884 else
885 qir_SF(c, qir_SUB(c, src0, src1));
886
887 switch (sel_instr->op) {
888 case nir_op_seq:
889 case nir_op_sne:
890 case nir_op_sge:
891 case nir_op_slt:
892 *dest = qir_SEL(c, cond,
893 qir_uniform_f(c, 1.0), qir_uniform_f(c, 0.0));
894 break;
895
896 case nir_op_bcsel:
897 *dest = qir_SEL(c, cond,
898 ntq_get_alu_src(c, sel_instr, 1),
899 ntq_get_alu_src(c, sel_instr, 2));
900 break;
901
902 default:
903 *dest = qir_SEL(c, cond,
904 qir_uniform_ui(c, ~0), qir_uniform_ui(c, 0));
905 break;
906 }
907
908 return true;
909 }
910
911 /**
912 * Attempts to fold a comparison generating a boolean result into the
913 * condition code for selecting between two values, instead of comparing the
914 * boolean result against 0 to generate the condition code.
915 */
916 static struct qreg ntq_emit_bcsel(struct vc4_compile *c, nir_alu_instr *instr,
917 struct qreg *src)
918 {
919 if (!instr->src[0].src.is_ssa)
920 goto out;
921 if (instr->src[0].src.ssa->parent_instr->type != nir_instr_type_alu)
922 goto out;
923 nir_alu_instr *compare =
924 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
925 if (!compare)
926 goto out;
927
928 struct qreg dest;
929 if (ntq_emit_comparison(c, &dest, compare, instr))
930 return dest;
931
932 out:
933 qir_SF(c, src[0]);
934 return qir_SEL(c, QPU_COND_NS, src[1], src[2]);
935 }
936
937 static struct qreg
938 ntq_fddx(struct vc4_compile *c, struct qreg src)
939 {
940 /* Make sure that we have a bare temp to use for MUL rotation, so it
941 * can be allocated to an accumulator.
942 */
943 if (src.pack || src.file != QFILE_TEMP)
944 src = qir_MOV(c, src);
945
946 struct qreg from_left = qir_ROT_MUL(c, src, 1);
947 struct qreg from_right = qir_ROT_MUL(c, src, 15);
948
949 /* Distinguish left/right pixels of the quad. */
950 qir_SF(c, qir_AND(c, qir_reg(QFILE_QPU_ELEMENT, 0),
951 qir_uniform_ui(c, 1)));
952
953 return qir_SEL(c, QPU_COND_ZS,
954 qir_FSUB(c, from_right, src),
955 qir_FSUB(c, src, from_left));
956 }
957
958 static struct qreg
959 ntq_fddy(struct vc4_compile *c, struct qreg src)
960 {
961 if (src.pack || src.file != QFILE_TEMP)
962 src = qir_MOV(c, src);
963
964 struct qreg from_bottom = qir_ROT_MUL(c, src, 2);
965 struct qreg from_top = qir_ROT_MUL(c, src, 14);
966
967 /* Distinguish top/bottom pixels of the quad. */
968 qir_SF(c, qir_AND(c,
969 qir_reg(QFILE_QPU_ELEMENT, 0),
970 qir_uniform_ui(c, 2)));
971
972 return qir_SEL(c, QPU_COND_ZS,
973 qir_FSUB(c, from_top, src),
974 qir_FSUB(c, src, from_bottom));
975 }
976
977 static void
978 ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr)
979 {
980 /* This should always be lowered to ALU operations for VC4. */
981 assert(!instr->dest.saturate);
982
983 /* Vectors are special in that they have non-scalarized writemasks,
984 * and just take the first swizzle channel for each argument in order
985 * into each writemask channel.
986 */
987 if (instr->op == nir_op_vec2 ||
988 instr->op == nir_op_vec3 ||
989 instr->op == nir_op_vec4) {
990 struct qreg srcs[4];
991 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
992 srcs[i] = ntq_get_src(c, instr->src[i].src,
993 instr->src[i].swizzle[0]);
994 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
995 ntq_store_dest(c, &instr->dest.dest, i, srcs[i]);
996 return;
997 }
998
999 if (instr->op == nir_op_pack_unorm_4x8) {
1000 ntq_emit_pack_unorm_4x8(c, instr);
1001 return;
1002 }
1003
1004 if (instr->op == nir_op_unpack_unorm_4x8) {
1005 struct qreg src = ntq_get_src(c, instr->src[0].src,
1006 instr->src[0].swizzle[0]);
1007 for (int i = 0; i < 4; i++) {
1008 if (instr->dest.write_mask & (1 << i))
1009 ntq_store_dest(c, &instr->dest.dest, i,
1010 qir_UNPACK_8_F(c, src, i));
1011 }
1012 return;
1013 }
1014
1015 /* General case: We can just grab the one used channel per src. */
1016 struct qreg src[nir_op_infos[instr->op].num_inputs];
1017 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
1018 src[i] = ntq_get_alu_src(c, instr, i);
1019 }
1020
1021 struct qreg result;
1022
1023 switch (instr->op) {
1024 case nir_op_fmov:
1025 case nir_op_imov:
1026 result = qir_MOV(c, src[0]);
1027 break;
1028 case nir_op_fmul:
1029 result = qir_FMUL(c, src[0], src[1]);
1030 break;
1031 case nir_op_fadd:
1032 result = qir_FADD(c, src[0], src[1]);
1033 break;
1034 case nir_op_fsub:
1035 result = qir_FSUB(c, src[0], src[1]);
1036 break;
1037 case nir_op_fmin:
1038 result = qir_FMIN(c, src[0], src[1]);
1039 break;
1040 case nir_op_fmax:
1041 result = qir_FMAX(c, src[0], src[1]);
1042 break;
1043
1044 case nir_op_f2i:
1045 case nir_op_f2u:
1046 result = qir_FTOI(c, src[0]);
1047 break;
1048 case nir_op_i2f:
1049 case nir_op_u2f:
1050 result = qir_ITOF(c, src[0]);
1051 break;
1052 case nir_op_b2f:
1053 result = qir_AND(c, src[0], qir_uniform_f(c, 1.0));
1054 break;
1055 case nir_op_b2i:
1056 result = qir_AND(c, src[0], qir_uniform_ui(c, 1));
1057 break;
1058 case nir_op_i2b:
1059 case nir_op_f2b:
1060 qir_SF(c, src[0]);
1061 result = qir_SEL(c, QPU_COND_ZC,
1062 qir_uniform_ui(c, ~0),
1063 qir_uniform_ui(c, 0));
1064 break;
1065
1066 case nir_op_iadd:
1067 result = qir_ADD(c, src[0], src[1]);
1068 break;
1069 case nir_op_ushr:
1070 result = qir_SHR(c, src[0], src[1]);
1071 break;
1072 case nir_op_isub:
1073 result = qir_SUB(c, src[0], src[1]);
1074 break;
1075 case nir_op_ishr:
1076 result = qir_ASR(c, src[0], src[1]);
1077 break;
1078 case nir_op_ishl:
1079 result = qir_SHL(c, src[0], src[1]);
1080 break;
1081 case nir_op_imin:
1082 result = qir_MIN(c, src[0], src[1]);
1083 break;
1084 case nir_op_imax:
1085 result = qir_MAX(c, src[0], src[1]);
1086 break;
1087 case nir_op_iand:
1088 result = qir_AND(c, src[0], src[1]);
1089 break;
1090 case nir_op_ior:
1091 result = qir_OR(c, src[0], src[1]);
1092 break;
1093 case nir_op_ixor:
1094 result = qir_XOR(c, src[0], src[1]);
1095 break;
1096 case nir_op_inot:
1097 result = qir_NOT(c, src[0]);
1098 break;
1099
1100 case nir_op_imul:
1101 result = ntq_umul(c, src[0], src[1]);
1102 break;
1103
1104 case nir_op_seq:
1105 case nir_op_sne:
1106 case nir_op_sge:
1107 case nir_op_slt:
1108 case nir_op_feq:
1109 case nir_op_fne:
1110 case nir_op_fge:
1111 case nir_op_flt:
1112 case nir_op_ieq:
1113 case nir_op_ine:
1114 case nir_op_ige:
1115 case nir_op_uge:
1116 case nir_op_ilt:
1117 if (!ntq_emit_comparison(c, &result, instr, instr)) {
1118 fprintf(stderr, "Bad comparison instruction\n");
1119 }
1120 break;
1121
1122 case nir_op_bcsel:
1123 result = ntq_emit_bcsel(c, instr, src);
1124 break;
1125 case nir_op_fcsel:
1126 qir_SF(c, src[0]);
1127 result = qir_SEL(c, QPU_COND_ZC, src[1], src[2]);
1128 break;
1129
1130 case nir_op_frcp:
1131 result = ntq_rcp(c, src[0]);
1132 break;
1133 case nir_op_frsq:
1134 result = ntq_rsq(c, src[0]);
1135 break;
1136 case nir_op_fexp2:
1137 result = qir_EXP2(c, src[0]);
1138 break;
1139 case nir_op_flog2:
1140 result = qir_LOG2(c, src[0]);
1141 break;
1142
1143 case nir_op_ftrunc:
1144 result = qir_ITOF(c, qir_FTOI(c, src[0]));
1145 break;
1146 case nir_op_fceil:
1147 result = ntq_fceil(c, src[0]);
1148 break;
1149 case nir_op_ffract:
1150 result = ntq_ffract(c, src[0]);
1151 break;
1152 case nir_op_ffloor:
1153 result = ntq_ffloor(c, src[0]);
1154 break;
1155
1156 case nir_op_fsin:
1157 result = ntq_fsin(c, src[0]);
1158 break;
1159 case nir_op_fcos:
1160 result = ntq_fcos(c, src[0]);
1161 break;
1162
1163 case nir_op_fsign:
1164 result = ntq_fsign(c, src[0]);
1165 break;
1166
1167 case nir_op_fabs:
1168 result = qir_FMAXABS(c, src[0], src[0]);
1169 break;
1170 case nir_op_iabs:
1171 result = qir_MAX(c, src[0],
1172 qir_SUB(c, qir_uniform_ui(c, 0), src[0]));
1173 break;
1174
1175 case nir_op_ibitfield_extract:
1176 result = ntq_emit_ibfe(c, src[0], src[1], src[2]);
1177 break;
1178
1179 case nir_op_ubitfield_extract:
1180 result = ntq_emit_ubfe(c, src[0], src[1], src[2]);
1181 break;
1182
1183 case nir_op_usadd_4x8:
1184 result = qir_V8ADDS(c, src[0], src[1]);
1185 break;
1186
1187 case nir_op_ussub_4x8:
1188 result = qir_V8SUBS(c, src[0], src[1]);
1189 break;
1190
1191 case nir_op_umin_4x8:
1192 result = qir_V8MIN(c, src[0], src[1]);
1193 break;
1194
1195 case nir_op_umax_4x8:
1196 result = qir_V8MAX(c, src[0], src[1]);
1197 break;
1198
1199 case nir_op_umul_unorm_4x8:
1200 result = qir_V8MULD(c, src[0], src[1]);
1201 break;
1202
1203 case nir_op_fddx:
1204 case nir_op_fddx_coarse:
1205 case nir_op_fddx_fine:
1206 result = ntq_fddx(c, src[0]);
1207 break;
1208
1209 case nir_op_fddy:
1210 case nir_op_fddy_coarse:
1211 case nir_op_fddy_fine:
1212 result = ntq_fddy(c, src[0]);
1213 break;
1214
1215 default:
1216 fprintf(stderr, "unknown NIR ALU inst: ");
1217 nir_print_instr(&instr->instr, stderr);
1218 fprintf(stderr, "\n");
1219 abort();
1220 }
1221
1222 /* We have a scalar result, so the instruction should only have a
1223 * single channel written to.
1224 */
1225 assert(util_is_power_of_two(instr->dest.write_mask));
1226 ntq_store_dest(c, &instr->dest.dest,
1227 ffs(instr->dest.write_mask) - 1, result);
1228 }
1229
1230 static void
1231 emit_frag_end(struct vc4_compile *c)
1232 {
1233 struct qreg color;
1234 if (c->output_color_index != -1) {
1235 color = c->outputs[c->output_color_index];
1236 } else {
1237 color = qir_uniform_ui(c, 0);
1238 }
1239
1240 uint32_t discard_cond = QPU_COND_ALWAYS;
1241 if (c->s->info.fs.uses_discard) {
1242 qir_SF(c, c->discard);
1243 discard_cond = QPU_COND_ZS;
1244 }
1245
1246 if (c->fs_key->stencil_enabled) {
1247 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1248 qir_uniform(c, QUNIFORM_STENCIL, 0));
1249 if (c->fs_key->stencil_twoside) {
1250 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1251 qir_uniform(c, QUNIFORM_STENCIL, 1));
1252 }
1253 if (c->fs_key->stencil_full_writemasks) {
1254 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1255 qir_uniform(c, QUNIFORM_STENCIL, 2));
1256 }
1257 }
1258
1259 if (c->output_sample_mask_index != -1) {
1260 qir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1261 }
1262
1263 if (c->fs_key->depth_enabled) {
1264 if (c->output_position_index != -1) {
1265 qir_FTOI_dest(c, qir_reg(QFILE_TLB_Z_WRITE, 0),
1266 qir_FMUL(c,
1267 c->outputs[c->output_position_index],
1268 qir_uniform_f(c, 0xffffff)))->cond = discard_cond;
1269 } else {
1270 qir_MOV_dest(c, qir_reg(QFILE_TLB_Z_WRITE, 0),
1271 qir_FRAG_Z(c))->cond = discard_cond;
1272 }
1273 }
1274
1275 if (!c->msaa_per_sample_output) {
1276 qir_MOV_dest(c, qir_reg(QFILE_TLB_COLOR_WRITE, 0),
1277 color)->cond = discard_cond;
1278 } else {
1279 for (int i = 0; i < VC4_MAX_SAMPLES; i++) {
1280 qir_MOV_dest(c, qir_reg(QFILE_TLB_COLOR_WRITE_MS, 0),
1281 c->sample_colors[i])->cond = discard_cond;
1282 }
1283 }
1284 }
1285
1286 static void
1287 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1288 {
1289 struct qreg packed = qir_get_temp(c);
1290
1291 for (int i = 0; i < 2; i++) {
1292 struct qreg scale =
1293 qir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1294
1295 struct qreg packed_chan = packed;
1296 packed_chan.pack = QPU_PACK_A_16A + i;
1297
1298 qir_FTOI_dest(c, packed_chan,
1299 qir_FMUL(c,
1300 qir_FMUL(c,
1301 c->outputs[c->output_position_index + i],
1302 scale),
1303 rcp_w));
1304 }
1305
1306 qir_VPM_WRITE(c, packed);
1307 }
1308
1309 static void
1310 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1311 {
1312 struct qreg zscale = qir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1313 struct qreg zoffset = qir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1314
1315 qir_VPM_WRITE(c, qir_FADD(c, qir_FMUL(c, qir_FMUL(c,
1316 c->outputs[c->output_position_index + 2],
1317 zscale),
1318 rcp_w),
1319 zoffset));
1320 }
1321
1322 static void
1323 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1324 {
1325 qir_VPM_WRITE(c, rcp_w);
1326 }
1327
1328 static void
1329 emit_point_size_write(struct vc4_compile *c)
1330 {
1331 struct qreg point_size;
1332
1333 if (c->output_point_size_index != -1)
1334 point_size = c->outputs[c->output_point_size_index];
1335 else
1336 point_size = qir_uniform_f(c, 1.0);
1337
1338 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1339 * BCM21553).
1340 */
1341 point_size = qir_FMAX(c, point_size, qir_uniform_f(c, .125));
1342
1343 qir_VPM_WRITE(c, point_size);
1344 }
1345
1346 /**
1347 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1348 *
1349 * The simulator insists that there be at least one vertex attribute, so
1350 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also
1351 * insists that all vertex attributes loaded get read by the VS/CS, so we have
1352 * to consume it here.
1353 */
1354 static void
1355 emit_stub_vpm_read(struct vc4_compile *c)
1356 {
1357 if (c->num_inputs)
1358 return;
1359
1360 c->vattr_sizes[0] = 4;
1361 (void)qir_MOV(c, qir_reg(QFILE_VPM, 0));
1362 c->num_inputs++;
1363 }
1364
1365 static void
1366 emit_vert_end(struct vc4_compile *c,
1367 struct vc4_varying_slot *fs_inputs,
1368 uint32_t num_fs_inputs)
1369 {
1370 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1371
1372 emit_stub_vpm_read(c);
1373
1374 emit_scaled_viewport_write(c, rcp_w);
1375 emit_zs_write(c, rcp_w);
1376 emit_rcp_wc_write(c, rcp_w);
1377 if (c->vs_key->per_vertex_point_size)
1378 emit_point_size_write(c);
1379
1380 for (int i = 0; i < num_fs_inputs; i++) {
1381 struct vc4_varying_slot *input = &fs_inputs[i];
1382 int j;
1383
1384 for (j = 0; j < c->num_outputs; j++) {
1385 struct vc4_varying_slot *output =
1386 &c->output_slots[j];
1387
1388 if (input->slot == output->slot &&
1389 input->swizzle == output->swizzle) {
1390 qir_VPM_WRITE(c, c->outputs[j]);
1391 break;
1392 }
1393 }
1394 /* Emit padding if we didn't find a declared VS output for
1395 * this FS input.
1396 */
1397 if (j == c->num_outputs)
1398 qir_VPM_WRITE(c, qir_uniform_f(c, 0.0));
1399 }
1400 }
1401
1402 static void
1403 emit_coord_end(struct vc4_compile *c)
1404 {
1405 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1406
1407 emit_stub_vpm_read(c);
1408
1409 for (int i = 0; i < 4; i++)
1410 qir_VPM_WRITE(c, c->outputs[c->output_position_index + i]);
1411
1412 emit_scaled_viewport_write(c, rcp_w);
1413 emit_zs_write(c, rcp_w);
1414 emit_rcp_wc_write(c, rcp_w);
1415 if (c->vs_key->per_vertex_point_size)
1416 emit_point_size_write(c);
1417 }
1418
1419 static void
1420 vc4_optimize_nir(struct nir_shader *s)
1421 {
1422 bool progress;
1423
1424 do {
1425 progress = false;
1426
1427 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1428 NIR_PASS(progress, s, nir_lower_alu_to_scalar);
1429 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1430 NIR_PASS(progress, s, nir_copy_prop);
1431 NIR_PASS(progress, s, nir_opt_remove_phis);
1432 NIR_PASS(progress, s, nir_opt_dce);
1433 NIR_PASS(progress, s, nir_opt_dead_cf);
1434 NIR_PASS(progress, s, nir_opt_cse);
1435 NIR_PASS(progress, s, nir_opt_peephole_select, 8);
1436 NIR_PASS(progress, s, nir_opt_algebraic);
1437 NIR_PASS(progress, s, nir_opt_constant_folding);
1438 NIR_PASS(progress, s, nir_opt_undef);
1439 } while (progress);
1440 }
1441
1442 static int
1443 driver_location_compare(const void *in_a, const void *in_b)
1444 {
1445 const nir_variable *const *a = in_a;
1446 const nir_variable *const *b = in_b;
1447
1448 return (*a)->data.driver_location - (*b)->data.driver_location;
1449 }
1450
1451 static void
1452 ntq_setup_inputs(struct vc4_compile *c)
1453 {
1454 unsigned num_entries = 0;
1455 nir_foreach_variable(var, &c->s->inputs)
1456 num_entries++;
1457
1458 nir_variable *vars[num_entries];
1459
1460 unsigned i = 0;
1461 nir_foreach_variable(var, &c->s->inputs)
1462 vars[i++] = var;
1463
1464 /* Sort the variables so that we emit the input setup in
1465 * driver_location order. This is required for VPM reads, whose data
1466 * is fetched into the VPM in driver_location (TGSI register index)
1467 * order.
1468 */
1469 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1470
1471 for (unsigned i = 0; i < num_entries; i++) {
1472 nir_variable *var = vars[i];
1473 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1474 unsigned loc = var->data.driver_location;
1475
1476 assert(array_len == 1);
1477 (void)array_len;
1478 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1479 (loc + 1) * 4);
1480
1481 if (c->stage == QSTAGE_FRAG) {
1482 if (var->data.location == VARYING_SLOT_POS) {
1483 emit_fragcoord_input(c, loc);
1484 } else if (var->data.location == VARYING_SLOT_PNTC ||
1485 (var->data.location >= VARYING_SLOT_VAR0 &&
1486 (c->fs_key->point_sprite_mask &
1487 (1 << (var->data.location -
1488 VARYING_SLOT_VAR0))))) {
1489 c->inputs[loc * 4 + 0] = c->point_x;
1490 c->inputs[loc * 4 + 1] = c->point_y;
1491 } else {
1492 emit_fragment_input(c, loc, var->data.location);
1493 }
1494 } else {
1495 emit_vertex_input(c, loc);
1496 }
1497 }
1498 }
1499
1500 static void
1501 ntq_setup_outputs(struct vc4_compile *c)
1502 {
1503 nir_foreach_variable(var, &c->s->outputs) {
1504 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1505 unsigned loc = var->data.driver_location * 4;
1506
1507 assert(array_len == 1);
1508 (void)array_len;
1509
1510 for (int i = 0; i < 4; i++)
1511 add_output(c, loc + i, var->data.location, i);
1512
1513 if (c->stage == QSTAGE_FRAG) {
1514 switch (var->data.location) {
1515 case FRAG_RESULT_COLOR:
1516 case FRAG_RESULT_DATA0:
1517 c->output_color_index = loc;
1518 break;
1519 case FRAG_RESULT_DEPTH:
1520 c->output_position_index = loc;
1521 break;
1522 case FRAG_RESULT_SAMPLE_MASK:
1523 c->output_sample_mask_index = loc;
1524 break;
1525 }
1526 } else {
1527 switch (var->data.location) {
1528 case VARYING_SLOT_POS:
1529 c->output_position_index = loc;
1530 break;
1531 case VARYING_SLOT_PSIZ:
1532 c->output_point_size_index = loc;
1533 break;
1534 }
1535 }
1536 }
1537 }
1538
1539 static void
1540 ntq_setup_uniforms(struct vc4_compile *c)
1541 {
1542 nir_foreach_variable(var, &c->s->uniforms) {
1543 uint32_t vec4_count = st_glsl_type_size(var->type);
1544 unsigned vec4_size = 4 * sizeof(float);
1545
1546 declare_uniform_range(c, var->data.driver_location * vec4_size,
1547 vec4_count * vec4_size);
1548
1549 }
1550 }
1551
1552 /**
1553 * Sets up the mapping from nir_register to struct qreg *.
1554 *
1555 * Each nir_register gets a struct qreg per 32-bit component being stored.
1556 */
1557 static void
1558 ntq_setup_registers(struct vc4_compile *c, struct exec_list *list)
1559 {
1560 foreach_list_typed(nir_register, nir_reg, node, list) {
1561 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1562 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1563 array_len *
1564 nir_reg->num_components);
1565
1566 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1567
1568 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1569 qregs[i] = qir_get_temp(c);
1570 }
1571 }
1572
1573 static void
1574 ntq_emit_load_const(struct vc4_compile *c, nir_load_const_instr *instr)
1575 {
1576 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1577 for (int i = 0; i < instr->def.num_components; i++)
1578 qregs[i] = qir_uniform_ui(c, instr->value.u32[i]);
1579
1580 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1581 }
1582
1583 static void
1584 ntq_emit_ssa_undef(struct vc4_compile *c, nir_ssa_undef_instr *instr)
1585 {
1586 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1587
1588 /* QIR needs there to be *some* value, so pick 0 (same as for
1589 * ntq_setup_registers().
1590 */
1591 for (int i = 0; i < instr->def.num_components; i++)
1592 qregs[i] = qir_uniform_ui(c, 0);
1593 }
1594
1595 static void
1596 ntq_emit_intrinsic(struct vc4_compile *c, nir_intrinsic_instr *instr)
1597 {
1598 nir_const_value *const_offset;
1599 unsigned offset;
1600
1601 switch (instr->intrinsic) {
1602 case nir_intrinsic_load_uniform:
1603 assert(instr->num_components == 1);
1604 const_offset = nir_src_as_const_value(instr->src[0]);
1605 if (const_offset) {
1606 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1607 assert(offset % 4 == 0);
1608 /* We need dwords */
1609 offset = offset / 4;
1610 ntq_store_dest(c, &instr->dest, 0,
1611 qir_uniform(c, QUNIFORM_UNIFORM,
1612 offset));
1613 } else {
1614 ntq_store_dest(c, &instr->dest, 0,
1615 indirect_uniform_load(c, instr));
1616 }
1617 break;
1618
1619 case nir_intrinsic_load_user_clip_plane:
1620 for (int i = 0; i < instr->num_components; i++) {
1621 ntq_store_dest(c, &instr->dest, i,
1622 qir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1623 nir_intrinsic_ucp_id(instr) *
1624 4 + i));
1625 }
1626 break;
1627
1628 case nir_intrinsic_load_blend_const_color_r_float:
1629 case nir_intrinsic_load_blend_const_color_g_float:
1630 case nir_intrinsic_load_blend_const_color_b_float:
1631 case nir_intrinsic_load_blend_const_color_a_float:
1632 ntq_store_dest(c, &instr->dest, 0,
1633 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_X +
1634 (instr->intrinsic -
1635 nir_intrinsic_load_blend_const_color_r_float),
1636 0));
1637 break;
1638
1639 case nir_intrinsic_load_blend_const_color_rgba8888_unorm:
1640 ntq_store_dest(c, &instr->dest, 0,
1641 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_RGBA,
1642 0));
1643 break;
1644
1645 case nir_intrinsic_load_blend_const_color_aaaa8888_unorm:
1646 ntq_store_dest(c, &instr->dest, 0,
1647 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_AAAA,
1648 0));
1649 break;
1650
1651 case nir_intrinsic_load_alpha_ref_float:
1652 ntq_store_dest(c, &instr->dest, 0,
1653 qir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1654 break;
1655
1656 case nir_intrinsic_load_sample_mask_in:
1657 ntq_store_dest(c, &instr->dest, 0,
1658 qir_uniform(c, QUNIFORM_SAMPLE_MASK, 0));
1659 break;
1660
1661 case nir_intrinsic_load_front_face:
1662 /* The register contains 0 (front) or 1 (back), and we need to
1663 * turn it into a NIR bool where true means front.
1664 */
1665 ntq_store_dest(c, &instr->dest, 0,
1666 qir_ADD(c,
1667 qir_uniform_ui(c, -1),
1668 qir_reg(QFILE_FRAG_REV_FLAG, 0)));
1669 break;
1670
1671 case nir_intrinsic_load_input:
1672 assert(instr->num_components == 1);
1673 const_offset = nir_src_as_const_value(instr->src[0]);
1674 assert(const_offset && "vc4 doesn't support indirect inputs");
1675 if (c->stage == QSTAGE_FRAG &&
1676 nir_intrinsic_base(instr) >= VC4_NIR_TLB_COLOR_READ_INPUT) {
1677 assert(const_offset->u32[0] == 0);
1678 /* Reads of the per-sample color need to be done in
1679 * order.
1680 */
1681 int sample_index = (nir_intrinsic_base(instr) -
1682 VC4_NIR_TLB_COLOR_READ_INPUT);
1683 for (int i = 0; i <= sample_index; i++) {
1684 if (c->color_reads[i].file == QFILE_NULL) {
1685 c->color_reads[i] =
1686 qir_TLB_COLOR_READ(c);
1687 }
1688 }
1689 ntq_store_dest(c, &instr->dest, 0,
1690 c->color_reads[sample_index]);
1691 } else {
1692 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1693 int comp = nir_intrinsic_component(instr);
1694 ntq_store_dest(c, &instr->dest, 0,
1695 c->inputs[offset * 4 + comp]);
1696 }
1697 break;
1698
1699 case nir_intrinsic_store_output:
1700 const_offset = nir_src_as_const_value(instr->src[1]);
1701 assert(const_offset && "vc4 doesn't support indirect outputs");
1702 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1703
1704 /* MSAA color outputs are the only case where we have an
1705 * output that's not lowered to being a store of a single 32
1706 * bit value.
1707 */
1708 if (c->stage == QSTAGE_FRAG && instr->num_components == 4) {
1709 assert(offset == c->output_color_index);
1710 for (int i = 0; i < 4; i++) {
1711 c->sample_colors[i] =
1712 qir_MOV(c, ntq_get_src(c, instr->src[0],
1713 i));
1714 }
1715 } else {
1716 offset = offset * 4 + nir_intrinsic_component(instr);
1717 assert(instr->num_components == 1);
1718 c->outputs[offset] =
1719 qir_MOV(c, ntq_get_src(c, instr->src[0], 0));
1720 c->num_outputs = MAX2(c->num_outputs, offset + 1);
1721 }
1722 break;
1723
1724 case nir_intrinsic_discard:
1725 if (c->execute.file != QFILE_NULL) {
1726 qir_SF(c, c->execute);
1727 qir_MOV_cond(c, QPU_COND_ZS, c->discard,
1728 qir_uniform_ui(c, ~0));
1729 } else {
1730 qir_MOV_dest(c, c->discard, qir_uniform_ui(c, ~0));
1731 }
1732 break;
1733
1734 case nir_intrinsic_discard_if: {
1735 /* true (~0) if we're discarding */
1736 struct qreg cond = ntq_get_src(c, instr->src[0], 0);
1737
1738 if (c->execute.file != QFILE_NULL) {
1739 /* execute == 0 means the channel is active. Invert
1740 * the condition so that we can use zero as "executing
1741 * and discarding."
1742 */
1743 qir_SF(c, qir_AND(c, c->execute, qir_NOT(c, cond)));
1744 qir_MOV_cond(c, QPU_COND_ZS, c->discard, cond);
1745 } else {
1746 qir_OR_dest(c, c->discard, c->discard,
1747 ntq_get_src(c, instr->src[0], 0));
1748 }
1749
1750 break;
1751 }
1752
1753 default:
1754 fprintf(stderr, "Unknown intrinsic: ");
1755 nir_print_instr(&instr->instr, stderr);
1756 fprintf(stderr, "\n");
1757 break;
1758 }
1759 }
1760
1761 /* Clears (activates) the execute flags for any channels whose jump target
1762 * matches this block.
1763 */
1764 static void
1765 ntq_activate_execute_for_block(struct vc4_compile *c)
1766 {
1767 qir_SF(c, qir_SUB(c,
1768 c->execute,
1769 qir_uniform_ui(c, c->cur_block->index)));
1770 qir_MOV_cond(c, QPU_COND_ZS, c->execute, qir_uniform_ui(c, 0));
1771 }
1772
1773 static void
1774 ntq_emit_if(struct vc4_compile *c, nir_if *if_stmt)
1775 {
1776 if (!c->vc4->screen->has_control_flow) {
1777 fprintf(stderr,
1778 "IF statement support requires updated kernel.\n");
1779 return;
1780 }
1781
1782 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
1783 bool empty_else_block =
1784 (nir_else_block == nir_if_last_else_block(if_stmt) &&
1785 exec_list_is_empty(&nir_else_block->instr_list));
1786
1787 struct qblock *then_block = qir_new_block(c);
1788 struct qblock *after_block = qir_new_block(c);
1789 struct qblock *else_block;
1790 if (empty_else_block)
1791 else_block = after_block;
1792 else
1793 else_block = qir_new_block(c);
1794
1795 bool was_top_level = false;
1796 if (c->execute.file == QFILE_NULL) {
1797 c->execute = qir_MOV(c, qir_uniform_ui(c, 0));
1798 was_top_level = true;
1799 }
1800
1801 /* Set ZS for executing (execute == 0) and jumping (if->condition ==
1802 * 0) channels, and then update execute flags for those to point to
1803 * the ELSE block.
1804 */
1805 qir_SF(c, qir_OR(c,
1806 c->execute,
1807 ntq_get_src(c, if_stmt->condition, 0)));
1808 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
1809 qir_uniform_ui(c, else_block->index));
1810
1811 /* Jump to ELSE if nothing is active for THEN, otherwise fall
1812 * through.
1813 */
1814 qir_SF(c, c->execute);
1815 qir_BRANCH(c, QPU_COND_BRANCH_ALL_ZC);
1816 qir_link_blocks(c->cur_block, else_block);
1817 qir_link_blocks(c->cur_block, then_block);
1818
1819 /* Process the THEN block. */
1820 qir_set_emit_block(c, then_block);
1821 ntq_emit_cf_list(c, &if_stmt->then_list);
1822
1823 if (!empty_else_block) {
1824 /* Handle the end of the THEN block. First, all currently
1825 * active channels update their execute flags to point to
1826 * ENDIF
1827 */
1828 qir_SF(c, c->execute);
1829 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
1830 qir_uniform_ui(c, after_block->index));
1831
1832 /* If everything points at ENDIF, then jump there immediately. */
1833 qir_SF(c, qir_SUB(c, c->execute, qir_uniform_ui(c, after_block->index)));
1834 qir_BRANCH(c, QPU_COND_BRANCH_ALL_ZS);
1835 qir_link_blocks(c->cur_block, after_block);
1836 qir_link_blocks(c->cur_block, else_block);
1837
1838 qir_set_emit_block(c, else_block);
1839 ntq_activate_execute_for_block(c);
1840 ntq_emit_cf_list(c, &if_stmt->else_list);
1841 }
1842
1843 qir_link_blocks(c->cur_block, after_block);
1844
1845 qir_set_emit_block(c, after_block);
1846 if (was_top_level)
1847 c->execute = c->undef;
1848 else
1849 ntq_activate_execute_for_block(c);
1850
1851 }
1852
1853 static void
1854 ntq_emit_jump(struct vc4_compile *c, nir_jump_instr *jump)
1855 {
1856 switch (jump->type) {
1857 case nir_jump_break:
1858 qir_SF(c, c->execute);
1859 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
1860 qir_uniform_ui(c, c->loop_break_block->index));
1861 break;
1862
1863 case nir_jump_continue:
1864 qir_SF(c, c->execute);
1865 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
1866 qir_uniform_ui(c, c->loop_cont_block->index));
1867 break;
1868
1869 case nir_jump_return:
1870 unreachable("All returns shouold be lowered\n");
1871 }
1872 }
1873
1874 static void
1875 ntq_emit_instr(struct vc4_compile *c, nir_instr *instr)
1876 {
1877 switch (instr->type) {
1878 case nir_instr_type_alu:
1879 ntq_emit_alu(c, nir_instr_as_alu(instr));
1880 break;
1881
1882 case nir_instr_type_intrinsic:
1883 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
1884 break;
1885
1886 case nir_instr_type_load_const:
1887 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
1888 break;
1889
1890 case nir_instr_type_ssa_undef:
1891 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
1892 break;
1893
1894 case nir_instr_type_tex:
1895 ntq_emit_tex(c, nir_instr_as_tex(instr));
1896 break;
1897
1898 case nir_instr_type_jump:
1899 ntq_emit_jump(c, nir_instr_as_jump(instr));
1900 break;
1901
1902 default:
1903 fprintf(stderr, "Unknown NIR instr type: ");
1904 nir_print_instr(instr, stderr);
1905 fprintf(stderr, "\n");
1906 abort();
1907 }
1908 }
1909
1910 static void
1911 ntq_emit_block(struct vc4_compile *c, nir_block *block)
1912 {
1913 nir_foreach_instr(instr, block) {
1914 ntq_emit_instr(c, instr);
1915 }
1916 }
1917
1918 static void ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list);
1919
1920 static void
1921 ntq_emit_loop(struct vc4_compile *c, nir_loop *loop)
1922 {
1923 if (!c->vc4->screen->has_control_flow) {
1924 fprintf(stderr,
1925 "loop support requires updated kernel.\n");
1926 ntq_emit_cf_list(c, &loop->body);
1927 return;
1928 }
1929
1930 bool was_top_level = false;
1931 if (c->execute.file == QFILE_NULL) {
1932 c->execute = qir_MOV(c, qir_uniform_ui(c, 0));
1933 was_top_level = true;
1934 }
1935
1936 struct qblock *save_loop_cont_block = c->loop_cont_block;
1937 struct qblock *save_loop_break_block = c->loop_break_block;
1938
1939 c->loop_cont_block = qir_new_block(c);
1940 c->loop_break_block = qir_new_block(c);
1941
1942 qir_link_blocks(c->cur_block, c->loop_cont_block);
1943 qir_set_emit_block(c, c->loop_cont_block);
1944 ntq_activate_execute_for_block(c);
1945
1946 ntq_emit_cf_list(c, &loop->body);
1947
1948 /* If anything had explicitly continued, or is here at the end of the
1949 * loop, then we need to loop again. SF updates are masked by the
1950 * instruction's condition, so we can do the OR of the two conditions
1951 * within SF.
1952 */
1953 qir_SF(c, c->execute);
1954 struct qinst *cont_check =
1955 qir_SUB_dest(c,
1956 c->undef,
1957 c->execute,
1958 qir_uniform_ui(c, c->loop_cont_block->index));
1959 cont_check->cond = QPU_COND_ZC;
1960 cont_check->sf = true;
1961
1962 qir_BRANCH(c, QPU_COND_BRANCH_ANY_ZS);
1963 qir_link_blocks(c->cur_block, c->loop_cont_block);
1964 qir_link_blocks(c->cur_block, c->loop_break_block);
1965
1966 qir_set_emit_block(c, c->loop_break_block);
1967 if (was_top_level)
1968 c->execute = c->undef;
1969 else
1970 ntq_activate_execute_for_block(c);
1971
1972 c->loop_break_block = save_loop_break_block;
1973 c->loop_cont_block = save_loop_cont_block;
1974 }
1975
1976 static void
1977 ntq_emit_function(struct vc4_compile *c, nir_function_impl *func)
1978 {
1979 fprintf(stderr, "FUNCTIONS not handled.\n");
1980 abort();
1981 }
1982
1983 static void
1984 ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list)
1985 {
1986 foreach_list_typed(nir_cf_node, node, node, list) {
1987 switch (node->type) {
1988 case nir_cf_node_block:
1989 ntq_emit_block(c, nir_cf_node_as_block(node));
1990 break;
1991
1992 case nir_cf_node_if:
1993 ntq_emit_if(c, nir_cf_node_as_if(node));
1994 break;
1995
1996 case nir_cf_node_loop:
1997 ntq_emit_loop(c, nir_cf_node_as_loop(node));
1998 break;
1999
2000 case nir_cf_node_function:
2001 ntq_emit_function(c, nir_cf_node_as_function(node));
2002 break;
2003
2004 default:
2005 fprintf(stderr, "Unknown NIR node type\n");
2006 abort();
2007 }
2008 }
2009 }
2010
2011 static void
2012 ntq_emit_impl(struct vc4_compile *c, nir_function_impl *impl)
2013 {
2014 ntq_setup_registers(c, &impl->registers);
2015 ntq_emit_cf_list(c, &impl->body);
2016 }
2017
2018 static void
2019 nir_to_qir(struct vc4_compile *c)
2020 {
2021 if (c->stage == QSTAGE_FRAG && c->s->info.fs.uses_discard)
2022 c->discard = qir_MOV(c, qir_uniform_ui(c, 0));
2023
2024 ntq_setup_inputs(c);
2025 ntq_setup_outputs(c);
2026 ntq_setup_uniforms(c);
2027 ntq_setup_registers(c, &c->s->registers);
2028
2029 /* Find the main function and emit the body. */
2030 nir_foreach_function(function, c->s) {
2031 assert(strcmp(function->name, "main") == 0);
2032 assert(function->impl);
2033 ntq_emit_impl(c, function->impl);
2034 }
2035 }
2036
2037 static const nir_shader_compiler_options nir_options = {
2038 .lower_extract_byte = true,
2039 .lower_extract_word = true,
2040 .lower_ffma = true,
2041 .lower_flrp32 = true,
2042 .lower_fpow = true,
2043 .lower_fsat = true,
2044 .lower_fsqrt = true,
2045 .lower_negate = true,
2046 .native_integers = true,
2047 };
2048
2049 const void *
2050 vc4_screen_get_compiler_options(struct pipe_screen *pscreen,
2051 enum pipe_shader_ir ir, unsigned shader)
2052 {
2053 return &nir_options;
2054 }
2055
2056 static int
2057 count_nir_instrs(nir_shader *nir)
2058 {
2059 int count = 0;
2060 nir_foreach_function(function, nir) {
2061 if (!function->impl)
2062 continue;
2063 nir_foreach_block(block, function->impl) {
2064 nir_foreach_instr(instr, block)
2065 count++;
2066 }
2067 }
2068 return count;
2069 }
2070
2071 static struct vc4_compile *
2072 vc4_shader_ntq(struct vc4_context *vc4, enum qstage stage,
2073 struct vc4_key *key)
2074 {
2075 struct vc4_compile *c = qir_compile_init();
2076
2077 c->vc4 = vc4;
2078 c->stage = stage;
2079 c->shader_state = &key->shader_state->base;
2080 c->program_id = key->shader_state->program_id;
2081 c->variant_id =
2082 p_atomic_inc_return(&key->shader_state->compiled_variant_count);
2083
2084 c->key = key;
2085 switch (stage) {
2086 case QSTAGE_FRAG:
2087 c->fs_key = (struct vc4_fs_key *)key;
2088 if (c->fs_key->is_points) {
2089 c->point_x = emit_fragment_varying(c, ~0, 0);
2090 c->point_y = emit_fragment_varying(c, ~0, 0);
2091 } else if (c->fs_key->is_lines) {
2092 c->line_x = emit_fragment_varying(c, ~0, 0);
2093 }
2094 break;
2095 case QSTAGE_VERT:
2096 c->vs_key = (struct vc4_vs_key *)key;
2097 break;
2098 case QSTAGE_COORD:
2099 c->vs_key = (struct vc4_vs_key *)key;
2100 break;
2101 }
2102
2103 c->s = nir_shader_clone(c, key->shader_state->base.ir.nir);
2104
2105 if (stage == QSTAGE_FRAG)
2106 NIR_PASS_V(c->s, vc4_nir_lower_blend, c);
2107
2108 struct nir_lower_tex_options tex_options = {
2109 /* We would need to implement txs, but we don't want the
2110 * int/float conversions
2111 */
2112 .lower_rect = false,
2113
2114 .lower_txp = ~0,
2115
2116 /* Apply swizzles to all samplers. */
2117 .swizzle_result = ~0,
2118 };
2119
2120 /* Lower the format swizzle and ARB_texture_swizzle-style swizzle.
2121 * The format swizzling applies before sRGB decode, and
2122 * ARB_texture_swizzle is the last thing before returning the sample.
2123 */
2124 for (int i = 0; i < ARRAY_SIZE(key->tex); i++) {
2125 enum pipe_format format = c->key->tex[i].format;
2126
2127 if (!format)
2128 continue;
2129
2130 const uint8_t *format_swizzle = vc4_get_format_swizzle(format);
2131
2132 for (int j = 0; j < 4; j++) {
2133 uint8_t arb_swiz = c->key->tex[i].swizzle[j];
2134
2135 if (arb_swiz <= 3) {
2136 tex_options.swizzles[i][j] =
2137 format_swizzle[arb_swiz];
2138 } else {
2139 tex_options.swizzles[i][j] = arb_swiz;
2140 }
2141 }
2142
2143 if (util_format_is_srgb(format))
2144 tex_options.lower_srgb |= (1 << i);
2145 }
2146
2147 NIR_PASS_V(c->s, nir_lower_tex, &tex_options);
2148
2149 if (c->fs_key && c->fs_key->light_twoside)
2150 NIR_PASS_V(c->s, nir_lower_two_sided_color);
2151
2152 if (c->vs_key && c->vs_key->clamp_color)
2153 NIR_PASS_V(c->s, nir_lower_clamp_color_outputs);
2154
2155 if (c->key->ucp_enables) {
2156 if (stage == QSTAGE_FRAG) {
2157 NIR_PASS_V(c->s, nir_lower_clip_fs, c->key->ucp_enables);
2158 } else {
2159 NIR_PASS_V(c->s, nir_lower_clip_vs, c->key->ucp_enables);
2160 NIR_PASS_V(c->s, nir_lower_io_to_scalar,
2161 nir_var_shader_out);
2162 }
2163 }
2164
2165 /* FS input scalarizing must happen after nir_lower_two_sided_color,
2166 * which only handles a vec4 at a time. Similarly, VS output
2167 * scalarizing must happen after nir_lower_clip_vs.
2168 */
2169 if (c->stage == QSTAGE_FRAG)
2170 NIR_PASS_V(c->s, nir_lower_io_to_scalar, nir_var_shader_in);
2171 else
2172 NIR_PASS_V(c->s, nir_lower_io_to_scalar, nir_var_shader_out);
2173
2174 NIR_PASS_V(c->s, vc4_nir_lower_io, c);
2175 NIR_PASS_V(c->s, vc4_nir_lower_txf_ms, c);
2176 NIR_PASS_V(c->s, nir_lower_idiv);
2177
2178 vc4_optimize_nir(c->s);
2179
2180 NIR_PASS_V(c->s, nir_convert_from_ssa, true);
2181
2182 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2183 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d NIR instructions\n",
2184 qir_get_stage_name(c->stage),
2185 c->program_id, c->variant_id,
2186 count_nir_instrs(c->s));
2187 }
2188
2189 if (vc4_debug & VC4_DEBUG_NIR) {
2190 fprintf(stderr, "%s prog %d/%d NIR:\n",
2191 qir_get_stage_name(c->stage),
2192 c->program_id, c->variant_id);
2193 nir_print_shader(c->s, stderr);
2194 }
2195
2196 nir_to_qir(c);
2197
2198 switch (stage) {
2199 case QSTAGE_FRAG:
2200 emit_frag_end(c);
2201 break;
2202 case QSTAGE_VERT:
2203 emit_vert_end(c,
2204 c->vs_key->fs_inputs->input_slots,
2205 c->vs_key->fs_inputs->num_inputs);
2206 break;
2207 case QSTAGE_COORD:
2208 emit_coord_end(c);
2209 break;
2210 }
2211
2212 if (vc4_debug & VC4_DEBUG_QIR) {
2213 fprintf(stderr, "%s prog %d/%d pre-opt QIR:\n",
2214 qir_get_stage_name(c->stage),
2215 c->program_id, c->variant_id);
2216 qir_dump(c);
2217 fprintf(stderr, "\n");
2218 }
2219
2220 qir_optimize(c);
2221 qir_lower_uniforms(c);
2222
2223 qir_schedule_instructions(c);
2224 qir_emit_uniform_stream_resets(c);
2225
2226 if (vc4_debug & VC4_DEBUG_QIR) {
2227 fprintf(stderr, "%s prog %d/%d QIR:\n",
2228 qir_get_stage_name(c->stage),
2229 c->program_id, c->variant_id);
2230 qir_dump(c);
2231 fprintf(stderr, "\n");
2232 }
2233
2234 qir_reorder_uniforms(c);
2235 vc4_generate_code(vc4, c);
2236
2237 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2238 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d instructions\n",
2239 qir_get_stage_name(c->stage),
2240 c->program_id, c->variant_id,
2241 c->qpu_inst_count);
2242 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d uniforms\n",
2243 qir_get_stage_name(c->stage),
2244 c->program_id, c->variant_id,
2245 c->num_uniforms);
2246 }
2247
2248 ralloc_free(c->s);
2249
2250 return c;
2251 }
2252
2253 static void *
2254 vc4_shader_state_create(struct pipe_context *pctx,
2255 const struct pipe_shader_state *cso)
2256 {
2257 struct vc4_context *vc4 = vc4_context(pctx);
2258 struct vc4_uncompiled_shader *so = CALLOC_STRUCT(vc4_uncompiled_shader);
2259 if (!so)
2260 return NULL;
2261
2262 so->program_id = vc4->next_uncompiled_program_id++;
2263
2264 nir_shader *s;
2265
2266 if (cso->type == PIPE_SHADER_IR_NIR) {
2267 /* The backend takes ownership of the NIR shader on state
2268 * creation.
2269 */
2270 s = cso->ir.nir;
2271 } else {
2272 assert(cso->type == PIPE_SHADER_IR_TGSI);
2273
2274 if (vc4_debug & VC4_DEBUG_TGSI) {
2275 fprintf(stderr, "prog %d TGSI:\n",
2276 so->program_id);
2277 tgsi_dump(cso->tokens, 0);
2278 fprintf(stderr, "\n");
2279 }
2280 s = tgsi_to_nir(cso->tokens, &nir_options);
2281 }
2282
2283 NIR_PASS_V(s, nir_opt_global_to_local);
2284 NIR_PASS_V(s, nir_convert_to_ssa);
2285 NIR_PASS_V(s, nir_normalize_cubemap_coords);
2286
2287 NIR_PASS_V(s, nir_lower_load_const_to_scalar);
2288
2289 vc4_optimize_nir(s);
2290
2291 NIR_PASS_V(s, nir_remove_dead_variables, nir_var_local);
2292
2293 /* Garbage collect dead instructions */
2294 nir_sweep(s);
2295
2296 so->base.type = PIPE_SHADER_IR_NIR;
2297 so->base.ir.nir = s;
2298
2299 if (vc4_debug & VC4_DEBUG_NIR) {
2300 fprintf(stderr, "%s prog %d NIR:\n",
2301 gl_shader_stage_name(s->stage),
2302 so->program_id);
2303 nir_print_shader(s, stderr);
2304 fprintf(stderr, "\n");
2305 }
2306
2307 return so;
2308 }
2309
2310 static void
2311 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
2312 struct vc4_compile *c)
2313 {
2314 int count = c->num_uniforms;
2315 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
2316
2317 uinfo->count = count;
2318 uinfo->data = ralloc_array(shader, uint32_t, count);
2319 memcpy(uinfo->data, c->uniform_data,
2320 count * sizeof(*uinfo->data));
2321 uinfo->contents = ralloc_array(shader, enum quniform_contents, count);
2322 memcpy(uinfo->contents, c->uniform_contents,
2323 count * sizeof(*uinfo->contents));
2324 uinfo->num_texture_samples = c->num_texture_samples;
2325
2326 vc4_set_shader_uniform_dirty_flags(shader);
2327 }
2328
2329 static void
2330 vc4_setup_compiled_fs_inputs(struct vc4_context *vc4, struct vc4_compile *c,
2331 struct vc4_compiled_shader *shader)
2332 {
2333 struct vc4_fs_inputs inputs;
2334
2335 memset(&inputs, 0, sizeof(inputs));
2336 inputs.input_slots = ralloc_array(shader,
2337 struct vc4_varying_slot,
2338 c->num_input_slots);
2339
2340 bool input_live[c->num_input_slots];
2341
2342 memset(input_live, 0, sizeof(input_live));
2343 qir_for_each_inst_inorder(inst, c) {
2344 for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) {
2345 if (inst->src[i].file == QFILE_VARY)
2346 input_live[inst->src[i].index] = true;
2347 }
2348 }
2349
2350 for (int i = 0; i < c->num_input_slots; i++) {
2351 struct vc4_varying_slot *slot = &c->input_slots[i];
2352
2353 if (!input_live[i])
2354 continue;
2355
2356 /* Skip non-VS-output inputs. */
2357 if (slot->slot == (uint8_t)~0)
2358 continue;
2359
2360 if (slot->slot == VARYING_SLOT_COL0 ||
2361 slot->slot == VARYING_SLOT_COL1 ||
2362 slot->slot == VARYING_SLOT_BFC0 ||
2363 slot->slot == VARYING_SLOT_BFC1) {
2364 shader->color_inputs |= (1 << inputs.num_inputs);
2365 }
2366
2367 inputs.input_slots[inputs.num_inputs] = *slot;
2368 inputs.num_inputs++;
2369 }
2370 shader->num_inputs = inputs.num_inputs;
2371
2372 /* Add our set of inputs to the set of all inputs seen. This way, we
2373 * can have a single pointer that identifies an FS inputs set,
2374 * allowing VS to avoid recompiling when the FS is recompiled (or a
2375 * new one is bound using separate shader objects) but the inputs
2376 * don't change.
2377 */
2378 struct set_entry *entry = _mesa_set_search(vc4->fs_inputs_set, &inputs);
2379 if (entry) {
2380 shader->fs_inputs = entry->key;
2381 ralloc_free(inputs.input_slots);
2382 } else {
2383 struct vc4_fs_inputs *alloc_inputs;
2384
2385 alloc_inputs = rzalloc(vc4->fs_inputs_set, struct vc4_fs_inputs);
2386 memcpy(alloc_inputs, &inputs, sizeof(inputs));
2387 ralloc_steal(alloc_inputs, inputs.input_slots);
2388 _mesa_set_add(vc4->fs_inputs_set, alloc_inputs);
2389
2390 shader->fs_inputs = alloc_inputs;
2391 }
2392 }
2393
2394 static struct vc4_compiled_shader *
2395 vc4_get_compiled_shader(struct vc4_context *vc4, enum qstage stage,
2396 struct vc4_key *key)
2397 {
2398 struct hash_table *ht;
2399 uint32_t key_size;
2400 if (stage == QSTAGE_FRAG) {
2401 ht = vc4->fs_cache;
2402 key_size = sizeof(struct vc4_fs_key);
2403 } else {
2404 ht = vc4->vs_cache;
2405 key_size = sizeof(struct vc4_vs_key);
2406 }
2407
2408 struct vc4_compiled_shader *shader;
2409 struct hash_entry *entry = _mesa_hash_table_search(ht, key);
2410 if (entry)
2411 return entry->data;
2412
2413 struct vc4_compile *c = vc4_shader_ntq(vc4, stage, key);
2414 shader = rzalloc(NULL, struct vc4_compiled_shader);
2415
2416 shader->program_id = vc4->next_compiled_program_id++;
2417 if (stage == QSTAGE_FRAG) {
2418 vc4_setup_compiled_fs_inputs(vc4, c, shader);
2419
2420 /* Note: the temporary clone in c->s has been freed. */
2421 nir_shader *orig_shader = key->shader_state->base.ir.nir;
2422 if (orig_shader->info.outputs_written & (1 << FRAG_RESULT_DEPTH))
2423 shader->disable_early_z = true;
2424 } else {
2425 shader->num_inputs = c->num_inputs;
2426
2427 shader->vattr_offsets[0] = 0;
2428 for (int i = 0; i < 8; i++) {
2429 shader->vattr_offsets[i + 1] =
2430 shader->vattr_offsets[i] + c->vattr_sizes[i];
2431
2432 if (c->vattr_sizes[i])
2433 shader->vattrs_live |= (1 << i);
2434 }
2435 }
2436
2437 copy_uniform_state_to_shader(shader, c);
2438 shader->bo = vc4_bo_alloc_shader(vc4->screen, c->qpu_insts,
2439 c->qpu_inst_count * sizeof(uint64_t));
2440
2441 /* Copy the compiler UBO range state to the compiled shader, dropping
2442 * out arrays that were never referenced by an indirect load.
2443 *
2444 * (Note that QIR dead code elimination of an array access still
2445 * leaves that array alive, though)
2446 */
2447 if (c->num_ubo_ranges) {
2448 shader->num_ubo_ranges = c->num_ubo_ranges;
2449 shader->ubo_ranges = ralloc_array(shader, struct vc4_ubo_range,
2450 c->num_ubo_ranges);
2451 uint32_t j = 0;
2452 for (int i = 0; i < c->num_uniform_ranges; i++) {
2453 struct vc4_compiler_ubo_range *range =
2454 &c->ubo_ranges[i];
2455 if (!range->used)
2456 continue;
2457
2458 shader->ubo_ranges[j].dst_offset = range->dst_offset;
2459 shader->ubo_ranges[j].src_offset = range->src_offset;
2460 shader->ubo_ranges[j].size = range->size;
2461 shader->ubo_size += c->ubo_ranges[i].size;
2462 j++;
2463 }
2464 }
2465 if (shader->ubo_size) {
2466 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2467 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d UBO uniforms\n",
2468 qir_get_stage_name(c->stage),
2469 c->program_id, c->variant_id,
2470 shader->ubo_size / 4);
2471 }
2472 }
2473
2474 qir_compile_destroy(c);
2475
2476 struct vc4_key *dup_key;
2477 dup_key = ralloc_size(shader, key_size);
2478 memcpy(dup_key, key, key_size);
2479 _mesa_hash_table_insert(ht, dup_key, shader);
2480
2481 return shader;
2482 }
2483
2484 static void
2485 vc4_setup_shared_key(struct vc4_context *vc4, struct vc4_key *key,
2486 struct vc4_texture_stateobj *texstate)
2487 {
2488 for (int i = 0; i < texstate->num_textures; i++) {
2489 struct pipe_sampler_view *sampler = texstate->textures[i];
2490 struct vc4_sampler_view *vc4_sampler = vc4_sampler_view(sampler);
2491 struct pipe_sampler_state *sampler_state =
2492 texstate->samplers[i];
2493
2494 if (!sampler)
2495 continue;
2496
2497 key->tex[i].format = sampler->format;
2498 key->tex[i].swizzle[0] = sampler->swizzle_r;
2499 key->tex[i].swizzle[1] = sampler->swizzle_g;
2500 key->tex[i].swizzle[2] = sampler->swizzle_b;
2501 key->tex[i].swizzle[3] = sampler->swizzle_a;
2502
2503 if (sampler->texture->nr_samples > 1) {
2504 key->tex[i].msaa_width = sampler->texture->width0;
2505 key->tex[i].msaa_height = sampler->texture->height0;
2506 } else if (sampler){
2507 key->tex[i].compare_mode = sampler_state->compare_mode;
2508 key->tex[i].compare_func = sampler_state->compare_func;
2509 key->tex[i].wrap_s = sampler_state->wrap_s;
2510 key->tex[i].wrap_t = sampler_state->wrap_t;
2511 key->tex[i].force_first_level =
2512 vc4_sampler->force_first_level;
2513 }
2514 }
2515
2516 key->ucp_enables = vc4->rasterizer->base.clip_plane_enable;
2517 }
2518
2519 static void
2520 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
2521 {
2522 struct vc4_job *job = vc4->job;
2523 struct vc4_fs_key local_key;
2524 struct vc4_fs_key *key = &local_key;
2525
2526 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2527 VC4_DIRTY_BLEND |
2528 VC4_DIRTY_FRAMEBUFFER |
2529 VC4_DIRTY_ZSA |
2530 VC4_DIRTY_RASTERIZER |
2531 VC4_DIRTY_SAMPLE_MASK |
2532 VC4_DIRTY_FRAGTEX |
2533 VC4_DIRTY_UNCOMPILED_FS))) {
2534 return;
2535 }
2536
2537 memset(key, 0, sizeof(*key));
2538 vc4_setup_shared_key(vc4, &key->base, &vc4->fragtex);
2539 key->base.shader_state = vc4->prog.bind_fs;
2540 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
2541 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
2542 prim_mode <= PIPE_PRIM_LINE_STRIP);
2543 key->blend = vc4->blend->rt[0];
2544 if (vc4->blend->logicop_enable) {
2545 key->logicop_func = vc4->blend->logicop_func;
2546 } else {
2547 key->logicop_func = PIPE_LOGICOP_COPY;
2548 }
2549 if (job->msaa) {
2550 key->msaa = vc4->rasterizer->base.multisample;
2551 key->sample_coverage = (vc4->rasterizer->base.multisample &&
2552 vc4->sample_mask != (1 << VC4_MAX_SAMPLES) - 1);
2553 key->sample_alpha_to_coverage = vc4->blend->alpha_to_coverage;
2554 key->sample_alpha_to_one = vc4->blend->alpha_to_one;
2555 }
2556
2557 if (vc4->framebuffer.cbufs[0])
2558 key->color_format = vc4->framebuffer.cbufs[0]->format;
2559
2560 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
2561 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
2562 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
2563 key->depth_enabled = (vc4->zsa->base.depth.enabled ||
2564 key->stencil_enabled);
2565 if (vc4->zsa->base.alpha.enabled) {
2566 key->alpha_test = true;
2567 key->alpha_test_func = vc4->zsa->base.alpha.func;
2568 }
2569
2570 if (key->is_points) {
2571 key->point_sprite_mask =
2572 vc4->rasterizer->base.sprite_coord_enable;
2573 key->point_coord_upper_left =
2574 (vc4->rasterizer->base.sprite_coord_mode ==
2575 PIPE_SPRITE_COORD_UPPER_LEFT);
2576 }
2577
2578 key->light_twoside = vc4->rasterizer->base.light_twoside;
2579
2580 struct vc4_compiled_shader *old_fs = vc4->prog.fs;
2581 vc4->prog.fs = vc4_get_compiled_shader(vc4, QSTAGE_FRAG, &key->base);
2582 if (vc4->prog.fs == old_fs)
2583 return;
2584
2585 vc4->dirty |= VC4_DIRTY_COMPILED_FS;
2586
2587 if (vc4->rasterizer->base.flatshade &&
2588 old_fs && vc4->prog.fs->color_inputs != old_fs->color_inputs) {
2589 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
2590 }
2591
2592 if (old_fs && vc4->prog.fs->fs_inputs != old_fs->fs_inputs)
2593 vc4->dirty |= VC4_DIRTY_FS_INPUTS;
2594 }
2595
2596 static void
2597 vc4_update_compiled_vs(struct vc4_context *vc4, uint8_t prim_mode)
2598 {
2599 struct vc4_vs_key local_key;
2600 struct vc4_vs_key *key = &local_key;
2601
2602 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2603 VC4_DIRTY_RASTERIZER |
2604 VC4_DIRTY_VERTTEX |
2605 VC4_DIRTY_VTXSTATE |
2606 VC4_DIRTY_UNCOMPILED_VS |
2607 VC4_DIRTY_FS_INPUTS))) {
2608 return;
2609 }
2610
2611 memset(key, 0, sizeof(*key));
2612 vc4_setup_shared_key(vc4, &key->base, &vc4->verttex);
2613 key->base.shader_state = vc4->prog.bind_vs;
2614 key->fs_inputs = vc4->prog.fs->fs_inputs;
2615 key->clamp_color = vc4->rasterizer->base.clamp_vertex_color;
2616
2617 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
2618 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
2619
2620 key->per_vertex_point_size =
2621 (prim_mode == PIPE_PRIM_POINTS &&
2622 vc4->rasterizer->base.point_size_per_vertex);
2623
2624 struct vc4_compiled_shader *vs =
2625 vc4_get_compiled_shader(vc4, QSTAGE_VERT, &key->base);
2626 if (vs != vc4->prog.vs) {
2627 vc4->prog.vs = vs;
2628 vc4->dirty |= VC4_DIRTY_COMPILED_VS;
2629 }
2630
2631 key->is_coord = true;
2632 /* Coord shaders don't care what the FS inputs are. */
2633 key->fs_inputs = NULL;
2634 struct vc4_compiled_shader *cs =
2635 vc4_get_compiled_shader(vc4, QSTAGE_COORD, &key->base);
2636 if (cs != vc4->prog.cs) {
2637 vc4->prog.cs = cs;
2638 vc4->dirty |= VC4_DIRTY_COMPILED_CS;
2639 }
2640 }
2641
2642 void
2643 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
2644 {
2645 vc4_update_compiled_fs(vc4, prim_mode);
2646 vc4_update_compiled_vs(vc4, prim_mode);
2647 }
2648
2649 static uint32_t
2650 fs_cache_hash(const void *key)
2651 {
2652 return _mesa_hash_data(key, sizeof(struct vc4_fs_key));
2653 }
2654
2655 static uint32_t
2656 vs_cache_hash(const void *key)
2657 {
2658 return _mesa_hash_data(key, sizeof(struct vc4_vs_key));
2659 }
2660
2661 static bool
2662 fs_cache_compare(const void *key1, const void *key2)
2663 {
2664 return memcmp(key1, key2, sizeof(struct vc4_fs_key)) == 0;
2665 }
2666
2667 static bool
2668 vs_cache_compare(const void *key1, const void *key2)
2669 {
2670 return memcmp(key1, key2, sizeof(struct vc4_vs_key)) == 0;
2671 }
2672
2673 static uint32_t
2674 fs_inputs_hash(const void *key)
2675 {
2676 const struct vc4_fs_inputs *inputs = key;
2677
2678 return _mesa_hash_data(inputs->input_slots,
2679 sizeof(*inputs->input_slots) *
2680 inputs->num_inputs);
2681 }
2682
2683 static bool
2684 fs_inputs_compare(const void *key1, const void *key2)
2685 {
2686 const struct vc4_fs_inputs *inputs1 = key1;
2687 const struct vc4_fs_inputs *inputs2 = key2;
2688
2689 return (inputs1->num_inputs == inputs2->num_inputs &&
2690 memcmp(inputs1->input_slots,
2691 inputs2->input_slots,
2692 sizeof(*inputs1->input_slots) *
2693 inputs1->num_inputs) == 0);
2694 }
2695
2696 static void
2697 delete_from_cache_if_matches(struct hash_table *ht,
2698 struct hash_entry *entry,
2699 struct vc4_uncompiled_shader *so)
2700 {
2701 const struct vc4_key *key = entry->key;
2702
2703 if (key->shader_state == so) {
2704 struct vc4_compiled_shader *shader = entry->data;
2705 _mesa_hash_table_remove(ht, entry);
2706 vc4_bo_unreference(&shader->bo);
2707 ralloc_free(shader);
2708 }
2709 }
2710
2711 static void
2712 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
2713 {
2714 struct vc4_context *vc4 = vc4_context(pctx);
2715 struct vc4_uncompiled_shader *so = hwcso;
2716
2717 struct hash_entry *entry;
2718 hash_table_foreach(vc4->fs_cache, entry)
2719 delete_from_cache_if_matches(vc4->fs_cache, entry, so);
2720 hash_table_foreach(vc4->vs_cache, entry)
2721 delete_from_cache_if_matches(vc4->vs_cache, entry, so);
2722
2723 ralloc_free(so->base.ir.nir);
2724 free(so);
2725 }
2726
2727 static void
2728 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
2729 {
2730 struct vc4_context *vc4 = vc4_context(pctx);
2731 vc4->prog.bind_fs = hwcso;
2732 vc4->dirty |= VC4_DIRTY_UNCOMPILED_FS;
2733 }
2734
2735 static void
2736 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
2737 {
2738 struct vc4_context *vc4 = vc4_context(pctx);
2739 vc4->prog.bind_vs = hwcso;
2740 vc4->dirty |= VC4_DIRTY_UNCOMPILED_VS;
2741 }
2742
2743 void
2744 vc4_program_init(struct pipe_context *pctx)
2745 {
2746 struct vc4_context *vc4 = vc4_context(pctx);
2747
2748 pctx->create_vs_state = vc4_shader_state_create;
2749 pctx->delete_vs_state = vc4_shader_state_delete;
2750
2751 pctx->create_fs_state = vc4_shader_state_create;
2752 pctx->delete_fs_state = vc4_shader_state_delete;
2753
2754 pctx->bind_fs_state = vc4_fp_state_bind;
2755 pctx->bind_vs_state = vc4_vp_state_bind;
2756
2757 vc4->fs_cache = _mesa_hash_table_create(pctx, fs_cache_hash,
2758 fs_cache_compare);
2759 vc4->vs_cache = _mesa_hash_table_create(pctx, vs_cache_hash,
2760 vs_cache_compare);
2761 vc4->fs_inputs_set = _mesa_set_create(pctx, fs_inputs_hash,
2762 fs_inputs_compare);
2763 }
2764
2765 void
2766 vc4_program_fini(struct pipe_context *pctx)
2767 {
2768 struct vc4_context *vc4 = vc4_context(pctx);
2769
2770 struct hash_entry *entry;
2771 hash_table_foreach(vc4->fs_cache, entry) {
2772 struct vc4_compiled_shader *shader = entry->data;
2773 vc4_bo_unreference(&shader->bo);
2774 ralloc_free(shader);
2775 _mesa_hash_table_remove(vc4->fs_cache, entry);
2776 }
2777
2778 hash_table_foreach(vc4->vs_cache, entry) {
2779 struct vc4_compiled_shader *shader = entry->data;
2780 vc4_bo_unreference(&shader->bo);
2781 ralloc_free(shader);
2782 _mesa_hash_table_remove(vc4->vs_cache, entry);
2783 }
2784 }