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[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "util/u_format.h"
27 #include "util/u_hash.h"
28 #include "util/u_math.h"
29 #include "util/u_memory.h"
30 #include "util/ralloc.h"
31 #include "util/hash_table.h"
32 #include "tgsi/tgsi_dump.h"
33 #include "tgsi/tgsi_lowering.h"
34 #include "tgsi/tgsi_parse.h"
35 #include "glsl/nir/nir.h"
36 #include "glsl/nir/nir_builder.h"
37 #include "nir/tgsi_to_nir.h"
38 #include "vc4_context.h"
39 #include "vc4_qpu.h"
40 #include "vc4_qir.h"
41 #ifdef USE_VC4_SIMULATOR
42 #include "simpenrose/simpenrose.h"
43 #endif
44
45 static struct qreg
46 ntq_get_src(struct vc4_compile *c, nir_src src, int i);
47
48 static void
49 resize_qreg_array(struct vc4_compile *c,
50 struct qreg **regs,
51 uint32_t *size,
52 uint32_t decl_size)
53 {
54 if (*size >= decl_size)
55 return;
56
57 uint32_t old_size = *size;
58 *size = MAX2(*size * 2, decl_size);
59 *regs = reralloc(c, *regs, struct qreg, *size);
60 if (!*regs) {
61 fprintf(stderr, "Malloc failure\n");
62 abort();
63 }
64
65 for (uint32_t i = old_size; i < *size; i++)
66 (*regs)[i] = c->undef;
67 }
68
69 static struct qreg
70 indirect_uniform_load(struct vc4_compile *c, nir_intrinsic_instr *intr)
71 {
72 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0);
73 uint32_t offset = intr->const_index[0];
74 struct vc4_compiler_ubo_range *range = NULL;
75 unsigned i;
76 for (i = 0; i < c->num_uniform_ranges; i++) {
77 range = &c->ubo_ranges[i];
78 if (offset >= range->src_offset &&
79 offset < range->src_offset + range->size) {
80 break;
81 }
82 }
83 /* The driver-location-based offset always has to be within a declared
84 * uniform range.
85 */
86 assert(range);
87 if (!range->used) {
88 range->used = true;
89 range->dst_offset = c->next_ubo_dst_offset;
90 c->next_ubo_dst_offset += range->size;
91 c->num_ubo_ranges++;
92 };
93
94 offset -= range->src_offset;
95
96 /* Adjust for where we stored the TGSI register base. */
97 indirect_offset = qir_ADD(c, indirect_offset,
98 qir_uniform_ui(c, (range->dst_offset +
99 offset)));
100
101 /* Clamp to [0, array size). Note that MIN/MAX are signed. */
102 indirect_offset = qir_MAX(c, indirect_offset, qir_uniform_ui(c, 0));
103 indirect_offset = qir_MIN(c, indirect_offset,
104 qir_uniform_ui(c, (range->dst_offset +
105 range->size - 4)));
106
107 qir_TEX_DIRECT(c, indirect_offset, qir_uniform(c, QUNIFORM_UBO_ADDR, 0));
108 c->num_texture_samples++;
109 return qir_TEX_RESULT(c);
110 }
111
112 nir_ssa_def *vc4_nir_get_state_uniform(struct nir_builder *b,
113 enum quniform_contents contents)
114 {
115 nir_intrinsic_instr *intr =
116 nir_intrinsic_instr_create(b->shader,
117 nir_intrinsic_load_uniform);
118 intr->const_index[0] = (VC4_NIR_STATE_UNIFORM_OFFSET + contents) * 4;
119 intr->num_components = 1;
120 intr->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
121 nir_ssa_dest_init(&intr->instr, &intr->dest, 1, NULL);
122 nir_builder_instr_insert(b, &intr->instr);
123 return &intr->dest.ssa;
124 }
125
126 nir_ssa_def *
127 vc4_nir_get_swizzled_channel(nir_builder *b, nir_ssa_def **srcs, int swiz)
128 {
129 switch (swiz) {
130 default:
131 case UTIL_FORMAT_SWIZZLE_NONE:
132 fprintf(stderr, "warning: unknown swizzle\n");
133 /* FALLTHROUGH */
134 case UTIL_FORMAT_SWIZZLE_0:
135 return nir_imm_float(b, 0.0);
136 case UTIL_FORMAT_SWIZZLE_1:
137 return nir_imm_float(b, 1.0);
138 case UTIL_FORMAT_SWIZZLE_X:
139 case UTIL_FORMAT_SWIZZLE_Y:
140 case UTIL_FORMAT_SWIZZLE_Z:
141 case UTIL_FORMAT_SWIZZLE_W:
142 return srcs[swiz];
143 }
144 }
145
146 static struct qreg *
147 ntq_init_ssa_def(struct vc4_compile *c, nir_ssa_def *def)
148 {
149 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
150 def->num_components);
151 _mesa_hash_table_insert(c->def_ht, def, qregs);
152 return qregs;
153 }
154
155 static struct qreg *
156 ntq_get_dest(struct vc4_compile *c, nir_dest *dest)
157 {
158 if (dest->is_ssa) {
159 struct qreg *qregs = ntq_init_ssa_def(c, &dest->ssa);
160 for (int i = 0; i < dest->ssa.num_components; i++)
161 qregs[i] = c->undef;
162 return qregs;
163 } else {
164 nir_register *reg = dest->reg.reg;
165 assert(dest->reg.base_offset == 0);
166 assert(reg->num_array_elems == 0);
167 struct hash_entry *entry =
168 _mesa_hash_table_search(c->def_ht, reg);
169 return entry->data;
170 }
171 }
172
173 static struct qreg
174 ntq_get_src(struct vc4_compile *c, nir_src src, int i)
175 {
176 struct hash_entry *entry;
177 if (src.is_ssa) {
178 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
179 assert(i < src.ssa->num_components);
180 } else {
181 nir_register *reg = src.reg.reg;
182 entry = _mesa_hash_table_search(c->def_ht, reg);
183 assert(reg->num_array_elems == 0);
184 assert(src.reg.base_offset == 0);
185 assert(i < reg->num_components);
186 }
187
188 struct qreg *qregs = entry->data;
189 return qregs[i];
190 }
191
192 static struct qreg
193 ntq_get_alu_src(struct vc4_compile *c, nir_alu_instr *instr,
194 unsigned src)
195 {
196 assert(util_is_power_of_two(instr->dest.write_mask));
197 unsigned chan = ffs(instr->dest.write_mask) - 1;
198 struct qreg r = ntq_get_src(c, instr->src[src].src,
199 instr->src[src].swizzle[chan]);
200
201 assert(!instr->src[src].abs);
202 assert(!instr->src[src].negate);
203
204 return r;
205 };
206
207 static struct qreg
208 get_swizzled_channel(struct vc4_compile *c,
209 struct qreg *srcs, int swiz)
210 {
211 switch (swiz) {
212 default:
213 case UTIL_FORMAT_SWIZZLE_NONE:
214 fprintf(stderr, "warning: unknown swizzle\n");
215 /* FALLTHROUGH */
216 case UTIL_FORMAT_SWIZZLE_0:
217 return qir_uniform_f(c, 0.0);
218 case UTIL_FORMAT_SWIZZLE_1:
219 return qir_uniform_f(c, 1.0);
220 case UTIL_FORMAT_SWIZZLE_X:
221 case UTIL_FORMAT_SWIZZLE_Y:
222 case UTIL_FORMAT_SWIZZLE_Z:
223 case UTIL_FORMAT_SWIZZLE_W:
224 return srcs[swiz];
225 }
226 }
227
228 static inline struct qreg
229 qir_SAT(struct vc4_compile *c, struct qreg val)
230 {
231 return qir_FMAX(c,
232 qir_FMIN(c, val, qir_uniform_f(c, 1.0)),
233 qir_uniform_f(c, 0.0));
234 }
235
236 static struct qreg
237 ntq_rcp(struct vc4_compile *c, struct qreg x)
238 {
239 struct qreg r = qir_RCP(c, x);
240
241 /* Apply a Newton-Raphson step to improve the accuracy. */
242 r = qir_FMUL(c, r, qir_FSUB(c,
243 qir_uniform_f(c, 2.0),
244 qir_FMUL(c, x, r)));
245
246 return r;
247 }
248
249 static struct qreg
250 ntq_rsq(struct vc4_compile *c, struct qreg x)
251 {
252 struct qreg r = qir_RSQ(c, x);
253
254 /* Apply a Newton-Raphson step to improve the accuracy. */
255 r = qir_FMUL(c, r, qir_FSUB(c,
256 qir_uniform_f(c, 1.5),
257 qir_FMUL(c,
258 qir_uniform_f(c, 0.5),
259 qir_FMUL(c, x,
260 qir_FMUL(c, r, r)))));
261
262 return r;
263 }
264
265 static struct qreg
266 qir_srgb_decode(struct vc4_compile *c, struct qreg srgb)
267 {
268 struct qreg low = qir_FMUL(c, srgb, qir_uniform_f(c, 1.0 / 12.92));
269 struct qreg high = qir_POW(c,
270 qir_FMUL(c,
271 qir_FADD(c,
272 srgb,
273 qir_uniform_f(c, 0.055)),
274 qir_uniform_f(c, 1.0 / 1.055)),
275 qir_uniform_f(c, 2.4));
276
277 qir_SF(c, qir_FSUB(c, srgb, qir_uniform_f(c, 0.04045)));
278 return qir_SEL_X_Y_NS(c, low, high);
279 }
280
281 static struct qreg
282 ntq_umul(struct vc4_compile *c, struct qreg src0, struct qreg src1)
283 {
284 struct qreg src0_hi = qir_SHR(c, src0,
285 qir_uniform_ui(c, 24));
286 struct qreg src1_hi = qir_SHR(c, src1,
287 qir_uniform_ui(c, 24));
288
289 struct qreg hilo = qir_MUL24(c, src0_hi, src1);
290 struct qreg lohi = qir_MUL24(c, src0, src1_hi);
291 struct qreg lolo = qir_MUL24(c, src0, src1);
292
293 return qir_ADD(c, lolo, qir_SHL(c,
294 qir_ADD(c, hilo, lohi),
295 qir_uniform_ui(c, 24)));
296 }
297
298 static struct qreg
299 ntq_scale_depth_texture(struct vc4_compile *c, struct qreg src)
300 {
301 struct qreg depthf = qir_ITOF(c, qir_SHR(c, src,
302 qir_uniform_ui(c, 8)));
303 return qir_FMUL(c, depthf, qir_uniform_f(c, 1.0f/0xffffff));
304 }
305
306 /**
307 * Emits a lowered TXF_MS from an MSAA texture.
308 *
309 * The addressing math has been lowered in NIR, and now we just need to read
310 * it like a UBO.
311 */
312 static void
313 ntq_emit_txf(struct vc4_compile *c, nir_tex_instr *instr)
314 {
315 uint32_t tile_width = 32;
316 uint32_t tile_height = 32;
317 uint32_t tile_size = (tile_height * tile_width *
318 VC4_MAX_SAMPLES * sizeof(uint32_t));
319
320 unsigned unit = instr->sampler_index;
321 uint32_t w = align(c->key->tex[unit].msaa_width, tile_width);
322 uint32_t w_tiles = w / tile_width;
323 uint32_t h = align(c->key->tex[unit].msaa_height, tile_height);
324 uint32_t h_tiles = h / tile_height;
325 uint32_t size = w_tiles * h_tiles * tile_size;
326
327 struct qreg addr;
328 assert(instr->num_srcs == 1);
329 assert(instr->src[0].src_type == nir_tex_src_coord);
330 addr = ntq_get_src(c, instr->src[0].src, 0);
331
332 /* Perform the clamping required by kernel validation. */
333 addr = qir_MAX(c, addr, qir_uniform_ui(c, 0));
334 addr = qir_MIN(c, addr, qir_uniform_ui(c, size - 4));
335
336 qir_TEX_DIRECT(c, addr, qir_uniform(c, QUNIFORM_TEXTURE_MSAA_ADDR, unit));
337
338 struct qreg tex = qir_TEX_RESULT(c);
339 c->num_texture_samples++;
340
341 struct qreg texture_output[4];
342 enum pipe_format format = c->key->tex[unit].format;
343 if (util_format_is_depth_or_stencil(format)) {
344 struct qreg scaled = ntq_scale_depth_texture(c, tex);
345 for (int i = 0; i < 4; i++)
346 texture_output[i] = scaled;
347 } else {
348 struct qreg tex_result_unpacked[4];
349 for (int i = 0; i < 4; i++)
350 tex_result_unpacked[i] = qir_UNPACK_8_F(c, tex, i);
351
352 const uint8_t *format_swiz =
353 vc4_get_format_swizzle(c->key->tex[unit].format);
354 for (int i = 0; i < 4; i++) {
355 texture_output[i] =
356 get_swizzled_channel(c, tex_result_unpacked,
357 format_swiz[i]);
358 }
359 }
360
361 struct qreg *dest = ntq_get_dest(c, &instr->dest);
362 for (int i = 0; i < 4; i++) {
363 dest[i] = get_swizzled_channel(c, texture_output,
364 c->key->tex[unit].swizzle[i]);
365 }
366 }
367
368 static void
369 ntq_emit_tex(struct vc4_compile *c, nir_tex_instr *instr)
370 {
371 struct qreg s, t, r, lod, proj, compare;
372 bool is_txb = false, is_txl = false, has_proj = false;
373 unsigned unit = instr->sampler_index;
374
375 if (instr->op == nir_texop_txf) {
376 ntq_emit_txf(c, instr);
377 return;
378 }
379
380 for (unsigned i = 0; i < instr->num_srcs; i++) {
381 switch (instr->src[i].src_type) {
382 case nir_tex_src_coord:
383 s = ntq_get_src(c, instr->src[i].src, 0);
384 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D)
385 t = qir_uniform_f(c, 0.5);
386 else
387 t = ntq_get_src(c, instr->src[i].src, 1);
388 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
389 r = ntq_get_src(c, instr->src[i].src, 2);
390 break;
391 case nir_tex_src_bias:
392 lod = ntq_get_src(c, instr->src[i].src, 0);
393 is_txb = true;
394 break;
395 case nir_tex_src_lod:
396 lod = ntq_get_src(c, instr->src[i].src, 0);
397 is_txl = true;
398 break;
399 case nir_tex_src_comparitor:
400 compare = ntq_get_src(c, instr->src[i].src, 0);
401 break;
402 case nir_tex_src_projector:
403 proj = qir_RCP(c, ntq_get_src(c, instr->src[i].src, 0));
404 s = qir_FMUL(c, s, proj);
405 t = qir_FMUL(c, t, proj);
406 has_proj = true;
407 break;
408 default:
409 unreachable("unknown texture source");
410 }
411 }
412
413 struct qreg texture_u[] = {
414 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit),
415 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
416 qir_uniform(c, QUNIFORM_CONSTANT, 0),
417 qir_uniform(c, QUNIFORM_CONSTANT, 0),
418 };
419 uint32_t next_texture_u = 0;
420
421 /* There is no native support for GL texture rectangle coordinates, so
422 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
423 * 1]).
424 */
425 if (instr->sampler_dim == GLSL_SAMPLER_DIM_RECT) {
426 s = qir_FMUL(c, s,
427 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_X, unit));
428 t = qir_FMUL(c, t,
429 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_Y, unit));
430 }
431
432 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE || is_txl) {
433 texture_u[2] = qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P2,
434 unit | (is_txl << 16));
435 }
436
437 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
438 struct qreg ma = qir_FMAXABS(c, qir_FMAXABS(c, s, t), r);
439 struct qreg rcp_ma = qir_RCP(c, ma);
440 s = qir_FMUL(c, s, rcp_ma);
441 t = qir_FMUL(c, t, rcp_ma);
442 r = qir_FMUL(c, r, rcp_ma);
443
444 qir_TEX_R(c, r, texture_u[next_texture_u++]);
445 } else if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
446 c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP ||
447 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
448 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
449 qir_TEX_R(c, qir_uniform(c, QUNIFORM_TEXTURE_BORDER_COLOR, unit),
450 texture_u[next_texture_u++]);
451 }
452
453 if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP) {
454 s = qir_SAT(c, s);
455 }
456
457 if (c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
458 t = qir_SAT(c, t);
459 }
460
461 qir_TEX_T(c, t, texture_u[next_texture_u++]);
462
463 if (is_txl || is_txb)
464 qir_TEX_B(c, lod, texture_u[next_texture_u++]);
465
466 qir_TEX_S(c, s, texture_u[next_texture_u++]);
467
468 c->num_texture_samples++;
469 struct qreg tex = qir_TEX_RESULT(c);
470
471 enum pipe_format format = c->key->tex[unit].format;
472
473 struct qreg unpacked[4];
474 if (util_format_is_depth_or_stencil(format)) {
475 struct qreg normalized = ntq_scale_depth_texture(c, tex);
476 struct qreg depth_output;
477
478 struct qreg one = qir_uniform_f(c, 1.0f);
479 if (c->key->tex[unit].compare_mode) {
480 if (has_proj)
481 compare = qir_FMUL(c, compare, proj);
482
483 switch (c->key->tex[unit].compare_func) {
484 case PIPE_FUNC_NEVER:
485 depth_output = qir_uniform_f(c, 0.0f);
486 break;
487 case PIPE_FUNC_ALWAYS:
488 depth_output = one;
489 break;
490 case PIPE_FUNC_EQUAL:
491 qir_SF(c, qir_FSUB(c, compare, normalized));
492 depth_output = qir_SEL_X_0_ZS(c, one);
493 break;
494 case PIPE_FUNC_NOTEQUAL:
495 qir_SF(c, qir_FSUB(c, compare, normalized));
496 depth_output = qir_SEL_X_0_ZC(c, one);
497 break;
498 case PIPE_FUNC_GREATER:
499 qir_SF(c, qir_FSUB(c, compare, normalized));
500 depth_output = qir_SEL_X_0_NC(c, one);
501 break;
502 case PIPE_FUNC_GEQUAL:
503 qir_SF(c, qir_FSUB(c, normalized, compare));
504 depth_output = qir_SEL_X_0_NS(c, one);
505 break;
506 case PIPE_FUNC_LESS:
507 qir_SF(c, qir_FSUB(c, compare, normalized));
508 depth_output = qir_SEL_X_0_NS(c, one);
509 break;
510 case PIPE_FUNC_LEQUAL:
511 qir_SF(c, qir_FSUB(c, normalized, compare));
512 depth_output = qir_SEL_X_0_NC(c, one);
513 break;
514 }
515 } else {
516 depth_output = normalized;
517 }
518
519 for (int i = 0; i < 4; i++)
520 unpacked[i] = depth_output;
521 } else {
522 for (int i = 0; i < 4; i++)
523 unpacked[i] = qir_UNPACK_8_F(c, tex, i);
524 }
525
526 const uint8_t *format_swiz = vc4_get_format_swizzle(format);
527 struct qreg texture_output[4];
528 for (int i = 0; i < 4; i++) {
529 texture_output[i] = get_swizzled_channel(c, unpacked,
530 format_swiz[i]);
531 }
532
533 if (util_format_is_srgb(format)) {
534 for (int i = 0; i < 3; i++)
535 texture_output[i] = qir_srgb_decode(c,
536 texture_output[i]);
537 }
538
539 struct qreg *dest = ntq_get_dest(c, &instr->dest);
540 for (int i = 0; i < 4; i++) {
541 dest[i] = get_swizzled_channel(c, texture_output,
542 c->key->tex[unit].swizzle[i]);
543 }
544 }
545
546 /**
547 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
548 * to zero).
549 */
550 static struct qreg
551 ntq_ffract(struct vc4_compile *c, struct qreg src)
552 {
553 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
554 struct qreg diff = qir_FSUB(c, src, trunc);
555 qir_SF(c, diff);
556 return qir_SEL_X_Y_NS(c,
557 qir_FADD(c, diff, qir_uniform_f(c, 1.0)),
558 diff);
559 }
560
561 /**
562 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
563 * zero).
564 */
565 static struct qreg
566 ntq_ffloor(struct vc4_compile *c, struct qreg src)
567 {
568 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
569
570 /* This will be < 0 if we truncated and the truncation was of a value
571 * that was < 0 in the first place.
572 */
573 qir_SF(c, qir_FSUB(c, src, trunc));
574
575 return qir_SEL_X_Y_NS(c,
576 qir_FSUB(c, trunc, qir_uniform_f(c, 1.0)),
577 trunc);
578 }
579
580 /**
581 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
582 * zero).
583 */
584 static struct qreg
585 ntq_fceil(struct vc4_compile *c, struct qreg src)
586 {
587 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
588
589 /* This will be < 0 if we truncated and the truncation was of a value
590 * that was > 0 in the first place.
591 */
592 qir_SF(c, qir_FSUB(c, trunc, src));
593
594 return qir_SEL_X_Y_NS(c,
595 qir_FADD(c, trunc, qir_uniform_f(c, 1.0)),
596 trunc);
597 }
598
599 static struct qreg
600 ntq_fsin(struct vc4_compile *c, struct qreg src)
601 {
602 float coeff[] = {
603 -2.0 * M_PI,
604 pow(2.0 * M_PI, 3) / (3 * 2 * 1),
605 -pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
606 pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
607 -pow(2.0 * M_PI, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
608 };
609
610 struct qreg scaled_x =
611 qir_FMUL(c,
612 src,
613 qir_uniform_f(c, 1.0 / (M_PI * 2.0)));
614
615 struct qreg x = qir_FADD(c,
616 ntq_ffract(c, scaled_x),
617 qir_uniform_f(c, -0.5));
618 struct qreg x2 = qir_FMUL(c, x, x);
619 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
620 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
621 x = qir_FMUL(c, x, x2);
622 sum = qir_FADD(c,
623 sum,
624 qir_FMUL(c,
625 x,
626 qir_uniform_f(c, coeff[i])));
627 }
628 return sum;
629 }
630
631 static struct qreg
632 ntq_fcos(struct vc4_compile *c, struct qreg src)
633 {
634 float coeff[] = {
635 -1.0f,
636 pow(2.0 * M_PI, 2) / (2 * 1),
637 -pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
638 pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
639 -pow(2.0 * M_PI, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
640 pow(2.0 * M_PI, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
641 };
642
643 struct qreg scaled_x =
644 qir_FMUL(c, src,
645 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
646 struct qreg x_frac = qir_FADD(c,
647 ntq_ffract(c, scaled_x),
648 qir_uniform_f(c, -0.5));
649
650 struct qreg sum = qir_uniform_f(c, coeff[0]);
651 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
652 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
653 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
654 if (i != 1)
655 x = qir_FMUL(c, x, x2);
656
657 struct qreg mul = qir_FMUL(c,
658 x,
659 qir_uniform_f(c, coeff[i]));
660 if (i == 0)
661 sum = mul;
662 else
663 sum = qir_FADD(c, sum, mul);
664 }
665 return sum;
666 }
667
668 static struct qreg
669 ntq_fsign(struct vc4_compile *c, struct qreg src)
670 {
671 qir_SF(c, src);
672 return qir_SEL_X_Y_NC(c,
673 qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0)),
674 qir_uniform_f(c, -1.0));
675 }
676
677 static void
678 emit_vertex_input(struct vc4_compile *c, int attr)
679 {
680 enum pipe_format format = c->vs_key->attr_formats[attr];
681 uint32_t attr_size = util_format_get_blocksize(format);
682
683 c->vattr_sizes[attr] = align(attr_size, 4);
684 for (int i = 0; i < align(attr_size, 4) / 4; i++) {
685 struct qreg vpm = { QFILE_VPM, attr * 4 + i };
686 c->inputs[attr * 4 + i] = qir_MOV(c, vpm);
687 c->num_inputs++;
688 }
689 }
690
691 static void
692 emit_fragcoord_input(struct vc4_compile *c, int attr)
693 {
694 c->inputs[attr * 4 + 0] = qir_FRAG_X(c);
695 c->inputs[attr * 4 + 1] = qir_FRAG_Y(c);
696 c->inputs[attr * 4 + 2] =
697 qir_FMUL(c,
698 qir_ITOF(c, qir_FRAG_Z(c)),
699 qir_uniform_f(c, 1.0 / 0xffffff));
700 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
701 }
702
703 static struct qreg
704 emit_fragment_varying(struct vc4_compile *c, gl_varying_slot slot,
705 uint8_t swizzle)
706 {
707 uint32_t i = c->num_input_slots++;
708 struct qreg vary = {
709 QFILE_VARY,
710 i
711 };
712
713 if (c->num_input_slots >= c->input_slots_array_size) {
714 c->input_slots_array_size =
715 MAX2(4, c->input_slots_array_size * 2);
716
717 c->input_slots = reralloc(c, c->input_slots,
718 struct vc4_varying_slot,
719 c->input_slots_array_size);
720 }
721
722 c->input_slots[i].slot = slot;
723 c->input_slots[i].swizzle = swizzle;
724
725 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
726 }
727
728 static void
729 emit_fragment_input(struct vc4_compile *c, int attr, gl_varying_slot slot)
730 {
731 for (int i = 0; i < 4; i++) {
732 c->inputs[attr * 4 + i] =
733 emit_fragment_varying(c, slot, i);
734 c->num_inputs++;
735 }
736 }
737
738 static void
739 add_output(struct vc4_compile *c,
740 uint32_t decl_offset,
741 uint8_t slot,
742 uint8_t swizzle)
743 {
744 uint32_t old_array_size = c->outputs_array_size;
745 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
746 decl_offset + 1);
747
748 if (old_array_size != c->outputs_array_size) {
749 c->output_slots = reralloc(c,
750 c->output_slots,
751 struct vc4_varying_slot,
752 c->outputs_array_size);
753 }
754
755 c->output_slots[decl_offset].slot = slot;
756 c->output_slots[decl_offset].swizzle = swizzle;
757 }
758
759 static void
760 declare_uniform_range(struct vc4_compile *c, uint32_t start, uint32_t size)
761 {
762 unsigned array_id = c->num_uniform_ranges++;
763 if (array_id >= c->ubo_ranges_array_size) {
764 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
765 array_id + 1);
766 c->ubo_ranges = reralloc(c, c->ubo_ranges,
767 struct vc4_compiler_ubo_range,
768 c->ubo_ranges_array_size);
769 }
770
771 c->ubo_ranges[array_id].dst_offset = 0;
772 c->ubo_ranges[array_id].src_offset = start;
773 c->ubo_ranges[array_id].size = size;
774 c->ubo_ranges[array_id].used = false;
775 }
776
777 static bool
778 ntq_src_is_only_ssa_def_user(nir_src *src)
779 {
780 if (!src->is_ssa)
781 return false;
782
783 if (!list_empty(&src->ssa->if_uses))
784 return false;
785
786 return (src->ssa->uses.next == &src->use_link &&
787 src->ssa->uses.next->next == &src->ssa->uses);
788 }
789
790 /**
791 * In general, emits a nir_pack_unorm_4x8 as a series of MOVs with the pack
792 * bit set.
793 *
794 * However, as an optimization, it tries to find the instructions generating
795 * the sources to be packed and just emit the pack flag there, if possible.
796 */
797 static void
798 ntq_emit_pack_unorm_4x8(struct vc4_compile *c, nir_alu_instr *instr)
799 {
800 struct qreg result = qir_get_temp(c);
801 struct nir_alu_instr *vec4 = NULL;
802
803 /* If packing from a vec4 op (as expected), identify it so that we can
804 * peek back at what generated its sources.
805 */
806 if (instr->src[0].src.is_ssa &&
807 instr->src[0].src.ssa->parent_instr->type == nir_instr_type_alu &&
808 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr)->op ==
809 nir_op_vec4) {
810 vec4 = nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
811 }
812
813 /* If the pack is replicating the same channel 4 times, use the 8888
814 * pack flag. This is common for blending using the alpha
815 * channel.
816 */
817 if (instr->src[0].swizzle[0] == instr->src[0].swizzle[1] &&
818 instr->src[0].swizzle[0] == instr->src[0].swizzle[2] &&
819 instr->src[0].swizzle[0] == instr->src[0].swizzle[3]) {
820 struct qreg *dest = ntq_get_dest(c, &instr->dest.dest);
821 *dest = qir_PACK_8888_F(c,
822 ntq_get_src(c, instr->src[0].src,
823 instr->src[0].swizzle[0]));
824 return;
825 }
826
827 for (int i = 0; i < 4; i++) {
828 int swiz = instr->src[0].swizzle[i];
829 struct qreg src;
830 if (vec4) {
831 src = ntq_get_src(c, vec4->src[swiz].src,
832 vec4->src[swiz].swizzle[0]);
833 } else {
834 src = ntq_get_src(c, instr->src[0].src, swiz);
835 }
836
837 if (vec4 &&
838 ntq_src_is_only_ssa_def_user(&vec4->src[swiz].src) &&
839 src.file == QFILE_TEMP &&
840 c->defs[src.index] &&
841 qir_is_mul(c->defs[src.index]) &&
842 !c->defs[src.index]->dst.pack) {
843 struct qinst *rewrite = c->defs[src.index];
844 c->defs[src.index] = NULL;
845 rewrite->dst = result;
846 rewrite->dst.pack = QPU_PACK_MUL_8A + i;
847 continue;
848 }
849
850 qir_PACK_8_F(c, result, src, i);
851 }
852
853 struct qreg *dest = ntq_get_dest(c, &instr->dest.dest);
854 *dest = result;
855 }
856
857 /** Handles sign-extended bitfield extracts for 16 bits. */
858 static struct qreg
859 ntq_emit_ibfe(struct vc4_compile *c, struct qreg base, struct qreg offset,
860 struct qreg bits)
861 {
862 assert(bits.file == QFILE_UNIF &&
863 c->uniform_contents[bits.index] == QUNIFORM_CONSTANT &&
864 c->uniform_data[bits.index] == 16);
865
866 assert(offset.file == QFILE_UNIF &&
867 c->uniform_contents[offset.index] == QUNIFORM_CONSTANT);
868 int offset_bit = c->uniform_data[offset.index];
869 assert(offset_bit % 16 == 0);
870
871 return qir_UNPACK_16_I(c, base, offset_bit / 16);
872 }
873
874 /** Handles unsigned bitfield extracts for 8 bits. */
875 static struct qreg
876 ntq_emit_ubfe(struct vc4_compile *c, struct qreg base, struct qreg offset,
877 struct qreg bits)
878 {
879 assert(bits.file == QFILE_UNIF &&
880 c->uniform_contents[bits.index] == QUNIFORM_CONSTANT &&
881 c->uniform_data[bits.index] == 8);
882
883 assert(offset.file == QFILE_UNIF &&
884 c->uniform_contents[offset.index] == QUNIFORM_CONSTANT);
885 int offset_bit = c->uniform_data[offset.index];
886 assert(offset_bit % 8 == 0);
887
888 return qir_UNPACK_8_I(c, base, offset_bit / 8);
889 }
890
891 static void
892 ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr)
893 {
894 /* Vectors are special in that they have non-scalarized writemasks,
895 * and just take the first swizzle channel for each argument in order
896 * into each writemask channel.
897 */
898 if (instr->op == nir_op_vec2 ||
899 instr->op == nir_op_vec3 ||
900 instr->op == nir_op_vec4) {
901 struct qreg srcs[4];
902 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
903 srcs[i] = ntq_get_src(c, instr->src[i].src,
904 instr->src[i].swizzle[0]);
905 struct qreg *dest = ntq_get_dest(c, &instr->dest.dest);
906 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
907 dest[i] = srcs[i];
908 return;
909 }
910
911 if (instr->op == nir_op_pack_unorm_4x8) {
912 ntq_emit_pack_unorm_4x8(c, instr);
913 return;
914 }
915
916 if (instr->op == nir_op_unpack_unorm_4x8) {
917 struct qreg src = ntq_get_src(c, instr->src[0].src,
918 instr->src[0].swizzle[0]);
919 struct qreg *dest = ntq_get_dest(c, &instr->dest.dest);
920 for (int i = 0; i < 4; i++) {
921 if (instr->dest.write_mask & (1 << i))
922 dest[i] = qir_UNPACK_8_F(c, src, i);
923 }
924 return;
925 }
926
927 /* General case: We can just grab the one used channel per src. */
928 struct qreg src[nir_op_infos[instr->op].num_inputs];
929 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
930 src[i] = ntq_get_alu_src(c, instr, i);
931 }
932
933 /* Pick the channel to store the output in. */
934 assert(!instr->dest.saturate);
935 struct qreg *dest = ntq_get_dest(c, &instr->dest.dest);
936 assert(util_is_power_of_two(instr->dest.write_mask));
937 dest += ffs(instr->dest.write_mask) - 1;
938
939 switch (instr->op) {
940 case nir_op_fmov:
941 case nir_op_imov:
942 *dest = qir_MOV(c, src[0]);
943 break;
944 case nir_op_fmul:
945 *dest = qir_FMUL(c, src[0], src[1]);
946 break;
947 case nir_op_fadd:
948 *dest = qir_FADD(c, src[0], src[1]);
949 break;
950 case nir_op_fsub:
951 *dest = qir_FSUB(c, src[0], src[1]);
952 break;
953 case nir_op_fmin:
954 *dest = qir_FMIN(c, src[0], src[1]);
955 break;
956 case nir_op_fmax:
957 *dest = qir_FMAX(c, src[0], src[1]);
958 break;
959
960 case nir_op_f2i:
961 case nir_op_f2u:
962 *dest = qir_FTOI(c, src[0]);
963 break;
964 case nir_op_i2f:
965 case nir_op_u2f:
966 *dest = qir_ITOF(c, src[0]);
967 break;
968 case nir_op_b2f:
969 *dest = qir_AND(c, src[0], qir_uniform_f(c, 1.0));
970 break;
971 case nir_op_b2i:
972 *dest = qir_AND(c, src[0], qir_uniform_ui(c, 1));
973 break;
974 case nir_op_i2b:
975 case nir_op_f2b:
976 qir_SF(c, src[0]);
977 *dest = qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
978 break;
979
980 case nir_op_iadd:
981 *dest = qir_ADD(c, src[0], src[1]);
982 break;
983 case nir_op_ushr:
984 *dest = qir_SHR(c, src[0], src[1]);
985 break;
986 case nir_op_isub:
987 *dest = qir_SUB(c, src[0], src[1]);
988 break;
989 case nir_op_ishr:
990 *dest = qir_ASR(c, src[0], src[1]);
991 break;
992 case nir_op_ishl:
993 *dest = qir_SHL(c, src[0], src[1]);
994 break;
995 case nir_op_imin:
996 *dest = qir_MIN(c, src[0], src[1]);
997 break;
998 case nir_op_imax:
999 *dest = qir_MAX(c, src[0], src[1]);
1000 break;
1001 case nir_op_iand:
1002 *dest = qir_AND(c, src[0], src[1]);
1003 break;
1004 case nir_op_ior:
1005 *dest = qir_OR(c, src[0], src[1]);
1006 break;
1007 case nir_op_ixor:
1008 *dest = qir_XOR(c, src[0], src[1]);
1009 break;
1010 case nir_op_inot:
1011 *dest = qir_NOT(c, src[0]);
1012 break;
1013
1014 case nir_op_imul:
1015 *dest = ntq_umul(c, src[0], src[1]);
1016 break;
1017
1018 case nir_op_seq:
1019 qir_SF(c, qir_FSUB(c, src[0], src[1]));
1020 *dest = qir_SEL_X_0_ZS(c, qir_uniform_f(c, 1.0));
1021 break;
1022 case nir_op_sne:
1023 qir_SF(c, qir_FSUB(c, src[0], src[1]));
1024 *dest = qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0));
1025 break;
1026 case nir_op_sge:
1027 qir_SF(c, qir_FSUB(c, src[0], src[1]));
1028 *dest = qir_SEL_X_0_NC(c, qir_uniform_f(c, 1.0));
1029 break;
1030 case nir_op_slt:
1031 qir_SF(c, qir_FSUB(c, src[0], src[1]));
1032 *dest = qir_SEL_X_0_NS(c, qir_uniform_f(c, 1.0));
1033 break;
1034 case nir_op_feq:
1035 qir_SF(c, qir_FSUB(c, src[0], src[1]));
1036 *dest = qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
1037 break;
1038 case nir_op_fne:
1039 qir_SF(c, qir_FSUB(c, src[0], src[1]));
1040 *dest = qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
1041 break;
1042 case nir_op_fge:
1043 qir_SF(c, qir_FSUB(c, src[0], src[1]));
1044 *dest = qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
1045 break;
1046 case nir_op_flt:
1047 qir_SF(c, qir_FSUB(c, src[0], src[1]));
1048 *dest = qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
1049 break;
1050 case nir_op_ieq:
1051 qir_SF(c, qir_SUB(c, src[0], src[1]));
1052 *dest = qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
1053 break;
1054 case nir_op_ine:
1055 qir_SF(c, qir_SUB(c, src[0], src[1]));
1056 *dest = qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
1057 break;
1058 case nir_op_ige:
1059 qir_SF(c, qir_SUB(c, src[0], src[1]));
1060 *dest = qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
1061 break;
1062 case nir_op_uge:
1063 qir_SF(c, qir_SUB(c, src[0], src[1]));
1064 *dest = qir_SEL_X_0_CC(c, qir_uniform_ui(c, ~0));
1065 break;
1066 case nir_op_ilt:
1067 qir_SF(c, qir_SUB(c, src[0], src[1]));
1068 *dest = qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
1069 break;
1070
1071 case nir_op_bcsel:
1072 qir_SF(c, src[0]);
1073 *dest = qir_SEL_X_Y_NS(c, src[1], src[2]);
1074 break;
1075 case nir_op_fcsel:
1076 qir_SF(c, src[0]);
1077 *dest = qir_SEL_X_Y_ZC(c, src[1], src[2]);
1078 break;
1079
1080 case nir_op_frcp:
1081 *dest = ntq_rcp(c, src[0]);
1082 break;
1083 case nir_op_frsq:
1084 *dest = ntq_rsq(c, src[0]);
1085 break;
1086 case nir_op_fexp2:
1087 *dest = qir_EXP2(c, src[0]);
1088 break;
1089 case nir_op_flog2:
1090 *dest = qir_LOG2(c, src[0]);
1091 break;
1092
1093 case nir_op_ftrunc:
1094 *dest = qir_ITOF(c, qir_FTOI(c, src[0]));
1095 break;
1096 case nir_op_fceil:
1097 *dest = ntq_fceil(c, src[0]);
1098 break;
1099 case nir_op_ffract:
1100 *dest = ntq_ffract(c, src[0]);
1101 break;
1102 case nir_op_ffloor:
1103 *dest = ntq_ffloor(c, src[0]);
1104 break;
1105
1106 case nir_op_fsin:
1107 *dest = ntq_fsin(c, src[0]);
1108 break;
1109 case nir_op_fcos:
1110 *dest = ntq_fcos(c, src[0]);
1111 break;
1112
1113 case nir_op_fsign:
1114 *dest = ntq_fsign(c, src[0]);
1115 break;
1116
1117 case nir_op_fabs:
1118 *dest = qir_FMAXABS(c, src[0], src[0]);
1119 break;
1120 case nir_op_iabs:
1121 *dest = qir_MAX(c, src[0],
1122 qir_SUB(c, qir_uniform_ui(c, 0), src[0]));
1123 break;
1124
1125 case nir_op_ibitfield_extract:
1126 *dest = ntq_emit_ibfe(c, src[0], src[1], src[2]);
1127 break;
1128
1129 case nir_op_ubitfield_extract:
1130 *dest = ntq_emit_ubfe(c, src[0], src[1], src[2]);
1131 break;
1132
1133 case nir_op_usadd_4x8:
1134 *dest = qir_V8ADDS(c, src[0], src[1]);
1135 break;
1136
1137 case nir_op_ussub_4x8:
1138 *dest = qir_V8SUBS(c, src[0], src[1]);
1139 break;
1140
1141 case nir_op_umin_4x8:
1142 *dest = qir_V8MIN(c, src[0], src[1]);
1143 break;
1144
1145 case nir_op_umax_4x8:
1146 *dest = qir_V8MAX(c, src[0], src[1]);
1147 break;
1148
1149 case nir_op_umul_unorm_4x8:
1150 *dest = qir_V8MULD(c, src[0], src[1]);
1151 break;
1152
1153 default:
1154 fprintf(stderr, "unknown NIR ALU inst: ");
1155 nir_print_instr(&instr->instr, stderr);
1156 fprintf(stderr, "\n");
1157 abort();
1158 }
1159 }
1160
1161 static void
1162 emit_frag_end(struct vc4_compile *c)
1163 {
1164 struct qreg color;
1165 if (c->output_color_index != -1) {
1166 color = c->outputs[c->output_color_index];
1167 } else {
1168 color = qir_uniform_ui(c, 0);
1169 }
1170
1171 if (c->discard.file != QFILE_NULL)
1172 qir_TLB_DISCARD_SETUP(c, c->discard);
1173
1174 if (c->fs_key->stencil_enabled) {
1175 qir_TLB_STENCIL_SETUP(c, qir_uniform(c, QUNIFORM_STENCIL, 0));
1176 if (c->fs_key->stencil_twoside) {
1177 qir_TLB_STENCIL_SETUP(c, qir_uniform(c, QUNIFORM_STENCIL, 1));
1178 }
1179 if (c->fs_key->stencil_full_writemasks) {
1180 qir_TLB_STENCIL_SETUP(c, qir_uniform(c, QUNIFORM_STENCIL, 2));
1181 }
1182 }
1183
1184 if (c->output_sample_mask_index != -1) {
1185 qir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1186 }
1187
1188 if (c->fs_key->depth_enabled) {
1189 struct qreg z;
1190 if (c->output_position_index != -1) {
1191 z = qir_FTOI(c, qir_FMUL(c, c->outputs[c->output_position_index + 2],
1192 qir_uniform_f(c, 0xffffff)));
1193 } else {
1194 z = qir_FRAG_Z(c);
1195 }
1196 qir_TLB_Z_WRITE(c, z);
1197 }
1198
1199 if (!c->msaa_per_sample_output) {
1200 qir_TLB_COLOR_WRITE(c, color);
1201 } else {
1202 for (int i = 0; i < VC4_MAX_SAMPLES; i++)
1203 qir_TLB_COLOR_WRITE_MS(c, c->sample_colors[i]);
1204 }
1205 }
1206
1207 static void
1208 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1209 {
1210 struct qreg packed = qir_get_temp(c);
1211
1212 for (int i = 0; i < 2; i++) {
1213 struct qreg scale =
1214 qir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1215
1216 struct qreg packed_chan = packed;
1217 packed_chan.pack = QPU_PACK_A_16A + i;
1218
1219 qir_FTOI_dest(c, packed_chan,
1220 qir_FMUL(c,
1221 qir_FMUL(c,
1222 c->outputs[c->output_position_index + i],
1223 scale),
1224 rcp_w));
1225 }
1226
1227 qir_VPM_WRITE(c, packed);
1228 }
1229
1230 static void
1231 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1232 {
1233 struct qreg zscale = qir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1234 struct qreg zoffset = qir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1235
1236 qir_VPM_WRITE(c, qir_FADD(c, qir_FMUL(c, qir_FMUL(c,
1237 c->outputs[c->output_position_index + 2],
1238 zscale),
1239 rcp_w),
1240 zoffset));
1241 }
1242
1243 static void
1244 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1245 {
1246 qir_VPM_WRITE(c, rcp_w);
1247 }
1248
1249 static void
1250 emit_point_size_write(struct vc4_compile *c)
1251 {
1252 struct qreg point_size;
1253
1254 if (c->output_point_size_index != -1)
1255 point_size = c->outputs[c->output_point_size_index];
1256 else
1257 point_size = qir_uniform_f(c, 1.0);
1258
1259 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1260 * BCM21553).
1261 */
1262 point_size = qir_FMAX(c, point_size, qir_uniform_f(c, .125));
1263
1264 qir_VPM_WRITE(c, point_size);
1265 }
1266
1267 /**
1268 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1269 *
1270 * The simulator insists that there be at least one vertex attribute, so
1271 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also
1272 * insists that all vertex attributes loaded get read by the VS/CS, so we have
1273 * to consume it here.
1274 */
1275 static void
1276 emit_stub_vpm_read(struct vc4_compile *c)
1277 {
1278 if (c->num_inputs)
1279 return;
1280
1281 c->vattr_sizes[0] = 4;
1282 struct qreg vpm = { QFILE_VPM, 0 };
1283 (void)qir_MOV(c, vpm);
1284 c->num_inputs++;
1285 }
1286
1287 static void
1288 emit_vert_end(struct vc4_compile *c,
1289 struct vc4_varying_slot *fs_inputs,
1290 uint32_t num_fs_inputs)
1291 {
1292 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1293
1294 emit_stub_vpm_read(c);
1295
1296 emit_scaled_viewport_write(c, rcp_w);
1297 emit_zs_write(c, rcp_w);
1298 emit_rcp_wc_write(c, rcp_w);
1299 if (c->vs_key->per_vertex_point_size)
1300 emit_point_size_write(c);
1301
1302 for (int i = 0; i < num_fs_inputs; i++) {
1303 struct vc4_varying_slot *input = &fs_inputs[i];
1304 int j;
1305
1306 for (j = 0; j < c->num_outputs; j++) {
1307 struct vc4_varying_slot *output =
1308 &c->output_slots[j];
1309
1310 if (input->slot == output->slot &&
1311 input->swizzle == output->swizzle) {
1312 qir_VPM_WRITE(c, c->outputs[j]);
1313 break;
1314 }
1315 }
1316 /* Emit padding if we didn't find a declared VS output for
1317 * this FS input.
1318 */
1319 if (j == c->num_outputs)
1320 qir_VPM_WRITE(c, qir_uniform_f(c, 0.0));
1321 }
1322 }
1323
1324 static void
1325 emit_coord_end(struct vc4_compile *c)
1326 {
1327 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1328
1329 emit_stub_vpm_read(c);
1330
1331 for (int i = 0; i < 4; i++)
1332 qir_VPM_WRITE(c, c->outputs[c->output_position_index + i]);
1333
1334 emit_scaled_viewport_write(c, rcp_w);
1335 emit_zs_write(c, rcp_w);
1336 emit_rcp_wc_write(c, rcp_w);
1337 if (c->vs_key->per_vertex_point_size)
1338 emit_point_size_write(c);
1339 }
1340
1341 static void
1342 vc4_optimize_nir(struct nir_shader *s)
1343 {
1344 bool progress;
1345
1346 do {
1347 progress = false;
1348
1349 nir_lower_vars_to_ssa(s);
1350 nir_lower_alu_to_scalar(s);
1351
1352 progress = nir_copy_prop(s) || progress;
1353 progress = nir_opt_dce(s) || progress;
1354 progress = nir_opt_cse(s) || progress;
1355 progress = nir_opt_peephole_select(s) || progress;
1356 progress = nir_opt_algebraic(s) || progress;
1357 progress = nir_opt_constant_folding(s) || progress;
1358 progress = nir_opt_undef(s) || progress;
1359 } while (progress);
1360 }
1361
1362 static int
1363 driver_location_compare(const void *in_a, const void *in_b)
1364 {
1365 const nir_variable *const *a = in_a;
1366 const nir_variable *const *b = in_b;
1367
1368 return (*a)->data.driver_location - (*b)->data.driver_location;
1369 }
1370
1371 static void
1372 ntq_setup_inputs(struct vc4_compile *c)
1373 {
1374 unsigned num_entries = 0;
1375 nir_foreach_variable(var, &c->s->inputs)
1376 num_entries++;
1377
1378 nir_variable *vars[num_entries];
1379
1380 unsigned i = 0;
1381 nir_foreach_variable(var, &c->s->inputs)
1382 vars[i++] = var;
1383
1384 /* Sort the variables so that we emit the input setup in
1385 * driver_location order. This is required for VPM reads, whose data
1386 * is fetched into the VPM in driver_location (TGSI register index)
1387 * order.
1388 */
1389 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1390
1391 for (unsigned i = 0; i < num_entries; i++) {
1392 nir_variable *var = vars[i];
1393 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1394 unsigned loc = var->data.driver_location;
1395
1396 assert(array_len == 1);
1397 (void)array_len;
1398 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1399 (loc + 1) * 4);
1400
1401 if (c->stage == QSTAGE_FRAG) {
1402 if (var->data.location == VARYING_SLOT_POS) {
1403 emit_fragcoord_input(c, loc);
1404 } else if (var->data.location == VARYING_SLOT_FACE) {
1405 c->inputs[loc * 4 + 0] = qir_FRAG_REV_FLAG(c);
1406 } else if (var->data.location >= VARYING_SLOT_VAR0 &&
1407 (c->fs_key->point_sprite_mask &
1408 (1 << (var->data.location -
1409 VARYING_SLOT_VAR0)))) {
1410 c->inputs[loc * 4 + 0] = c->point_x;
1411 c->inputs[loc * 4 + 1] = c->point_y;
1412 } else {
1413 emit_fragment_input(c, loc, var->data.location);
1414 }
1415 } else {
1416 emit_vertex_input(c, loc);
1417 }
1418 }
1419 }
1420
1421 static void
1422 ntq_setup_outputs(struct vc4_compile *c)
1423 {
1424 nir_foreach_variable(var, &c->s->outputs) {
1425 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1426 unsigned loc = var->data.driver_location * 4;
1427
1428 assert(array_len == 1);
1429 (void)array_len;
1430
1431 for (int i = 0; i < 4; i++)
1432 add_output(c, loc + i, var->data.location, i);
1433
1434 if (c->stage == QSTAGE_FRAG) {
1435 switch (var->data.location) {
1436 case FRAG_RESULT_COLOR:
1437 case FRAG_RESULT_DATA0:
1438 c->output_color_index = loc;
1439 break;
1440 case FRAG_RESULT_DEPTH:
1441 c->output_position_index = loc;
1442 break;
1443 case FRAG_RESULT_SAMPLE_MASK:
1444 c->output_sample_mask_index = loc;
1445 break;
1446 }
1447 } else {
1448 switch (var->data.location) {
1449 case VARYING_SLOT_POS:
1450 c->output_position_index = loc;
1451 break;
1452 case VARYING_SLOT_PSIZ:
1453 c->output_point_size_index = loc;
1454 break;
1455 }
1456 }
1457 }
1458 }
1459
1460 static void
1461 ntq_setup_uniforms(struct vc4_compile *c)
1462 {
1463 nir_foreach_variable(var, &c->s->uniforms) {
1464 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1465 unsigned array_elem_size = 4 * sizeof(float);
1466
1467 declare_uniform_range(c, var->data.driver_location * array_elem_size,
1468 array_len * array_elem_size);
1469
1470 }
1471 }
1472
1473 /**
1474 * Sets up the mapping from nir_register to struct qreg *.
1475 *
1476 * Each nir_register gets a struct qreg per 32-bit component being stored.
1477 */
1478 static void
1479 ntq_setup_registers(struct vc4_compile *c, struct exec_list *list)
1480 {
1481 foreach_list_typed(nir_register, nir_reg, node, list) {
1482 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1483 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1484 array_len *
1485 nir_reg->num_components);
1486
1487 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1488
1489 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1490 qregs[i] = qir_uniform_ui(c, 0);
1491 }
1492 }
1493
1494 static void
1495 ntq_emit_load_const(struct vc4_compile *c, nir_load_const_instr *instr)
1496 {
1497 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1498 for (int i = 0; i < instr->def.num_components; i++)
1499 qregs[i] = qir_uniform_ui(c, instr->value.u[i]);
1500
1501 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1502 }
1503
1504 static void
1505 ntq_emit_ssa_undef(struct vc4_compile *c, nir_ssa_undef_instr *instr)
1506 {
1507 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1508
1509 /* QIR needs there to be *some* value, so pick 0 (same as for
1510 * ntq_setup_registers().
1511 */
1512 for (int i = 0; i < instr->def.num_components; i++)
1513 qregs[i] = qir_uniform_ui(c, 0);
1514 }
1515
1516 static void
1517 ntq_emit_intrinsic(struct vc4_compile *c, nir_intrinsic_instr *instr)
1518 {
1519 const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
1520 nir_const_value *const_offset;
1521 unsigned offset;
1522 struct qreg *dest = NULL;
1523
1524 if (info->has_dest) {
1525 dest = ntq_get_dest(c, &instr->dest);
1526 }
1527
1528 switch (instr->intrinsic) {
1529 case nir_intrinsic_load_uniform:
1530 assert(instr->num_components == 1);
1531 const_offset = nir_src_as_const_value(instr->src[0]);
1532 if (const_offset) {
1533 offset = instr->const_index[0] + const_offset->u[0];
1534 assert(offset % 4 == 0);
1535 /* We need dwords */
1536 offset = offset / 4;
1537 if (offset < VC4_NIR_STATE_UNIFORM_OFFSET) {
1538 *dest = qir_uniform(c, QUNIFORM_UNIFORM,
1539 offset);
1540 } else {
1541 *dest = qir_uniform(c, offset -
1542 VC4_NIR_STATE_UNIFORM_OFFSET,
1543 0);
1544 }
1545 } else {
1546 *dest = indirect_uniform_load(c, instr);
1547 }
1548 break;
1549
1550 case nir_intrinsic_load_user_clip_plane:
1551 *dest = qir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1552 instr->const_index[0]);
1553 break;
1554
1555 case nir_intrinsic_load_sample_mask_in:
1556 *dest = qir_uniform(c, QUNIFORM_SAMPLE_MASK, 0);
1557 break;
1558
1559 case nir_intrinsic_load_input:
1560 assert(instr->num_components == 1);
1561 const_offset = nir_src_as_const_value(instr->src[0]);
1562 assert(const_offset && "vc4 doesn't support indirect inputs");
1563 if (instr->const_index[0] >= VC4_NIR_TLB_COLOR_READ_INPUT) {
1564 assert(const_offset->u[0] == 0);
1565 /* Reads of the per-sample color need to be done in
1566 * order.
1567 */
1568 int sample_index = (instr->const_index[0] -
1569 VC4_NIR_TLB_COLOR_READ_INPUT);
1570 for (int i = 0; i <= sample_index; i++) {
1571 if (c->color_reads[i].file == QFILE_NULL) {
1572 c->color_reads[i] =
1573 qir_TLB_COLOR_READ(c);
1574 }
1575 }
1576 *dest = c->color_reads[sample_index];
1577 } else {
1578 offset = instr->const_index[0] + const_offset->u[0];
1579 *dest = c->inputs[offset];
1580 }
1581 break;
1582
1583 case nir_intrinsic_store_output:
1584 const_offset = nir_src_as_const_value(instr->src[1]);
1585 assert(const_offset && "vc4 doesn't support indirect outputs");
1586 offset = instr->const_index[0] + const_offset->u[0];
1587
1588 /* MSAA color outputs are the only case where we have an
1589 * output that's not lowered to being a store of a single 32
1590 * bit value.
1591 */
1592 if (c->stage == QSTAGE_FRAG && instr->num_components == 4) {
1593 assert(offset == c->output_color_index);
1594 for (int i = 0; i < 4; i++) {
1595 c->sample_colors[i] =
1596 qir_MOV(c, ntq_get_src(c, instr->src[0],
1597 i));
1598 }
1599 } else {
1600 assert(instr->num_components == 1);
1601 c->outputs[offset] =
1602 qir_MOV(c, ntq_get_src(c, instr->src[0], 0));
1603 c->num_outputs = MAX2(c->num_outputs, offset + 1);
1604 }
1605 break;
1606
1607 case nir_intrinsic_discard:
1608 c->discard = qir_uniform_ui(c, ~0);
1609 break;
1610
1611 case nir_intrinsic_discard_if:
1612 if (c->discard.file == QFILE_NULL)
1613 c->discard = qir_uniform_ui(c, 0);
1614 c->discard = qir_OR(c, c->discard,
1615 ntq_get_src(c, instr->src[0], 0));
1616 break;
1617
1618 default:
1619 fprintf(stderr, "Unknown intrinsic: ");
1620 nir_print_instr(&instr->instr, stderr);
1621 fprintf(stderr, "\n");
1622 break;
1623 }
1624 }
1625
1626 static void
1627 ntq_emit_if(struct vc4_compile *c, nir_if *if_stmt)
1628 {
1629 fprintf(stderr, "general IF statements not handled.\n");
1630 }
1631
1632 static void
1633 ntq_emit_instr(struct vc4_compile *c, nir_instr *instr)
1634 {
1635 switch (instr->type) {
1636 case nir_instr_type_alu:
1637 ntq_emit_alu(c, nir_instr_as_alu(instr));
1638 break;
1639
1640 case nir_instr_type_intrinsic:
1641 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
1642 break;
1643
1644 case nir_instr_type_load_const:
1645 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
1646 break;
1647
1648 case nir_instr_type_ssa_undef:
1649 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
1650 break;
1651
1652 case nir_instr_type_tex:
1653 ntq_emit_tex(c, nir_instr_as_tex(instr));
1654 break;
1655
1656 default:
1657 fprintf(stderr, "Unknown NIR instr type: ");
1658 nir_print_instr(instr, stderr);
1659 fprintf(stderr, "\n");
1660 abort();
1661 }
1662 }
1663
1664 static void
1665 ntq_emit_block(struct vc4_compile *c, nir_block *block)
1666 {
1667 nir_foreach_instr(block, instr) {
1668 ntq_emit_instr(c, instr);
1669 }
1670 }
1671
1672 static void
1673 ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list)
1674 {
1675 foreach_list_typed(nir_cf_node, node, node, list) {
1676 switch (node->type) {
1677 /* case nir_cf_node_loop: */
1678 case nir_cf_node_block:
1679 ntq_emit_block(c, nir_cf_node_as_block(node));
1680 break;
1681
1682 case nir_cf_node_if:
1683 ntq_emit_if(c, nir_cf_node_as_if(node));
1684 break;
1685
1686 default:
1687 assert(0);
1688 }
1689 }
1690 }
1691
1692 static void
1693 ntq_emit_impl(struct vc4_compile *c, nir_function_impl *impl)
1694 {
1695 ntq_setup_registers(c, &impl->registers);
1696 ntq_emit_cf_list(c, &impl->body);
1697 }
1698
1699 static void
1700 nir_to_qir(struct vc4_compile *c)
1701 {
1702 ntq_setup_inputs(c);
1703 ntq_setup_outputs(c);
1704 ntq_setup_uniforms(c);
1705 ntq_setup_registers(c, &c->s->registers);
1706
1707 /* Find the main function and emit the body. */
1708 nir_foreach_overload(c->s, overload) {
1709 assert(strcmp(overload->function->name, "main") == 0);
1710 assert(overload->impl);
1711 ntq_emit_impl(c, overload->impl);
1712 }
1713 }
1714
1715 static const nir_shader_compiler_options nir_options = {
1716 .lower_ffma = true,
1717 .lower_flrp = true,
1718 .lower_fpow = true,
1719 .lower_fsat = true,
1720 .lower_fsqrt = true,
1721 .lower_negate = true,
1722 };
1723
1724 static bool
1725 count_nir_instrs_in_block(nir_block *block, void *state)
1726 {
1727 int *count = (int *) state;
1728 nir_foreach_instr(block, instr) {
1729 *count = *count + 1;
1730 }
1731 return true;
1732 }
1733
1734 static int
1735 count_nir_instrs(nir_shader *nir)
1736 {
1737 int count = 0;
1738 nir_foreach_overload(nir, overload) {
1739 if (!overload->impl)
1740 continue;
1741 nir_foreach_block(overload->impl, count_nir_instrs_in_block, &count);
1742 }
1743 return count;
1744 }
1745
1746 static struct vc4_compile *
1747 vc4_shader_ntq(struct vc4_context *vc4, enum qstage stage,
1748 struct vc4_key *key)
1749 {
1750 struct vc4_compile *c = qir_compile_init();
1751
1752 c->stage = stage;
1753 c->shader_state = &key->shader_state->base;
1754 c->program_id = key->shader_state->program_id;
1755 c->variant_id = key->shader_state->compiled_variant_count++;
1756
1757 c->key = key;
1758 switch (stage) {
1759 case QSTAGE_FRAG:
1760 c->fs_key = (struct vc4_fs_key *)key;
1761 if (c->fs_key->is_points) {
1762 c->point_x = emit_fragment_varying(c, ~0, 0);
1763 c->point_y = emit_fragment_varying(c, ~0, 0);
1764 } else if (c->fs_key->is_lines) {
1765 c->line_x = emit_fragment_varying(c, ~0, 0);
1766 }
1767 break;
1768 case QSTAGE_VERT:
1769 c->vs_key = (struct vc4_vs_key *)key;
1770 break;
1771 case QSTAGE_COORD:
1772 c->vs_key = (struct vc4_vs_key *)key;
1773 break;
1774 }
1775
1776 const struct tgsi_token *tokens = key->shader_state->base.tokens;
1777
1778 if (vc4_debug & VC4_DEBUG_TGSI) {
1779 fprintf(stderr, "%s prog %d/%d TGSI:\n",
1780 qir_get_stage_name(c->stage),
1781 c->program_id, c->variant_id);
1782 tgsi_dump(tokens, 0);
1783 }
1784
1785 c->s = tgsi_to_nir(tokens, &nir_options);
1786 nir_opt_global_to_local(c->s);
1787 nir_convert_to_ssa(c->s);
1788
1789 if (stage == QSTAGE_FRAG)
1790 vc4_nir_lower_blend(c);
1791
1792 if (c->fs_key && c->fs_key->light_twoside)
1793 nir_lower_two_sided_color(c->s);
1794
1795 if (stage == QSTAGE_FRAG)
1796 nir_lower_clip_fs(c->s, c->key->ucp_enables);
1797 else
1798 nir_lower_clip_vs(c->s, c->key->ucp_enables);
1799
1800 vc4_nir_lower_io(c);
1801 vc4_nir_lower_txf_ms(c);
1802 nir_lower_idiv(c->s);
1803 nir_lower_load_const_to_scalar(c->s);
1804
1805 vc4_optimize_nir(c->s);
1806
1807 nir_remove_dead_variables(c->s);
1808
1809 nir_convert_from_ssa(c->s, true);
1810
1811 if (vc4_debug & VC4_DEBUG_SHADERDB) {
1812 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d NIR instructions\n",
1813 qir_get_stage_name(c->stage),
1814 c->program_id, c->variant_id,
1815 count_nir_instrs(c->s));
1816 }
1817
1818 if (vc4_debug & VC4_DEBUG_NIR) {
1819 fprintf(stderr, "%s prog %d/%d NIR:\n",
1820 qir_get_stage_name(c->stage),
1821 c->program_id, c->variant_id);
1822 nir_print_shader(c->s, stderr);
1823 }
1824
1825 nir_to_qir(c);
1826
1827 switch (stage) {
1828 case QSTAGE_FRAG:
1829 emit_frag_end(c);
1830 break;
1831 case QSTAGE_VERT:
1832 emit_vert_end(c,
1833 vc4->prog.fs->input_slots,
1834 vc4->prog.fs->num_inputs);
1835 break;
1836 case QSTAGE_COORD:
1837 emit_coord_end(c);
1838 break;
1839 }
1840
1841 if (vc4_debug & VC4_DEBUG_QIR) {
1842 fprintf(stderr, "%s prog %d/%d pre-opt QIR:\n",
1843 qir_get_stage_name(c->stage),
1844 c->program_id, c->variant_id);
1845 qir_dump(c);
1846 }
1847
1848 qir_optimize(c);
1849 qir_lower_uniforms(c);
1850
1851 qir_schedule_instructions(c);
1852
1853 if (vc4_debug & VC4_DEBUG_QIR) {
1854 fprintf(stderr, "%s prog %d/%d QIR:\n",
1855 qir_get_stage_name(c->stage),
1856 c->program_id, c->variant_id);
1857 qir_dump(c);
1858 }
1859
1860 qir_reorder_uniforms(c);
1861 vc4_generate_code(vc4, c);
1862
1863 if (vc4_debug & VC4_DEBUG_SHADERDB) {
1864 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d instructions\n",
1865 qir_get_stage_name(c->stage),
1866 c->program_id, c->variant_id,
1867 c->qpu_inst_count);
1868 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d uniforms\n",
1869 qir_get_stage_name(c->stage),
1870 c->program_id, c->variant_id,
1871 c->num_uniforms);
1872 }
1873
1874 ralloc_free(c->s);
1875
1876 return c;
1877 }
1878
1879 static void *
1880 vc4_shader_state_create(struct pipe_context *pctx,
1881 const struct pipe_shader_state *cso)
1882 {
1883 struct vc4_context *vc4 = vc4_context(pctx);
1884 struct vc4_uncompiled_shader *so = CALLOC_STRUCT(vc4_uncompiled_shader);
1885 if (!so)
1886 return NULL;
1887
1888 so->base.tokens = tgsi_dup_tokens(cso->tokens);
1889 so->program_id = vc4->next_uncompiled_program_id++;
1890
1891 return so;
1892 }
1893
1894 static void
1895 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
1896 struct vc4_compile *c)
1897 {
1898 int count = c->num_uniforms;
1899 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
1900
1901 uinfo->count = count;
1902 uinfo->data = ralloc_array(shader, uint32_t, count);
1903 memcpy(uinfo->data, c->uniform_data,
1904 count * sizeof(*uinfo->data));
1905 uinfo->contents = ralloc_array(shader, enum quniform_contents, count);
1906 memcpy(uinfo->contents, c->uniform_contents,
1907 count * sizeof(*uinfo->contents));
1908 uinfo->num_texture_samples = c->num_texture_samples;
1909
1910 vc4_set_shader_uniform_dirty_flags(shader);
1911 }
1912
1913 static struct vc4_compiled_shader *
1914 vc4_get_compiled_shader(struct vc4_context *vc4, enum qstage stage,
1915 struct vc4_key *key)
1916 {
1917 struct hash_table *ht;
1918 uint32_t key_size;
1919 if (stage == QSTAGE_FRAG) {
1920 ht = vc4->fs_cache;
1921 key_size = sizeof(struct vc4_fs_key);
1922 } else {
1923 ht = vc4->vs_cache;
1924 key_size = sizeof(struct vc4_vs_key);
1925 }
1926
1927 struct vc4_compiled_shader *shader;
1928 struct hash_entry *entry = _mesa_hash_table_search(ht, key);
1929 if (entry)
1930 return entry->data;
1931
1932 struct vc4_compile *c = vc4_shader_ntq(vc4, stage, key);
1933 shader = rzalloc(NULL, struct vc4_compiled_shader);
1934
1935 shader->program_id = vc4->next_compiled_program_id++;
1936 if (stage == QSTAGE_FRAG) {
1937 bool input_live[c->num_input_slots];
1938
1939 memset(input_live, 0, sizeof(input_live));
1940 list_for_each_entry(struct qinst, inst, &c->instructions, link) {
1941 for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) {
1942 if (inst->src[i].file == QFILE_VARY)
1943 input_live[inst->src[i].index] = true;
1944 }
1945 }
1946
1947 shader->input_slots = ralloc_array(shader,
1948 struct vc4_varying_slot,
1949 c->num_input_slots);
1950
1951 for (int i = 0; i < c->num_input_slots; i++) {
1952 struct vc4_varying_slot *slot = &c->input_slots[i];
1953
1954 if (!input_live[i])
1955 continue;
1956
1957 /* Skip non-VS-output inputs. */
1958 if (slot->slot == (uint8_t)~0)
1959 continue;
1960
1961 if (slot->slot == VARYING_SLOT_COL0 ||
1962 slot->slot == VARYING_SLOT_COL1 ||
1963 slot->slot == VARYING_SLOT_BFC0 ||
1964 slot->slot == VARYING_SLOT_BFC1) {
1965 shader->color_inputs |= (1 << shader->num_inputs);
1966 }
1967
1968 shader->input_slots[shader->num_inputs] = *slot;
1969 shader->num_inputs++;
1970 }
1971 } else {
1972 shader->num_inputs = c->num_inputs;
1973
1974 shader->vattr_offsets[0] = 0;
1975 for (int i = 0; i < 8; i++) {
1976 shader->vattr_offsets[i + 1] =
1977 shader->vattr_offsets[i] + c->vattr_sizes[i];
1978
1979 if (c->vattr_sizes[i])
1980 shader->vattrs_live |= (1 << i);
1981 }
1982 }
1983
1984 copy_uniform_state_to_shader(shader, c);
1985 shader->bo = vc4_bo_alloc_shader(vc4->screen, c->qpu_insts,
1986 c->qpu_inst_count * sizeof(uint64_t));
1987
1988 /* Copy the compiler UBO range state to the compiled shader, dropping
1989 * out arrays that were never referenced by an indirect load.
1990 *
1991 * (Note that QIR dead code elimination of an array access still
1992 * leaves that array alive, though)
1993 */
1994 if (c->num_ubo_ranges) {
1995 shader->num_ubo_ranges = c->num_ubo_ranges;
1996 shader->ubo_ranges = ralloc_array(shader, struct vc4_ubo_range,
1997 c->num_ubo_ranges);
1998 uint32_t j = 0;
1999 for (int i = 0; i < c->num_uniform_ranges; i++) {
2000 struct vc4_compiler_ubo_range *range =
2001 &c->ubo_ranges[i];
2002 if (!range->used)
2003 continue;
2004
2005 shader->ubo_ranges[j].dst_offset = range->dst_offset;
2006 shader->ubo_ranges[j].src_offset = range->src_offset;
2007 shader->ubo_ranges[j].size = range->size;
2008 shader->ubo_size += c->ubo_ranges[i].size;
2009 j++;
2010 }
2011 }
2012 if (shader->ubo_size) {
2013 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2014 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d UBO uniforms\n",
2015 qir_get_stage_name(c->stage),
2016 c->program_id, c->variant_id,
2017 shader->ubo_size / 4);
2018 }
2019 }
2020
2021 qir_compile_destroy(c);
2022
2023 struct vc4_key *dup_key;
2024 dup_key = ralloc_size(shader, key_size);
2025 memcpy(dup_key, key, key_size);
2026 _mesa_hash_table_insert(ht, dup_key, shader);
2027
2028 return shader;
2029 }
2030
2031 static void
2032 vc4_setup_shared_key(struct vc4_context *vc4, struct vc4_key *key,
2033 struct vc4_texture_stateobj *texstate)
2034 {
2035 for (int i = 0; i < texstate->num_textures; i++) {
2036 struct pipe_sampler_view *sampler = texstate->textures[i];
2037 struct pipe_sampler_state *sampler_state =
2038 texstate->samplers[i];
2039
2040 if (!sampler)
2041 continue;
2042
2043 key->tex[i].format = sampler->format;
2044 key->tex[i].swizzle[0] = sampler->swizzle_r;
2045 key->tex[i].swizzle[1] = sampler->swizzle_g;
2046 key->tex[i].swizzle[2] = sampler->swizzle_b;
2047 key->tex[i].swizzle[3] = sampler->swizzle_a;
2048
2049 if (sampler->texture->nr_samples > 1) {
2050 key->tex[i].msaa_width = sampler->texture->width0;
2051 key->tex[i].msaa_height = sampler->texture->height0;
2052 } else if (sampler){
2053 key->tex[i].compare_mode = sampler_state->compare_mode;
2054 key->tex[i].compare_func = sampler_state->compare_func;
2055 key->tex[i].wrap_s = sampler_state->wrap_s;
2056 key->tex[i].wrap_t = sampler_state->wrap_t;
2057 }
2058 }
2059
2060 key->ucp_enables = vc4->rasterizer->base.clip_plane_enable;
2061 }
2062
2063 static void
2064 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
2065 {
2066 struct vc4_fs_key local_key;
2067 struct vc4_fs_key *key = &local_key;
2068
2069 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2070 VC4_DIRTY_BLEND |
2071 VC4_DIRTY_FRAMEBUFFER |
2072 VC4_DIRTY_ZSA |
2073 VC4_DIRTY_RASTERIZER |
2074 VC4_DIRTY_FRAGTEX |
2075 VC4_DIRTY_TEXSTATE |
2076 VC4_DIRTY_UNCOMPILED_FS))) {
2077 return;
2078 }
2079
2080 memset(key, 0, sizeof(*key));
2081 vc4_setup_shared_key(vc4, &key->base, &vc4->fragtex);
2082 key->base.shader_state = vc4->prog.bind_fs;
2083 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
2084 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
2085 prim_mode <= PIPE_PRIM_LINE_STRIP);
2086 key->blend = vc4->blend->rt[0];
2087 if (vc4->blend->logicop_enable) {
2088 key->logicop_func = vc4->blend->logicop_func;
2089 } else {
2090 key->logicop_func = PIPE_LOGICOP_COPY;
2091 }
2092 key->msaa = vc4->rasterizer->base.multisample;
2093 key->sample_coverage = (vc4->rasterizer->base.multisample &&
2094 vc4->sample_mask != (1 << VC4_MAX_SAMPLES) - 1);
2095 key->sample_alpha_to_coverage = vc4->blend->alpha_to_coverage;
2096 key->sample_alpha_to_one = vc4->blend->alpha_to_one;
2097 if (vc4->framebuffer.cbufs[0])
2098 key->color_format = vc4->framebuffer.cbufs[0]->format;
2099
2100 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
2101 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
2102 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
2103 key->depth_enabled = (vc4->zsa->base.depth.enabled ||
2104 key->stencil_enabled);
2105 if (vc4->zsa->base.alpha.enabled) {
2106 key->alpha_test = true;
2107 key->alpha_test_func = vc4->zsa->base.alpha.func;
2108 }
2109
2110 if (key->is_points) {
2111 key->point_sprite_mask =
2112 vc4->rasterizer->base.sprite_coord_enable;
2113 key->point_coord_upper_left =
2114 (vc4->rasterizer->base.sprite_coord_mode ==
2115 PIPE_SPRITE_COORD_UPPER_LEFT);
2116 }
2117
2118 key->light_twoside = vc4->rasterizer->base.light_twoside;
2119
2120 struct vc4_compiled_shader *old_fs = vc4->prog.fs;
2121 vc4->prog.fs = vc4_get_compiled_shader(vc4, QSTAGE_FRAG, &key->base);
2122 if (vc4->prog.fs == old_fs)
2123 return;
2124
2125 vc4->dirty |= VC4_DIRTY_COMPILED_FS;
2126 if (vc4->rasterizer->base.flatshade &&
2127 old_fs && vc4->prog.fs->color_inputs != old_fs->color_inputs) {
2128 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
2129 }
2130 }
2131
2132 static void
2133 vc4_update_compiled_vs(struct vc4_context *vc4, uint8_t prim_mode)
2134 {
2135 struct vc4_vs_key local_key;
2136 struct vc4_vs_key *key = &local_key;
2137
2138 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2139 VC4_DIRTY_RASTERIZER |
2140 VC4_DIRTY_VERTTEX |
2141 VC4_DIRTY_TEXSTATE |
2142 VC4_DIRTY_VTXSTATE |
2143 VC4_DIRTY_UNCOMPILED_VS |
2144 VC4_DIRTY_COMPILED_FS))) {
2145 return;
2146 }
2147
2148 memset(key, 0, sizeof(*key));
2149 vc4_setup_shared_key(vc4, &key->base, &vc4->verttex);
2150 key->base.shader_state = vc4->prog.bind_vs;
2151 key->compiled_fs_id = vc4->prog.fs->program_id;
2152
2153 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
2154 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
2155
2156 key->per_vertex_point_size =
2157 (prim_mode == PIPE_PRIM_POINTS &&
2158 vc4->rasterizer->base.point_size_per_vertex);
2159
2160 struct vc4_compiled_shader *vs =
2161 vc4_get_compiled_shader(vc4, QSTAGE_VERT, &key->base);
2162 if (vs != vc4->prog.vs) {
2163 vc4->prog.vs = vs;
2164 vc4->dirty |= VC4_DIRTY_COMPILED_VS;
2165 }
2166
2167 key->is_coord = true;
2168 struct vc4_compiled_shader *cs =
2169 vc4_get_compiled_shader(vc4, QSTAGE_COORD, &key->base);
2170 if (cs != vc4->prog.cs) {
2171 vc4->prog.cs = cs;
2172 vc4->dirty |= VC4_DIRTY_COMPILED_CS;
2173 }
2174 }
2175
2176 void
2177 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
2178 {
2179 vc4_update_compiled_fs(vc4, prim_mode);
2180 vc4_update_compiled_vs(vc4, prim_mode);
2181 }
2182
2183 static uint32_t
2184 fs_cache_hash(const void *key)
2185 {
2186 return _mesa_hash_data(key, sizeof(struct vc4_fs_key));
2187 }
2188
2189 static uint32_t
2190 vs_cache_hash(const void *key)
2191 {
2192 return _mesa_hash_data(key, sizeof(struct vc4_vs_key));
2193 }
2194
2195 static bool
2196 fs_cache_compare(const void *key1, const void *key2)
2197 {
2198 return memcmp(key1, key2, sizeof(struct vc4_fs_key)) == 0;
2199 }
2200
2201 static bool
2202 vs_cache_compare(const void *key1, const void *key2)
2203 {
2204 return memcmp(key1, key2, sizeof(struct vc4_vs_key)) == 0;
2205 }
2206
2207 static void
2208 delete_from_cache_if_matches(struct hash_table *ht,
2209 struct hash_entry *entry,
2210 struct vc4_uncompiled_shader *so)
2211 {
2212 const struct vc4_key *key = entry->key;
2213
2214 if (key->shader_state == so) {
2215 struct vc4_compiled_shader *shader = entry->data;
2216 _mesa_hash_table_remove(ht, entry);
2217 vc4_bo_unreference(&shader->bo);
2218 ralloc_free(shader);
2219 }
2220 }
2221
2222 static void
2223 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
2224 {
2225 struct vc4_context *vc4 = vc4_context(pctx);
2226 struct vc4_uncompiled_shader *so = hwcso;
2227
2228 struct hash_entry *entry;
2229 hash_table_foreach(vc4->fs_cache, entry)
2230 delete_from_cache_if_matches(vc4->fs_cache, entry, so);
2231 hash_table_foreach(vc4->vs_cache, entry)
2232 delete_from_cache_if_matches(vc4->vs_cache, entry, so);
2233
2234 free((void *)so->base.tokens);
2235 free(so);
2236 }
2237
2238 static void
2239 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
2240 {
2241 struct vc4_context *vc4 = vc4_context(pctx);
2242 vc4->prog.bind_fs = hwcso;
2243 vc4->dirty |= VC4_DIRTY_UNCOMPILED_FS;
2244 }
2245
2246 static void
2247 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
2248 {
2249 struct vc4_context *vc4 = vc4_context(pctx);
2250 vc4->prog.bind_vs = hwcso;
2251 vc4->dirty |= VC4_DIRTY_UNCOMPILED_VS;
2252 }
2253
2254 void
2255 vc4_program_init(struct pipe_context *pctx)
2256 {
2257 struct vc4_context *vc4 = vc4_context(pctx);
2258
2259 pctx->create_vs_state = vc4_shader_state_create;
2260 pctx->delete_vs_state = vc4_shader_state_delete;
2261
2262 pctx->create_fs_state = vc4_shader_state_create;
2263 pctx->delete_fs_state = vc4_shader_state_delete;
2264
2265 pctx->bind_fs_state = vc4_fp_state_bind;
2266 pctx->bind_vs_state = vc4_vp_state_bind;
2267
2268 vc4->fs_cache = _mesa_hash_table_create(pctx, fs_cache_hash,
2269 fs_cache_compare);
2270 vc4->vs_cache = _mesa_hash_table_create(pctx, vs_cache_hash,
2271 vs_cache_compare);
2272 }
2273
2274 void
2275 vc4_program_fini(struct pipe_context *pctx)
2276 {
2277 struct vc4_context *vc4 = vc4_context(pctx);
2278
2279 struct hash_entry *entry;
2280 hash_table_foreach(vc4->fs_cache, entry) {
2281 struct vc4_compiled_shader *shader = entry->data;
2282 vc4_bo_unreference(&shader->bo);
2283 ralloc_free(shader);
2284 _mesa_hash_table_remove(vc4->fs_cache, entry);
2285 }
2286
2287 hash_table_foreach(vc4->vs_cache, entry) {
2288 struct vc4_compiled_shader *shader = entry->data;
2289 vc4_bo_unreference(&shader->bo);
2290 ralloc_free(shader);
2291 _mesa_hash_table_remove(vc4->vs_cache, entry);
2292 }
2293 }