vc4: Add a CSE optimization pass.
[mesa.git] / src / gallium / drivers / vc4 / vc4_qir.h
1 /*
2 * Copyright © 2014 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef VC4_QIR_H
25 #define VC4_QIR_H
26
27 #include <stdio.h>
28 #include <stdlib.h>
29 #include <stdbool.h>
30 #include <stdint.h>
31 #include <string.h>
32
33 #include "util/u_simple_list.h"
34
35 enum qfile {
36 QFILE_NULL,
37 QFILE_TEMP,
38 QFILE_VARY,
39 QFILE_UNIF,
40 };
41
42 struct qreg {
43 enum qfile file;
44 uint32_t index;
45 };
46
47 enum qop {
48 QOP_UNDEF,
49 QOP_MOV,
50 QOP_FADD,
51 QOP_FSUB,
52 QOP_FMUL,
53 QOP_MUL24,
54 QOP_FMIN,
55 QOP_FMAX,
56 QOP_FMINABS,
57 QOP_FMAXABS,
58 QOP_ADD,
59 QOP_SUB,
60 QOP_SHL,
61 QOP_SHR,
62 QOP_ASR,
63 QOP_MIN,
64 QOP_MAX,
65 QOP_AND,
66 QOP_OR,
67 QOP_XOR,
68 QOP_NOT,
69
70 /* Sets the flag register according to src. */
71 QOP_SF,
72
73 /* Note: Orderings of these compares must be the same as in
74 * qpu_defines.h. Selects the src[0] if the ns flag bit is set,
75 * otherwise 0. */
76 QOP_SEL_X_0_ZS,
77 QOP_SEL_X_0_ZC,
78 QOP_SEL_X_0_NS,
79 QOP_SEL_X_0_NC,
80 /* Selects the src[0] if the ns flag bit is set, otherwise src[1]. */
81 QOP_SEL_X_Y_ZS,
82 QOP_SEL_X_Y_ZC,
83 QOP_SEL_X_Y_NS,
84 QOP_SEL_X_Y_NC,
85
86 QOP_FTOI,
87 QOP_ITOF,
88 QOP_RCP,
89 QOP_RSQ,
90 QOP_EXP2,
91 QOP_LOG2,
92 QOP_VW_SETUP,
93 QOP_VR_SETUP,
94 QOP_PACK_SCALED,
95 QOP_PACK_COLORS,
96 QOP_VPM_WRITE,
97 QOP_VPM_READ,
98 QOP_TLB_DISCARD_SETUP,
99 QOP_TLB_PASSTHROUGH_Z_WRITE,
100 QOP_TLB_COLOR_WRITE,
101 QOP_TLB_COLOR_READ,
102 QOP_VARY_ADD_C,
103
104 QOP_FRAG_X,
105 QOP_FRAG_Y,
106 QOP_FRAG_Z,
107 QOP_FRAG_RCP_W,
108
109 /** Texture x coordinate parameter write */
110 QOP_TEX_S,
111 /** Texture y coordinate parameter write */
112 QOP_TEX_T,
113 /** Texture border color parameter or cube map z coordinate write */
114 QOP_TEX_R,
115 /** Texture LOD bias parameter write */
116 QOP_TEX_B,
117 /**
118 * Signal of texture read being necessary and then reading r4 into
119 * the destination
120 */
121 QOP_TEX_RESULT,
122 QOP_R4_UNPACK_A,
123 QOP_R4_UNPACK_B,
124 QOP_R4_UNPACK_C,
125 QOP_R4_UNPACK_D
126 };
127
128 struct simple_node {
129 struct simple_node *next;
130 struct simple_node *prev;
131 };
132
133 struct qinst {
134 struct simple_node link;
135
136 enum qop op;
137 struct qreg dst;
138 struct qreg *src;
139 };
140
141 enum qstage {
142 /**
143 * Coordinate shader, runs during binning, before the VS, and just
144 * outputs position.
145 */
146 QSTAGE_COORD,
147 QSTAGE_VERT,
148 QSTAGE_FRAG,
149 };
150
151 enum quniform_contents {
152 /**
153 * Indicates that a constant 32-bit value is copied from the program's
154 * uniform contents.
155 */
156 QUNIFORM_CONSTANT,
157 /**
158 * Indicates that the program's uniform contents are used as an index
159 * into the GL uniform storage.
160 */
161 QUNIFORM_UNIFORM,
162
163 /** @{
164 * Scaling factors from clip coordinates to relative to the viewport
165 * center.
166 *
167 * This is used by the coordinate and vertex shaders to produce the
168 * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed
169 * point offsets from the viewport ccenter.
170 */
171 QUNIFORM_VIEWPORT_X_SCALE,
172 QUNIFORM_VIEWPORT_Y_SCALE,
173 /** @} */
174
175 QUNIFORM_VIEWPORT_Z_OFFSET,
176 QUNIFORM_VIEWPORT_Z_SCALE,
177
178 /**
179 * A reference to a texture config parameter 0 uniform.
180 *
181 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
182 * defines texture type, miplevels, and such. It will be found as a
183 * parameter to the first QOP_TEX_[STRB] instruction in a sequence.
184 */
185 QUNIFORM_TEXTURE_CONFIG_P0,
186
187 /**
188 * A reference to a texture config parameter 1 uniform.
189 *
190 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
191 * defines texture width, height, filters, and wrap modes. It will be
192 * found as a parameter to the second QOP_TEX_[STRB] instruction in a
193 * sequence.
194 */
195 QUNIFORM_TEXTURE_CONFIG_P1,
196
197 QUNIFORM_TEXRECT_SCALE_X,
198 QUNIFORM_TEXRECT_SCALE_Y,
199
200 QUNIFORM_BLEND_CONST_COLOR,
201 };
202
203 struct qcompile {
204 struct qreg undef;
205 enum qstage stage;
206 uint32_t num_temps;
207 struct simple_node instructions;
208 uint32_t immediates[1024];
209
210 struct simple_node qpu_inst_list;
211 uint64_t *qpu_insts;
212 uint32_t qpu_inst_count;
213 uint32_t qpu_inst_size;
214 uint32_t num_inputs;
215 };
216
217 struct qcompile *qir_compile_init(void);
218 void qir_compile_destroy(struct qcompile *c);
219 struct qinst *qir_inst(enum qop op, struct qreg dst,
220 struct qreg src0, struct qreg src1);
221 struct qinst *qir_inst4(enum qop op, struct qreg dst,
222 struct qreg a,
223 struct qreg b,
224 struct qreg c,
225 struct qreg d);
226 void qir_emit(struct qcompile *c, struct qinst *inst);
227 struct qreg qir_get_temp(struct qcompile *c);
228 int qir_get_op_nsrc(enum qop qop);
229 bool qir_reg_equals(struct qreg a, struct qreg b);
230 bool qir_has_side_effects(struct qinst *inst);
231 bool qir_depends_on_flags(struct qinst *inst);
232 bool qir_writes_r4(struct qinst *inst);
233 bool qir_reads_r4(struct qinst *inst);
234
235 void qir_dump(struct qcompile *c);
236 void qir_dump_inst(struct qinst *inst);
237 const char *qir_get_stage_name(enum qstage stage);
238
239 void qir_optimize(struct qcompile *c);
240 bool qir_opt_algebraic(struct qcompile *c);
241 bool qir_opt_copy_propagation(struct qcompile *c);
242 bool qir_opt_cse(struct qcompile *c);
243 bool qir_opt_dead_code(struct qcompile *c);
244
245 #define QIR_ALU0(name) \
246 static inline struct qreg \
247 qir_##name(struct qcompile *c) \
248 { \
249 struct qreg t = qir_get_temp(c); \
250 qir_emit(c, qir_inst(QOP_##name, t, c->undef, c->undef)); \
251 return t; \
252 }
253
254 #define QIR_ALU1(name) \
255 static inline struct qreg \
256 qir_##name(struct qcompile *c, struct qreg a) \
257 { \
258 struct qreg t = qir_get_temp(c); \
259 qir_emit(c, qir_inst(QOP_##name, t, a, c->undef)); \
260 return t; \
261 }
262
263 #define QIR_ALU2(name) \
264 static inline struct qreg \
265 qir_##name(struct qcompile *c, struct qreg a, struct qreg b) \
266 { \
267 struct qreg t = qir_get_temp(c); \
268 qir_emit(c, qir_inst(QOP_##name, t, a, b)); \
269 return t; \
270 }
271
272 #define QIR_NODST_1(name) \
273 static inline void \
274 qir_##name(struct qcompile *c, struct qreg a) \
275 { \
276 qir_emit(c, qir_inst(QOP_##name, c->undef, a, c->undef)); \
277 }
278
279 #define QIR_NODST_2(name) \
280 static inline void \
281 qir_##name(struct qcompile *c, struct qreg a, struct qreg b) \
282 { \
283 qir_emit(c, qir_inst(QOP_##name, c->undef, a, b)); \
284 }
285
286 QIR_ALU1(MOV)
287 QIR_ALU2(FADD)
288 QIR_ALU2(FSUB)
289 QIR_ALU2(FMUL)
290 QIR_ALU2(MUL24)
291 QIR_NODST_1(SF)
292 QIR_ALU1(SEL_X_0_ZS)
293 QIR_ALU1(SEL_X_0_ZC)
294 QIR_ALU1(SEL_X_0_NS)
295 QIR_ALU1(SEL_X_0_NC)
296 QIR_ALU2(SEL_X_Y_ZS)
297 QIR_ALU2(SEL_X_Y_ZC)
298 QIR_ALU2(SEL_X_Y_NS)
299 QIR_ALU2(SEL_X_Y_NC)
300 QIR_ALU2(FMIN)
301 QIR_ALU2(FMAX)
302 QIR_ALU2(FMINABS)
303 QIR_ALU2(FMAXABS)
304 QIR_ALU1(FTOI)
305 QIR_ALU1(ITOF)
306
307 QIR_ALU2(ADD)
308 QIR_ALU2(SUB)
309 QIR_ALU2(SHL)
310 QIR_ALU2(SHR)
311 QIR_ALU2(ASR)
312 QIR_ALU2(MIN)
313 QIR_ALU2(MAX)
314 QIR_ALU2(AND)
315 QIR_ALU2(OR)
316 QIR_ALU2(XOR)
317 QIR_ALU1(NOT)
318
319 QIR_ALU1(RCP)
320 QIR_ALU1(RSQ)
321 QIR_ALU1(EXP2)
322 QIR_ALU1(LOG2)
323 QIR_ALU2(PACK_SCALED)
324 QIR_ALU1(VARY_ADD_C)
325 QIR_NODST_1(VPM_WRITE)
326 QIR_NODST_2(TEX_S)
327 QIR_NODST_2(TEX_T)
328 QIR_NODST_2(TEX_R)
329 QIR_NODST_2(TEX_B)
330 QIR_ALU0(FRAG_X)
331 QIR_ALU0(FRAG_Y)
332 QIR_ALU0(FRAG_Z)
333 QIR_ALU0(FRAG_RCP_W)
334 QIR_NODST_1(TLB_DISCARD_SETUP)
335
336 static inline struct qreg
337 qir_R4_UNPACK(struct qcompile *c, int i)
338 {
339 struct qreg t = qir_get_temp(c);
340 qir_emit(c, qir_inst(QOP_R4_UNPACK_A + i, t, c->undef, c->undef));
341 return t;
342 }
343
344 static inline struct qreg
345 qir_SEL_X_0_COND(struct qcompile *c, int i)
346 {
347 struct qreg t = qir_get_temp(c);
348 qir_emit(c, qir_inst(QOP_R4_UNPACK_A + i, t, c->undef, c->undef));
349 return t;
350 }
351
352 #endif /* VC4_QIR_H */