7d2bdc093ef4b4a16e3313f85e85d2c1472da5d5
[mesa.git] / src / gallium / drivers / vc4 / vc4_qir.h
1 /*
2 * Copyright © 2014 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef VC4_QIR_H
25 #define VC4_QIR_H
26
27 #include <assert.h>
28 #include <stdio.h>
29 #include <stdlib.h>
30 #include <stdbool.h>
31 #include <stdint.h>
32 #include <string.h>
33
34 #include "util/macros.h"
35 #include "compiler/nir/nir.h"
36 #include "util/list.h"
37 #include "util/u_math.h"
38
39 #include "vc4_screen.h"
40 #include "vc4_qpu_defines.h"
41 #include "kernel/vc4_packet.h"
42 #include "pipe/p_state.h"
43
44 struct nir_builder;
45
46 enum qfile {
47 QFILE_NULL,
48 QFILE_TEMP,
49 QFILE_VARY,
50 QFILE_UNIF,
51 QFILE_VPM,
52 QFILE_TLB_COLOR_WRITE,
53 QFILE_TLB_COLOR_WRITE_MS,
54 QFILE_TLB_Z_WRITE,
55 QFILE_TLB_STENCIL_SETUP,
56
57 /* Payload registers that aren't in the physical register file, so we
58 * can just use the corresponding qpu_reg at qpu_emit time.
59 */
60 QFILE_FRAG_X,
61 QFILE_FRAG_Y,
62 QFILE_FRAG_REV_FLAG,
63
64 /**
65 * Stores an immediate value in the index field that can be turned
66 * into a small immediate field by qpu_encode_small_immediate().
67 */
68 QFILE_SMALL_IMM,
69 };
70
71 struct qreg {
72 enum qfile file;
73 uint32_t index;
74 int pack;
75 };
76
77 static inline struct qreg qir_reg(enum qfile file, uint32_t index)
78 {
79 return (struct qreg){file, index};
80 }
81
82 enum qop {
83 QOP_UNDEF,
84 QOP_MOV,
85 QOP_FMOV,
86 QOP_MMOV,
87 QOP_FADD,
88 QOP_FSUB,
89 QOP_FMUL,
90 QOP_V8MULD,
91 QOP_V8MIN,
92 QOP_V8MAX,
93 QOP_V8ADDS,
94 QOP_V8SUBS,
95 QOP_MUL24,
96 QOP_FMIN,
97 QOP_FMAX,
98 QOP_FMINABS,
99 QOP_FMAXABS,
100 QOP_ADD,
101 QOP_SUB,
102 QOP_SHL,
103 QOP_SHR,
104 QOP_ASR,
105 QOP_MIN,
106 QOP_MAX,
107 QOP_AND,
108 QOP_OR,
109 QOP_XOR,
110 QOP_NOT,
111
112 QOP_FTOI,
113 QOP_ITOF,
114 QOP_RCP,
115 QOP_RSQ,
116 QOP_EXP2,
117 QOP_LOG2,
118 QOP_VW_SETUP,
119 QOP_VR_SETUP,
120 QOP_TLB_COLOR_READ,
121 QOP_MS_MASK,
122 QOP_VARY_ADD_C,
123
124 QOP_FRAG_Z,
125 QOP_FRAG_W,
126
127 /** Texture x coordinate parameter write */
128 QOP_TEX_S,
129 /** Texture y coordinate parameter write */
130 QOP_TEX_T,
131 /** Texture border color parameter or cube map z coordinate write */
132 QOP_TEX_R,
133 /** Texture LOD bias parameter write */
134 QOP_TEX_B,
135
136 /**
137 * Texture-unit 4-byte read with address provided direct in S
138 * cooordinate.
139 *
140 * The first operand is the offset from the start of the UBO, and the
141 * second is the uniform that has the UBO's base pointer.
142 */
143 QOP_TEX_DIRECT,
144
145 /**
146 * Signal of texture read being necessary and then reading r4 into
147 * the destination
148 */
149 QOP_TEX_RESULT,
150 };
151
152 struct queued_qpu_inst {
153 struct list_head link;
154 uint64_t inst;
155 };
156
157 struct qinst {
158 struct list_head link;
159
160 enum qop op;
161 struct qreg dst;
162 struct qreg *src;
163 bool sf;
164 uint8_t cond;
165 };
166
167 enum qstage {
168 /**
169 * Coordinate shader, runs during binning, before the VS, and just
170 * outputs position.
171 */
172 QSTAGE_COORD,
173 QSTAGE_VERT,
174 QSTAGE_FRAG,
175 };
176
177 enum quniform_contents {
178 /**
179 * Indicates that a constant 32-bit value is copied from the program's
180 * uniform contents.
181 */
182 QUNIFORM_CONSTANT,
183 /**
184 * Indicates that the program's uniform contents are used as an index
185 * into the GL uniform storage.
186 */
187 QUNIFORM_UNIFORM,
188
189 /** @{
190 * Scaling factors from clip coordinates to relative to the viewport
191 * center.
192 *
193 * This is used by the coordinate and vertex shaders to produce the
194 * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed
195 * point offsets from the viewport ccenter.
196 */
197 QUNIFORM_VIEWPORT_X_SCALE,
198 QUNIFORM_VIEWPORT_Y_SCALE,
199 /** @} */
200
201 QUNIFORM_VIEWPORT_Z_OFFSET,
202 QUNIFORM_VIEWPORT_Z_SCALE,
203
204 QUNIFORM_USER_CLIP_PLANE,
205
206 /**
207 * A reference to a texture config parameter 0 uniform.
208 *
209 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
210 * defines texture type, miplevels, and such. It will be found as a
211 * parameter to the first QOP_TEX_[STRB] instruction in a sequence.
212 */
213 QUNIFORM_TEXTURE_CONFIG_P0,
214
215 /**
216 * A reference to a texture config parameter 1 uniform.
217 *
218 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
219 * defines texture width, height, filters, and wrap modes. It will be
220 * found as a parameter to the second QOP_TEX_[STRB] instruction in a
221 * sequence.
222 */
223 QUNIFORM_TEXTURE_CONFIG_P1,
224
225 /** A reference to a texture config parameter 2 cubemap stride uniform */
226 QUNIFORM_TEXTURE_CONFIG_P2,
227
228 QUNIFORM_TEXTURE_MSAA_ADDR,
229
230 QUNIFORM_UBO_ADDR,
231
232 QUNIFORM_TEXRECT_SCALE_X,
233 QUNIFORM_TEXRECT_SCALE_Y,
234
235 QUNIFORM_TEXTURE_BORDER_COLOR,
236
237 QUNIFORM_BLEND_CONST_COLOR_X,
238 QUNIFORM_BLEND_CONST_COLOR_Y,
239 QUNIFORM_BLEND_CONST_COLOR_Z,
240 QUNIFORM_BLEND_CONST_COLOR_W,
241 QUNIFORM_BLEND_CONST_COLOR_RGBA,
242 QUNIFORM_BLEND_CONST_COLOR_AAAA,
243
244 QUNIFORM_STENCIL,
245
246 QUNIFORM_ALPHA_REF,
247 QUNIFORM_SAMPLE_MASK,
248 };
249
250 struct vc4_varying_slot {
251 uint8_t slot;
252 uint8_t swizzle;
253 };
254
255 struct vc4_compiler_ubo_range {
256 /**
257 * offset in bytes from the start of the ubo where this range is
258 * uploaded.
259 *
260 * Only set once used is set.
261 */
262 uint32_t dst_offset;
263
264 /**
265 * offset in bytes from the start of the gallium uniforms where the
266 * data comes from.
267 */
268 uint32_t src_offset;
269
270 /** size in bytes of this ubo range */
271 uint32_t size;
272
273 /**
274 * Set if this range is used by the shader for indirect uniforms
275 * access.
276 */
277 bool used;
278 };
279
280 struct vc4_key {
281 struct vc4_uncompiled_shader *shader_state;
282 struct {
283 enum pipe_format format;
284 uint8_t swizzle[4];
285 union {
286 struct {
287 unsigned compare_mode:1;
288 unsigned compare_func:3;
289 unsigned wrap_s:3;
290 unsigned wrap_t:3;
291 };
292 struct {
293 uint16_t msaa_width, msaa_height;
294 };
295 };
296 } tex[VC4_MAX_TEXTURE_SAMPLERS];
297 uint8_t ucp_enables;
298 };
299
300 struct vc4_fs_key {
301 struct vc4_key base;
302 enum pipe_format color_format;
303 bool depth_enabled;
304 bool stencil_enabled;
305 bool stencil_twoside;
306 bool stencil_full_writemasks;
307 bool is_points;
308 bool is_lines;
309 bool alpha_test;
310 bool point_coord_upper_left;
311 bool light_twoside;
312 bool msaa;
313 bool sample_coverage;
314 bool sample_alpha_to_coverage;
315 bool sample_alpha_to_one;
316 uint8_t alpha_test_func;
317 uint8_t logicop_func;
318 uint32_t point_sprite_mask;
319
320 struct pipe_rt_blend_state blend;
321 };
322
323 struct vc4_vs_key {
324 struct vc4_key base;
325
326 /**
327 * This is a proxy for the array of FS input semantics, which is
328 * larger than we would want to put in the key.
329 */
330 uint64_t compiled_fs_id;
331
332 enum pipe_format attr_formats[8];
333 bool is_coord;
334 bool per_vertex_point_size;
335 };
336
337 struct vc4_compile {
338 struct vc4_context *vc4;
339 nir_shader *s;
340 nir_function_impl *impl;
341 struct exec_list *cf_node_list;
342
343 /**
344 * Mapping from nir_register * or nir_ssa_def * to array of struct
345 * qreg for the values.
346 */
347 struct hash_table *def_ht;
348
349 /* For each temp, the instruction generating its value. */
350 struct qinst **defs;
351 uint32_t defs_array_size;
352
353 /**
354 * Inputs to the shader, arranged by TGSI declaration order.
355 *
356 * Not all fragment shader QFILE_VARY reads are present in this array.
357 */
358 struct qreg *inputs;
359 struct qreg *outputs;
360 bool msaa_per_sample_output;
361 struct qreg color_reads[VC4_MAX_SAMPLES];
362 struct qreg sample_colors[VC4_MAX_SAMPLES];
363 uint32_t inputs_array_size;
364 uint32_t outputs_array_size;
365 uint32_t uniforms_array_size;
366
367 struct vc4_compiler_ubo_range *ubo_ranges;
368 uint32_t ubo_ranges_array_size;
369 /** Number of uniform areas declared in ubo_ranges. */
370 uint32_t num_uniform_ranges;
371 /** Number of uniform areas used for indirect addressed loads. */
372 uint32_t num_ubo_ranges;
373 uint32_t next_ubo_dst_offset;
374
375 struct qreg line_x, point_x, point_y;
376 struct qreg discard;
377 struct qreg payload_FRAG_Z;
378 struct qreg payload_FRAG_W;
379
380 uint8_t vattr_sizes[8];
381
382 /* Bitfield for whether a given channel of a sampler needs sRGB
383 * decode.
384 */
385 uint8_t tex_srgb_decode[VC4_MAX_TEXTURE_SAMPLERS];
386
387 /**
388 * Array of the VARYING_SLOT_* of all FS QFILE_VARY reads.
389 *
390 * This includes those that aren't part of the VPM varyings, like
391 * point/line coordinates.
392 */
393 struct vc4_varying_slot *input_slots;
394 uint32_t num_input_slots;
395 uint32_t input_slots_array_size;
396
397 /**
398 * An entry per outputs[] in the VS indicating what the VARYING_SLOT_*
399 * of the output is. Used to emit from the VS in the order that the
400 * FS needs.
401 */
402 struct vc4_varying_slot *output_slots;
403
404 struct pipe_shader_state *shader_state;
405 struct vc4_key *key;
406 struct vc4_fs_key *fs_key;
407 struct vc4_vs_key *vs_key;
408
409 uint32_t *uniform_data;
410 enum quniform_contents *uniform_contents;
411 uint32_t uniform_array_size;
412 uint32_t num_uniforms;
413 uint32_t num_outputs;
414 uint32_t num_texture_samples;
415 uint32_t output_position_index;
416 uint32_t output_color_index;
417 uint32_t output_point_size_index;
418 uint32_t output_sample_mask_index;
419
420 struct qreg undef;
421 enum qstage stage;
422 uint32_t num_temps;
423 struct list_head instructions;
424
425 struct list_head qpu_inst_list;
426 uint64_t *qpu_insts;
427 uint32_t qpu_inst_count;
428 uint32_t qpu_inst_size;
429 uint32_t num_inputs;
430
431 uint32_t program_id;
432 uint32_t variant_id;
433 };
434
435 /* Special nir_load_input intrinsic index for loading the current TLB
436 * destination color.
437 */
438 #define VC4_NIR_TLB_COLOR_READ_INPUT 2000000000
439
440 #define VC4_NIR_MS_MASK_OUTPUT 2000000000
441
442 /* Special offset for nir_load_uniform values to get a QUNIFORM_*
443 * state-dependent value.
444 */
445 #define VC4_NIR_STATE_UNIFORM_OFFSET 1000000000
446
447 struct vc4_compile *qir_compile_init(void);
448 void qir_compile_destroy(struct vc4_compile *c);
449 struct qinst *qir_inst(enum qop op, struct qreg dst,
450 struct qreg src0, struct qreg src1);
451 struct qinst *qir_inst4(enum qop op, struct qreg dst,
452 struct qreg a,
453 struct qreg b,
454 struct qreg c,
455 struct qreg d);
456 void qir_remove_instruction(struct vc4_compile *c, struct qinst *qinst);
457 struct qreg qir_uniform(struct vc4_compile *c,
458 enum quniform_contents contents,
459 uint32_t data);
460 void qir_schedule_instructions(struct vc4_compile *c);
461 void qir_reorder_uniforms(struct vc4_compile *c);
462
463 void qir_emit(struct vc4_compile *c, struct qinst *inst);
464 static inline struct qinst *
465 qir_emit_nodef(struct vc4_compile *c, struct qinst *inst)
466 {
467 list_addtail(&inst->link, &c->instructions);
468 return inst;
469 }
470
471 struct qreg qir_get_temp(struct vc4_compile *c);
472 int qir_get_op_nsrc(enum qop qop);
473 bool qir_reg_equals(struct qreg a, struct qreg b);
474 bool qir_has_side_effects(struct vc4_compile *c, struct qinst *inst);
475 bool qir_has_side_effect_reads(struct vc4_compile *c, struct qinst *inst);
476 bool qir_is_mul(struct qinst *inst);
477 bool qir_is_raw_mov(struct qinst *inst);
478 bool qir_is_tex(struct qinst *inst);
479 bool qir_is_float_input(struct qinst *inst);
480 bool qir_depends_on_flags(struct qinst *inst);
481 bool qir_writes_r4(struct qinst *inst);
482 struct qreg qir_follow_movs(struct vc4_compile *c, struct qreg reg);
483
484 void qir_dump(struct vc4_compile *c);
485 void qir_dump_inst(struct vc4_compile *c, struct qinst *inst);
486 const char *qir_get_stage_name(enum qstage stage);
487
488 void qir_optimize(struct vc4_compile *c);
489 bool qir_opt_algebraic(struct vc4_compile *c);
490 bool qir_opt_constant_folding(struct vc4_compile *c);
491 bool qir_opt_copy_propagation(struct vc4_compile *c);
492 bool qir_opt_dead_code(struct vc4_compile *c);
493 bool qir_opt_small_immediates(struct vc4_compile *c);
494 bool qir_opt_vpm(struct vc4_compile *c);
495 void vc4_nir_lower_blend(nir_shader *s, struct vc4_compile *c);
496 void vc4_nir_lower_io(nir_shader *s, struct vc4_compile *c);
497 nir_ssa_def *vc4_nir_get_state_uniform(struct nir_builder *b,
498 enum quniform_contents contents);
499 nir_ssa_def *vc4_nir_get_swizzled_channel(struct nir_builder *b,
500 nir_ssa_def **srcs, int swiz);
501 void vc4_nir_lower_txf_ms(nir_shader *s, struct vc4_compile *c);
502 void qir_lower_uniforms(struct vc4_compile *c);
503
504 uint32_t qpu_schedule_instructions(struct vc4_compile *c);
505
506 void qir_SF(struct vc4_compile *c, struct qreg src);
507
508 static inline struct qreg
509 qir_uniform_ui(struct vc4_compile *c, uint32_t ui)
510 {
511 return qir_uniform(c, QUNIFORM_CONSTANT, ui);
512 }
513
514 static inline struct qreg
515 qir_uniform_f(struct vc4_compile *c, float f)
516 {
517 return qir_uniform(c, QUNIFORM_CONSTANT, fui(f));
518 }
519
520 #define QIR_ALU0(name) \
521 static inline struct qreg \
522 qir_##name(struct vc4_compile *c) \
523 { \
524 struct qreg t = qir_get_temp(c); \
525 qir_emit(c, qir_inst(QOP_##name, t, c->undef, c->undef)); \
526 return t; \
527 }
528
529 #define QIR_ALU1(name) \
530 static inline struct qreg \
531 qir_##name(struct vc4_compile *c, struct qreg a) \
532 { \
533 struct qreg t = qir_get_temp(c); \
534 qir_emit(c, qir_inst(QOP_##name, t, a, c->undef)); \
535 return t; \
536 } \
537 static inline struct qinst * \
538 qir_##name##_dest(struct vc4_compile *c, struct qreg dest, \
539 struct qreg a) \
540 { \
541 return qir_emit_nodef(c, qir_inst(QOP_##name, dest, a, \
542 c->undef)); \
543 }
544
545 #define QIR_ALU2(name) \
546 static inline struct qreg \
547 qir_##name(struct vc4_compile *c, struct qreg a, struct qreg b) \
548 { \
549 struct qreg t = qir_get_temp(c); \
550 qir_emit(c, qir_inst(QOP_##name, t, a, b)); \
551 return t; \
552 } \
553 static inline void \
554 qir_##name##_dest(struct vc4_compile *c, struct qreg dest, \
555 struct qreg a, struct qreg b) \
556 { \
557 qir_emit_nodef(c, qir_inst(QOP_##name, dest, a, b)); \
558 }
559
560 #define QIR_NODST_1(name) \
561 static inline struct qinst * \
562 qir_##name(struct vc4_compile *c, struct qreg a) \
563 { \
564 struct qinst *inst = qir_inst(QOP_##name, c->undef, \
565 a, c->undef); \
566 qir_emit(c, inst); \
567 return inst; \
568 }
569
570 #define QIR_NODST_2(name) \
571 static inline struct qinst * \
572 qir_##name(struct vc4_compile *c, struct qreg a, struct qreg b) \
573 { \
574 struct qinst *inst = qir_inst(QOP_##name, c->undef, \
575 a, b); \
576 qir_emit(c, inst); \
577 return inst; \
578 }
579
580 #define QIR_PACK(name) \
581 static inline struct qreg \
582 qir_##name(struct vc4_compile *c, struct qreg dest, struct qreg a) \
583 { \
584 qir_emit_nodef(c, qir_inst(QOP_##name, dest, a, c->undef)); \
585 return dest; \
586 }
587
588 #define QIR_PAYLOAD(name) \
589 static inline struct qreg \
590 qir_##name(struct vc4_compile *c) \
591 { \
592 struct qreg *payload = &c->payload_##name; \
593 if (payload->file != QFILE_NULL) \
594 return *payload; \
595 *payload = qir_get_temp(c); \
596 struct qinst *inst = qir_inst(QOP_##name, *payload, \
597 c->undef, c->undef); \
598 list_add(&inst->link, &c->instructions); \
599 c->defs[payload->index] = inst; \
600 return *payload; \
601 }
602
603 QIR_ALU1(MOV)
604 QIR_ALU1(FMOV)
605 QIR_ALU1(MMOV)
606 QIR_ALU2(FADD)
607 QIR_ALU2(FSUB)
608 QIR_ALU2(FMUL)
609 QIR_ALU2(V8MULD)
610 QIR_ALU2(V8MIN)
611 QIR_ALU2(V8MAX)
612 QIR_ALU2(V8ADDS)
613 QIR_ALU2(V8SUBS)
614 QIR_ALU2(MUL24)
615 QIR_ALU2(FMIN)
616 QIR_ALU2(FMAX)
617 QIR_ALU2(FMINABS)
618 QIR_ALU2(FMAXABS)
619 QIR_ALU1(FTOI)
620 QIR_ALU1(ITOF)
621
622 QIR_ALU2(ADD)
623 QIR_ALU2(SUB)
624 QIR_ALU2(SHL)
625 QIR_ALU2(SHR)
626 QIR_ALU2(ASR)
627 QIR_ALU2(MIN)
628 QIR_ALU2(MAX)
629 QIR_ALU2(AND)
630 QIR_ALU2(OR)
631 QIR_ALU2(XOR)
632 QIR_ALU1(NOT)
633
634 QIR_ALU1(RCP)
635 QIR_ALU1(RSQ)
636 QIR_ALU1(EXP2)
637 QIR_ALU1(LOG2)
638 QIR_ALU1(VARY_ADD_C)
639 QIR_NODST_2(TEX_S)
640 QIR_NODST_2(TEX_T)
641 QIR_NODST_2(TEX_R)
642 QIR_NODST_2(TEX_B)
643 QIR_NODST_2(TEX_DIRECT)
644 QIR_PAYLOAD(FRAG_Z)
645 QIR_PAYLOAD(FRAG_W)
646 QIR_ALU0(TEX_RESULT)
647 QIR_ALU0(TLB_COLOR_READ)
648 QIR_NODST_1(MS_MASK)
649
650 static inline struct qreg
651 qir_SEL(struct vc4_compile *c, uint8_t cond, struct qreg src0, struct qreg src1)
652 {
653 struct qreg t = qir_get_temp(c);
654 struct qinst *a = qir_MOV_dest(c, t, src0);
655 struct qinst *b = qir_MOV_dest(c, t, src1);
656 a->cond = cond;
657 b->cond = cond ^ 1;
658 return t;
659 }
660
661 static inline struct qreg
662 qir_UNPACK_8_F(struct vc4_compile *c, struct qreg src, int i)
663 {
664 struct qreg t = qir_FMOV(c, src);
665 c->defs[t.index]->src[0].pack = QPU_UNPACK_8A + i;
666 return t;
667 }
668
669 static inline struct qreg
670 qir_UNPACK_8_I(struct vc4_compile *c, struct qreg src, int i)
671 {
672 struct qreg t = qir_MOV(c, src);
673 c->defs[t.index]->src[0].pack = QPU_UNPACK_8A + i;
674 return t;
675 }
676
677 static inline struct qreg
678 qir_UNPACK_16_F(struct vc4_compile *c, struct qreg src, int i)
679 {
680 struct qreg t = qir_FMOV(c, src);
681 c->defs[t.index]->src[0].pack = QPU_UNPACK_16A + i;
682 return t;
683 }
684
685 static inline struct qreg
686 qir_UNPACK_16_I(struct vc4_compile *c, struct qreg src, int i)
687 {
688 struct qreg t = qir_MOV(c, src);
689 c->defs[t.index]->src[0].pack = QPU_UNPACK_16A + i;
690 return t;
691 }
692
693 static inline void
694 qir_PACK_8_F(struct vc4_compile *c, struct qreg dest, struct qreg val, int chan)
695 {
696 assert(!dest.pack);
697 dest.pack = QPU_PACK_MUL_8A + chan;
698 qir_emit(c, qir_inst(QOP_MMOV, dest, val, c->undef));
699 if (dest.file == QFILE_TEMP)
700 c->defs[dest.index] = NULL;
701 }
702
703 static inline struct qreg
704 qir_PACK_8888_F(struct vc4_compile *c, struct qreg val)
705 {
706 struct qreg dest = qir_MMOV(c, val);
707 c->defs[dest.index]->dst.pack = QPU_PACK_MUL_8888;
708 return dest;
709 }
710
711 static inline struct qreg
712 qir_POW(struct vc4_compile *c, struct qreg x, struct qreg y)
713 {
714 return qir_EXP2(c, qir_FMUL(c,
715 y,
716 qir_LOG2(c, x)));
717 }
718
719 static inline void
720 qir_VPM_WRITE(struct vc4_compile *c, struct qreg val)
721 {
722 qir_MOV_dest(c, qir_reg(QFILE_VPM, 0), val);
723 }
724
725 #endif /* VC4_QIR_H */