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[mesa.git] / src / gallium / drivers / vc4 / vc4_qir.h
1 /*
2 * Copyright © 2014 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef VC4_QIR_H
25 #define VC4_QIR_H
26
27 #include <assert.h>
28 #include <stdio.h>
29 #include <stdlib.h>
30 #include <stdbool.h>
31 #include <stdint.h>
32 #include <string.h>
33
34 #include "util/macros.h"
35 #include "compiler/nir/nir.h"
36 #include "util/list.h"
37 #include "util/u_math.h"
38
39 #include "vc4_screen.h"
40 #include "vc4_qpu_defines.h"
41 #include "vc4_qpu.h"
42 #include "kernel/vc4_packet.h"
43 #include "pipe/p_state.h"
44
45 struct nir_builder;
46
47 enum qfile {
48 QFILE_NULL,
49 QFILE_TEMP,
50 QFILE_VARY,
51 QFILE_UNIF,
52 QFILE_VPM,
53 QFILE_TLB_COLOR_WRITE,
54 QFILE_TLB_COLOR_WRITE_MS,
55 QFILE_TLB_Z_WRITE,
56 QFILE_TLB_STENCIL_SETUP,
57
58 /* Payload registers that aren't in the physical register file, so we
59 * can just use the corresponding qpu_reg at qpu_emit time.
60 */
61 QFILE_FRAG_X,
62 QFILE_FRAG_Y,
63 QFILE_FRAG_REV_FLAG,
64
65 /**
66 * Stores an immediate value in the index field that will be used
67 * directly by qpu_load_imm().
68 */
69 QFILE_LOAD_IMM,
70
71 /**
72 * Stores an immediate value in the index field that can be turned
73 * into a small immediate field by qpu_encode_small_immediate().
74 */
75 QFILE_SMALL_IMM,
76 };
77
78 struct qreg {
79 enum qfile file;
80 uint32_t index;
81 int pack;
82 };
83
84 static inline struct qreg qir_reg(enum qfile file, uint32_t index)
85 {
86 return (struct qreg){file, index};
87 }
88
89 enum qop {
90 QOP_UNDEF,
91 QOP_MOV,
92 QOP_FMOV,
93 QOP_MMOV,
94 QOP_FADD,
95 QOP_FSUB,
96 QOP_FMUL,
97 QOP_V8MULD,
98 QOP_V8MIN,
99 QOP_V8MAX,
100 QOP_V8ADDS,
101 QOP_V8SUBS,
102 QOP_MUL24,
103 QOP_FMIN,
104 QOP_FMAX,
105 QOP_FMINABS,
106 QOP_FMAXABS,
107 QOP_ADD,
108 QOP_SUB,
109 QOP_SHL,
110 QOP_SHR,
111 QOP_ASR,
112 QOP_MIN,
113 QOP_MAX,
114 QOP_AND,
115 QOP_OR,
116 QOP_XOR,
117 QOP_NOT,
118
119 QOP_FTOI,
120 QOP_ITOF,
121 QOP_RCP,
122 QOP_RSQ,
123 QOP_EXP2,
124 QOP_LOG2,
125 QOP_VW_SETUP,
126 QOP_VR_SETUP,
127 QOP_TLB_COLOR_READ,
128 QOP_MS_MASK,
129 QOP_VARY_ADD_C,
130
131 QOP_FRAG_Z,
132 QOP_FRAG_W,
133
134 /** Texture x coordinate parameter write */
135 QOP_TEX_S,
136 /** Texture y coordinate parameter write */
137 QOP_TEX_T,
138 /** Texture border color parameter or cube map z coordinate write */
139 QOP_TEX_R,
140 /** Texture LOD bias parameter write */
141 QOP_TEX_B,
142
143 /**
144 * Texture-unit 4-byte read with address provided direct in S
145 * cooordinate.
146 *
147 * The first operand is the offset from the start of the UBO, and the
148 * second is the uniform that has the UBO's base pointer.
149 */
150 QOP_TEX_DIRECT,
151
152 /**
153 * Signal of texture read being necessary and then reading r4 into
154 * the destination
155 */
156 QOP_TEX_RESULT,
157
158 QOP_LOAD_IMM,
159
160 /* Jumps to block->successor[0] if the qinst->cond (as a
161 * QPU_COND_BRANCH_*) passes, or block->successor[1] if not. Note
162 * that block->successor[1] may be unset if the condition is ALWAYS.
163 */
164 QOP_BRANCH,
165
166 /* Emits an ADD from src[0] to src[1], where src[0] must be a
167 * QOP_LOAD_IMM result and src[1] is a QUNIFORM_UNIFORMS_ADDRESS,
168 * required by the kernel as part of its branch validation.
169 */
170 QOP_UNIFORMS_RESET,
171 };
172
173 struct queued_qpu_inst {
174 struct list_head link;
175 uint64_t inst;
176 };
177
178 struct qinst {
179 struct list_head link;
180
181 enum qop op;
182 struct qreg dst;
183 struct qreg *src;
184 bool sf;
185 uint8_t cond;
186 };
187
188 enum qstage {
189 /**
190 * Coordinate shader, runs during binning, before the VS, and just
191 * outputs position.
192 */
193 QSTAGE_COORD,
194 QSTAGE_VERT,
195 QSTAGE_FRAG,
196 };
197
198 enum quniform_contents {
199 /**
200 * Indicates that a constant 32-bit value is copied from the program's
201 * uniform contents.
202 */
203 QUNIFORM_CONSTANT,
204 /**
205 * Indicates that the program's uniform contents are used as an index
206 * into the GL uniform storage.
207 */
208 QUNIFORM_UNIFORM,
209
210 /** @{
211 * Scaling factors from clip coordinates to relative to the viewport
212 * center.
213 *
214 * This is used by the coordinate and vertex shaders to produce the
215 * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed
216 * point offsets from the viewport ccenter.
217 */
218 QUNIFORM_VIEWPORT_X_SCALE,
219 QUNIFORM_VIEWPORT_Y_SCALE,
220 /** @} */
221
222 QUNIFORM_VIEWPORT_Z_OFFSET,
223 QUNIFORM_VIEWPORT_Z_SCALE,
224
225 QUNIFORM_USER_CLIP_PLANE,
226
227 /**
228 * A reference to a texture config parameter 0 uniform.
229 *
230 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
231 * defines texture type, miplevels, and such. It will be found as a
232 * parameter to the first QOP_TEX_[STRB] instruction in a sequence.
233 */
234 QUNIFORM_TEXTURE_CONFIG_P0,
235
236 /**
237 * A reference to a texture config parameter 1 uniform.
238 *
239 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
240 * defines texture width, height, filters, and wrap modes. It will be
241 * found as a parameter to the second QOP_TEX_[STRB] instruction in a
242 * sequence.
243 */
244 QUNIFORM_TEXTURE_CONFIG_P1,
245
246 /** A reference to a texture config parameter 2 cubemap stride uniform */
247 QUNIFORM_TEXTURE_CONFIG_P2,
248
249 QUNIFORM_TEXTURE_MSAA_ADDR,
250
251 QUNIFORM_UBO_ADDR,
252
253 QUNIFORM_TEXRECT_SCALE_X,
254 QUNIFORM_TEXRECT_SCALE_Y,
255
256 QUNIFORM_TEXTURE_BORDER_COLOR,
257
258 QUNIFORM_BLEND_CONST_COLOR_X,
259 QUNIFORM_BLEND_CONST_COLOR_Y,
260 QUNIFORM_BLEND_CONST_COLOR_Z,
261 QUNIFORM_BLEND_CONST_COLOR_W,
262 QUNIFORM_BLEND_CONST_COLOR_RGBA,
263 QUNIFORM_BLEND_CONST_COLOR_AAAA,
264
265 QUNIFORM_STENCIL,
266
267 QUNIFORM_ALPHA_REF,
268 QUNIFORM_SAMPLE_MASK,
269
270 /* Placeholder uniform that will be updated by the kernel when used by
271 * an instruction writing to QPU_W_UNIFORMS_ADDRESS.
272 */
273 QUNIFORM_UNIFORMS_ADDRESS,
274 };
275
276 struct vc4_varying_slot {
277 uint8_t slot;
278 uint8_t swizzle;
279 };
280
281 struct vc4_compiler_ubo_range {
282 /**
283 * offset in bytes from the start of the ubo where this range is
284 * uploaded.
285 *
286 * Only set once used is set.
287 */
288 uint32_t dst_offset;
289
290 /**
291 * offset in bytes from the start of the gallium uniforms where the
292 * data comes from.
293 */
294 uint32_t src_offset;
295
296 /** size in bytes of this ubo range */
297 uint32_t size;
298
299 /**
300 * Set if this range is used by the shader for indirect uniforms
301 * access.
302 */
303 bool used;
304 };
305
306 struct vc4_key {
307 struct vc4_uncompiled_shader *shader_state;
308 struct {
309 enum pipe_format format;
310 uint8_t swizzle[4];
311 union {
312 struct {
313 unsigned compare_mode:1;
314 unsigned compare_func:3;
315 unsigned wrap_s:3;
316 unsigned wrap_t:3;
317 };
318 struct {
319 uint16_t msaa_width, msaa_height;
320 };
321 };
322 } tex[VC4_MAX_TEXTURE_SAMPLERS];
323 uint8_t ucp_enables;
324 };
325
326 struct vc4_fs_key {
327 struct vc4_key base;
328 enum pipe_format color_format;
329 bool depth_enabled;
330 bool stencil_enabled;
331 bool stencil_twoside;
332 bool stencil_full_writemasks;
333 bool is_points;
334 bool is_lines;
335 bool alpha_test;
336 bool point_coord_upper_left;
337 bool light_twoside;
338 bool msaa;
339 bool sample_coverage;
340 bool sample_alpha_to_coverage;
341 bool sample_alpha_to_one;
342 uint8_t alpha_test_func;
343 uint8_t logicop_func;
344 uint32_t point_sprite_mask;
345
346 struct pipe_rt_blend_state blend;
347 };
348
349 struct vc4_vs_key {
350 struct vc4_key base;
351
352 /**
353 * This is a proxy for the array of FS input semantics, which is
354 * larger than we would want to put in the key.
355 */
356 uint64_t compiled_fs_id;
357
358 enum pipe_format attr_formats[8];
359 bool is_coord;
360 bool per_vertex_point_size;
361 bool clamp_color;
362 };
363
364 /** A basic block of QIR intructions. */
365 struct qblock {
366 struct list_head link;
367
368 struct list_head instructions;
369 struct list_head qpu_inst_list;
370
371 struct set *predecessors;
372 struct qblock *successors[2];
373
374 int index;
375
376 /* Instruction IPs for the first and last instruction of the block.
377 * Set by vc4_qpu_schedule.c.
378 */
379 uint32_t start_qpu_ip;
380 uint32_t end_qpu_ip;
381
382 /* Instruction IP for the branch instruction of the block. Set by
383 * vc4_qpu_schedule.c.
384 */
385 uint32_t branch_qpu_ip;
386
387 /** @{ used by vc4_qir_live_variables.c */
388 BITSET_WORD *def;
389 BITSET_WORD *use;
390 BITSET_WORD *live_in;
391 BITSET_WORD *live_out;
392 int start_ip, end_ip;
393 /** @} */
394 };
395
396 struct vc4_compile {
397 struct vc4_context *vc4;
398 nir_shader *s;
399 nir_function_impl *impl;
400 struct exec_list *cf_node_list;
401
402 /**
403 * Mapping from nir_register * or nir_ssa_def * to array of struct
404 * qreg for the values.
405 */
406 struct hash_table *def_ht;
407
408 /* For each temp, the instruction generating its value. */
409 struct qinst **defs;
410 uint32_t defs_array_size;
411
412 /**
413 * Inputs to the shader, arranged by TGSI declaration order.
414 *
415 * Not all fragment shader QFILE_VARY reads are present in this array.
416 */
417 struct qreg *inputs;
418 struct qreg *outputs;
419 bool msaa_per_sample_output;
420 struct qreg color_reads[VC4_MAX_SAMPLES];
421 struct qreg sample_colors[VC4_MAX_SAMPLES];
422 uint32_t inputs_array_size;
423 uint32_t outputs_array_size;
424 uint32_t uniforms_array_size;
425
426 struct vc4_compiler_ubo_range *ubo_ranges;
427 uint32_t ubo_ranges_array_size;
428 /** Number of uniform areas declared in ubo_ranges. */
429 uint32_t num_uniform_ranges;
430 /** Number of uniform areas used for indirect addressed loads. */
431 uint32_t num_ubo_ranges;
432 uint32_t next_ubo_dst_offset;
433
434 /* State for whether we're executing on each channel currently. 0 if
435 * yes, otherwise a block number + 1 that the channel jumped to.
436 */
437 struct qreg execute;
438
439 struct qreg line_x, point_x, point_y;
440 struct qreg discard;
441 struct qreg payload_FRAG_Z;
442 struct qreg payload_FRAG_W;
443
444 uint8_t vattr_sizes[8];
445
446 /**
447 * Array of the VARYING_SLOT_* of all FS QFILE_VARY reads.
448 *
449 * This includes those that aren't part of the VPM varyings, like
450 * point/line coordinates.
451 */
452 struct vc4_varying_slot *input_slots;
453 uint32_t num_input_slots;
454 uint32_t input_slots_array_size;
455
456 /**
457 * An entry per outputs[] in the VS indicating what the VARYING_SLOT_*
458 * of the output is. Used to emit from the VS in the order that the
459 * FS needs.
460 */
461 struct vc4_varying_slot *output_slots;
462
463 struct pipe_shader_state *shader_state;
464 struct vc4_key *key;
465 struct vc4_fs_key *fs_key;
466 struct vc4_vs_key *vs_key;
467
468 /* Live ranges of temps. */
469 int *temp_start, *temp_end;
470
471 uint32_t *uniform_data;
472 enum quniform_contents *uniform_contents;
473 uint32_t uniform_array_size;
474 uint32_t num_uniforms;
475 uint32_t num_outputs;
476 uint32_t num_texture_samples;
477 uint32_t output_position_index;
478 uint32_t output_color_index;
479 uint32_t output_point_size_index;
480 uint32_t output_sample_mask_index;
481
482 struct qreg undef;
483 enum qstage stage;
484 uint32_t num_temps;
485
486 struct list_head blocks;
487 int next_block_index;
488 struct qblock *cur_block;
489 struct qblock *loop_cont_block;
490 struct qblock *loop_break_block;
491
492 struct list_head qpu_inst_list;
493
494 uint64_t *qpu_insts;
495 uint32_t qpu_inst_count;
496 uint32_t qpu_inst_size;
497 uint32_t num_inputs;
498
499 uint32_t program_id;
500 uint32_t variant_id;
501 };
502
503 /* Special nir_load_input intrinsic index for loading the current TLB
504 * destination color.
505 */
506 #define VC4_NIR_TLB_COLOR_READ_INPUT 2000000000
507
508 #define VC4_NIR_MS_MASK_OUTPUT 2000000000
509
510 /* Special offset for nir_load_uniform values to get a QUNIFORM_*
511 * state-dependent value.
512 */
513 #define VC4_NIR_STATE_UNIFORM_OFFSET 1000000000
514
515 struct vc4_compile *qir_compile_init(void);
516 void qir_compile_destroy(struct vc4_compile *c);
517 struct qblock *qir_new_block(struct vc4_compile *c);
518 void qir_set_emit_block(struct vc4_compile *c, struct qblock *block);
519 void qir_link_blocks(struct qblock *predecessor, struct qblock *successor);
520 struct qblock *qir_entry_block(struct vc4_compile *c);
521 struct qblock *qir_exit_block(struct vc4_compile *c);
522 struct qinst *qir_inst(enum qop op, struct qreg dst,
523 struct qreg src0, struct qreg src1);
524 struct qinst *qir_inst4(enum qop op, struct qreg dst,
525 struct qreg a,
526 struct qreg b,
527 struct qreg c,
528 struct qreg d);
529 void qir_remove_instruction(struct vc4_compile *c, struct qinst *qinst);
530 struct qreg qir_uniform(struct vc4_compile *c,
531 enum quniform_contents contents,
532 uint32_t data);
533 void qir_schedule_instructions(struct vc4_compile *c);
534 void qir_reorder_uniforms(struct vc4_compile *c);
535 void qir_emit_uniform_stream_resets(struct vc4_compile *c);
536
537 struct qreg qir_emit_def(struct vc4_compile *c, struct qinst *inst);
538 struct qinst *qir_emit_nondef(struct vc4_compile *c, struct qinst *inst);
539
540 struct qreg qir_get_temp(struct vc4_compile *c);
541 void qir_calculate_live_intervals(struct vc4_compile *c);
542 int qir_get_op_nsrc(enum qop qop);
543 bool qir_reg_equals(struct qreg a, struct qreg b);
544 bool qir_has_side_effects(struct vc4_compile *c, struct qinst *inst);
545 bool qir_has_side_effect_reads(struct vc4_compile *c, struct qinst *inst);
546 bool qir_is_mul(struct qinst *inst);
547 bool qir_is_raw_mov(struct qinst *inst);
548 bool qir_is_tex(struct qinst *inst);
549 bool qir_is_float_input(struct qinst *inst);
550 bool qir_depends_on_flags(struct qinst *inst);
551 bool qir_writes_r4(struct qinst *inst);
552 struct qreg qir_follow_movs(struct vc4_compile *c, struct qreg reg);
553 uint8_t qir_channels_written(struct qinst *inst);
554
555 void qir_dump(struct vc4_compile *c);
556 void qir_dump_inst(struct vc4_compile *c, struct qinst *inst);
557 const char *qir_get_stage_name(enum qstage stage);
558
559 void qir_validate(struct vc4_compile *c);
560
561 void qir_optimize(struct vc4_compile *c);
562 bool qir_opt_algebraic(struct vc4_compile *c);
563 bool qir_opt_constant_folding(struct vc4_compile *c);
564 bool qir_opt_copy_propagation(struct vc4_compile *c);
565 bool qir_opt_dead_code(struct vc4_compile *c);
566 bool qir_opt_peephole_sf(struct vc4_compile *c);
567 bool qir_opt_small_immediates(struct vc4_compile *c);
568 bool qir_opt_vpm(struct vc4_compile *c);
569 void vc4_nir_lower_blend(nir_shader *s, struct vc4_compile *c);
570 void vc4_nir_lower_io(nir_shader *s, struct vc4_compile *c);
571 nir_ssa_def *vc4_nir_get_state_uniform(struct nir_builder *b,
572 enum quniform_contents contents);
573 nir_ssa_def *vc4_nir_get_swizzled_channel(struct nir_builder *b,
574 nir_ssa_def **srcs, int swiz);
575 void vc4_nir_lower_txf_ms(nir_shader *s, struct vc4_compile *c);
576 void qir_lower_uniforms(struct vc4_compile *c);
577
578 uint32_t qpu_schedule_instructions(struct vc4_compile *c);
579
580 void qir_SF(struct vc4_compile *c, struct qreg src);
581
582 static inline struct qreg
583 qir_uniform_ui(struct vc4_compile *c, uint32_t ui)
584 {
585 return qir_uniform(c, QUNIFORM_CONSTANT, ui);
586 }
587
588 static inline struct qreg
589 qir_uniform_f(struct vc4_compile *c, float f)
590 {
591 return qir_uniform(c, QUNIFORM_CONSTANT, fui(f));
592 }
593
594 #define QIR_ALU0(name) \
595 static inline struct qreg \
596 qir_##name(struct vc4_compile *c) \
597 { \
598 return qir_emit_def(c, qir_inst(QOP_##name, c->undef, \
599 c->undef, c->undef)); \
600 } \
601 static inline struct qinst * \
602 qir_##name##_dest(struct vc4_compile *c, struct qreg dest) \
603 { \
604 return qir_emit_nondef(c, qir_inst(QOP_##name, dest, \
605 c->undef, c->undef)); \
606 }
607
608 #define QIR_ALU1(name) \
609 static inline struct qreg \
610 qir_##name(struct vc4_compile *c, struct qreg a) \
611 { \
612 return qir_emit_def(c, qir_inst(QOP_##name, c->undef, \
613 a, c->undef)); \
614 } \
615 static inline struct qinst * \
616 qir_##name##_dest(struct vc4_compile *c, struct qreg dest, \
617 struct qreg a) \
618 { \
619 return qir_emit_nondef(c, qir_inst(QOP_##name, dest, a, \
620 c->undef)); \
621 }
622
623 #define QIR_ALU2(name) \
624 static inline struct qreg \
625 qir_##name(struct vc4_compile *c, struct qreg a, struct qreg b) \
626 { \
627 return qir_emit_def(c, qir_inst(QOP_##name, c->undef, a, b)); \
628 } \
629 static inline struct qinst * \
630 qir_##name##_dest(struct vc4_compile *c, struct qreg dest, \
631 struct qreg a, struct qreg b) \
632 { \
633 return qir_emit_nondef(c, qir_inst(QOP_##name, dest, a, b)); \
634 }
635
636 #define QIR_NODST_1(name) \
637 static inline struct qinst * \
638 qir_##name(struct vc4_compile *c, struct qreg a) \
639 { \
640 return qir_emit_nondef(c, qir_inst(QOP_##name, c->undef, \
641 a, c->undef)); \
642 }
643
644 #define QIR_NODST_2(name) \
645 static inline struct qinst * \
646 qir_##name(struct vc4_compile *c, struct qreg a, struct qreg b) \
647 { \
648 return qir_emit_nondef(c, qir_inst(QOP_##name, c->undef, \
649 a, b)); \
650 }
651
652 #define QIR_PAYLOAD(name) \
653 static inline struct qreg \
654 qir_##name(struct vc4_compile *c) \
655 { \
656 struct qreg *payload = &c->payload_##name; \
657 if (payload->file != QFILE_NULL) \
658 return *payload; \
659 *payload = qir_get_temp(c); \
660 struct qinst *inst = qir_inst(QOP_##name, *payload, \
661 c->undef, c->undef); \
662 struct qblock *entry = qir_entry_block(c); \
663 list_add(&inst->link, &entry->instructions); \
664 c->defs[payload->index] = inst; \
665 return *payload; \
666 }
667
668 QIR_ALU1(MOV)
669 QIR_ALU1(FMOV)
670 QIR_ALU1(MMOV)
671 QIR_ALU2(FADD)
672 QIR_ALU2(FSUB)
673 QIR_ALU2(FMUL)
674 QIR_ALU2(V8MULD)
675 QIR_ALU2(V8MIN)
676 QIR_ALU2(V8MAX)
677 QIR_ALU2(V8ADDS)
678 QIR_ALU2(V8SUBS)
679 QIR_ALU2(MUL24)
680 QIR_ALU2(FMIN)
681 QIR_ALU2(FMAX)
682 QIR_ALU2(FMINABS)
683 QIR_ALU2(FMAXABS)
684 QIR_ALU1(FTOI)
685 QIR_ALU1(ITOF)
686
687 QIR_ALU2(ADD)
688 QIR_ALU2(SUB)
689 QIR_ALU2(SHL)
690 QIR_ALU2(SHR)
691 QIR_ALU2(ASR)
692 QIR_ALU2(MIN)
693 QIR_ALU2(MAX)
694 QIR_ALU2(AND)
695 QIR_ALU2(OR)
696 QIR_ALU2(XOR)
697 QIR_ALU1(NOT)
698
699 QIR_ALU1(RCP)
700 QIR_ALU1(RSQ)
701 QIR_ALU1(EXP2)
702 QIR_ALU1(LOG2)
703 QIR_ALU1(VARY_ADD_C)
704 QIR_NODST_2(TEX_S)
705 QIR_NODST_2(TEX_T)
706 QIR_NODST_2(TEX_R)
707 QIR_NODST_2(TEX_B)
708 QIR_NODST_2(TEX_DIRECT)
709 QIR_PAYLOAD(FRAG_Z)
710 QIR_PAYLOAD(FRAG_W)
711 QIR_ALU0(TEX_RESULT)
712 QIR_ALU0(TLB_COLOR_READ)
713 QIR_NODST_1(MS_MASK)
714
715 static inline struct qreg
716 qir_SEL(struct vc4_compile *c, uint8_t cond, struct qreg src0, struct qreg src1)
717 {
718 struct qreg t = qir_get_temp(c);
719 struct qinst *a = qir_MOV_dest(c, t, src0);
720 struct qinst *b = qir_MOV_dest(c, t, src1);
721 a->cond = cond;
722 b->cond = qpu_cond_complement(cond);
723 return t;
724 }
725
726 static inline struct qreg
727 qir_UNPACK_8_F(struct vc4_compile *c, struct qreg src, int i)
728 {
729 struct qreg t = qir_FMOV(c, src);
730 c->defs[t.index]->src[0].pack = QPU_UNPACK_8A + i;
731 return t;
732 }
733
734 static inline struct qreg
735 qir_UNPACK_8_I(struct vc4_compile *c, struct qreg src, int i)
736 {
737 struct qreg t = qir_MOV(c, src);
738 c->defs[t.index]->src[0].pack = QPU_UNPACK_8A + i;
739 return t;
740 }
741
742 static inline struct qreg
743 qir_UNPACK_16_F(struct vc4_compile *c, struct qreg src, int i)
744 {
745 struct qreg t = qir_FMOV(c, src);
746 c->defs[t.index]->src[0].pack = QPU_UNPACK_16A + i;
747 return t;
748 }
749
750 static inline struct qreg
751 qir_UNPACK_16_I(struct vc4_compile *c, struct qreg src, int i)
752 {
753 struct qreg t = qir_MOV(c, src);
754 c->defs[t.index]->src[0].pack = QPU_UNPACK_16A + i;
755 return t;
756 }
757
758 static inline void
759 qir_PACK_8_F(struct vc4_compile *c, struct qreg dest, struct qreg val, int chan)
760 {
761 assert(!dest.pack);
762 dest.pack = QPU_PACK_MUL_8A + chan;
763 qir_emit_nondef(c, qir_inst(QOP_MMOV, dest, val, c->undef));
764 }
765
766 static inline struct qreg
767 qir_PACK_8888_F(struct vc4_compile *c, struct qreg val)
768 {
769 struct qreg dest = qir_MMOV(c, val);
770 c->defs[dest.index]->dst.pack = QPU_PACK_MUL_8888;
771 return dest;
772 }
773
774 static inline struct qreg
775 qir_POW(struct vc4_compile *c, struct qreg x, struct qreg y)
776 {
777 return qir_EXP2(c, qir_FMUL(c,
778 y,
779 qir_LOG2(c, x)));
780 }
781
782 static inline void
783 qir_VPM_WRITE(struct vc4_compile *c, struct qreg val)
784 {
785 qir_MOV_dest(c, qir_reg(QFILE_VPM, 0), val);
786 }
787
788 static inline struct qreg
789 qir_LOAD_IMM(struct vc4_compile *c, uint32_t val)
790 {
791 return qir_emit_def(c, qir_inst(QOP_LOAD_IMM, c->undef,
792 qir_reg(QFILE_LOAD_IMM, val), c->undef));
793 }
794
795 static inline void
796 qir_MOV_cond(struct vc4_compile *c, uint8_t cond,
797 struct qreg dest, struct qreg src)
798 {
799 qir_MOV_dest(c, dest, src)->cond = cond;
800 }
801
802 static inline struct qinst *
803 qir_BRANCH(struct vc4_compile *c, uint8_t cond)
804 {
805 struct qinst *inst = qir_inst(QOP_BRANCH, c->undef, c->undef, c->undef);
806 inst->cond = cond;
807 qir_emit_nondef(c, inst);
808 return inst;
809 }
810
811 #define qir_for_each_block(block, c) \
812 list_for_each_entry(struct qblock, block, &c->blocks, link)
813
814 #define qir_for_each_block_rev(block, c) \
815 list_for_each_entry_rev(struct qblock, block, &c->blocks, link)
816
817 /* Loop over the non-NULL members of the successors array. */
818 #define qir_for_each_successor(succ, block) \
819 for (struct qblock *succ = block->successors[0]; \
820 succ != NULL; \
821 succ = (succ == block->successors[1] ? NULL : \
822 block->successors[1]))
823
824 #define qir_for_each_inst(inst, block) \
825 list_for_each_entry(struct qinst, inst, &block->instructions, link)
826
827 #define qir_for_each_inst_rev(inst, block) \
828 list_for_each_entry_rev(struct qinst, inst, &block->instructions, link)
829
830 #define qir_for_each_inst_safe(inst, block) \
831 list_for_each_entry_safe(struct qinst, inst, &block->instructions, link)
832
833 #define qir_for_each_inst_inorder(inst, c) \
834 qir_for_each_block(_block, c) \
835 qir_for_each_inst(inst, _block)
836
837 #endif /* VC4_QIR_H */