2 * Copyright © 2014 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
34 #include "util/macros.h"
35 #include "compiler/nir/nir.h"
36 #include "util/list.h"
37 #include "util/u_math.h"
39 #include "vc4_screen.h"
40 #include "vc4_qpu_defines.h"
42 #include "kernel/vc4_packet.h"
43 #include "pipe/p_state.h"
53 QFILE_TLB_COLOR_WRITE
,
54 QFILE_TLB_COLOR_WRITE_MS
,
56 QFILE_TLB_STENCIL_SETUP
,
58 /* Payload registers that aren't in the physical register file, so we
59 * can just use the corresponding qpu_reg at qpu_emit time.
67 * Stores an immediate value in the index field that will be used
68 * directly by qpu_load_imm().
73 * Stores an immediate value in the index field that can be turned
74 * into a small immediate field by qpu_encode_small_immediate().
85 static inline struct qreg
qir_reg(enum qfile file
, uint32_t index
)
87 return (struct qreg
){file
, index
};
135 /** Texture x coordinate parameter write */
137 /** Texture y coordinate parameter write */
139 /** Texture border color parameter or cube map z coordinate write */
141 /** Texture LOD bias parameter write */
145 * Texture-unit 4-byte read with address provided direct in S
148 * The first operand is the offset from the start of the UBO, and the
149 * second is the uniform that has the UBO's base pointer.
154 * Signal of texture read being necessary and then reading r4 into
160 * Insert the signal for switching threads in a threaded fragment
161 * shader. No value can be live in an accumulator across a thrsw.
163 * At the QPU level, this will have several delay slots before the
164 * switch happens. Those slots are the responsibility of the
169 /* 32-bit immediate loaded to each SIMD channel */
172 /* 32-bit immediate divided into 16 2-bit unsigned int values and
173 * loaded to each corresponding SIMD channel.
176 /* 32-bit immediate divided into 16 2-bit signed int values and
177 * loaded to each corresponding SIMD channel.
183 /* Jumps to block->successor[0] if the qinst->cond (as a
184 * QPU_COND_BRANCH_*) passes, or block->successor[1] if not. Note
185 * that block->successor[1] may be unset if the condition is ALWAYS.
189 /* Emits an ADD from src[0] to src[1], where src[0] must be a
190 * QOP_LOAD_IMM result and src[1] is a QUNIFORM_UNIFORMS_ADDRESS,
191 * required by the kernel as part of its branch validation.
196 struct queued_qpu_inst
{
197 struct list_head link
;
202 struct list_head link
;
208 bool cond_is_exec_mask
;
214 * Coordinate shader, runs during binning, before the VS, and just
222 enum quniform_contents
{
224 * Indicates that a constant 32-bit value is copied from the program's
229 * Indicates that the program's uniform contents are used as an index
230 * into the GL uniform storage.
235 * Scaling factors from clip coordinates to relative to the viewport
238 * This is used by the coordinate and vertex shaders to produce the
239 * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed
240 * point offsets from the viewport ccenter.
242 QUNIFORM_VIEWPORT_X_SCALE
,
243 QUNIFORM_VIEWPORT_Y_SCALE
,
246 QUNIFORM_VIEWPORT_Z_OFFSET
,
247 QUNIFORM_VIEWPORT_Z_SCALE
,
249 QUNIFORM_USER_CLIP_PLANE
,
252 * A reference to a texture config parameter 0 uniform.
254 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
255 * defines texture type, miplevels, and such. It will be found as a
256 * parameter to the first QOP_TEX_[STRB] instruction in a sequence.
258 QUNIFORM_TEXTURE_CONFIG_P0
,
261 * A reference to a texture config parameter 1 uniform.
263 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
264 * defines texture width, height, filters, and wrap modes. It will be
265 * found as a parameter to the second QOP_TEX_[STRB] instruction in a
268 QUNIFORM_TEXTURE_CONFIG_P1
,
270 /** A reference to a texture config parameter 2 cubemap stride uniform */
271 QUNIFORM_TEXTURE_CONFIG_P2
,
273 QUNIFORM_TEXTURE_FIRST_LEVEL
,
275 QUNIFORM_TEXTURE_MSAA_ADDR
,
279 QUNIFORM_TEXRECT_SCALE_X
,
280 QUNIFORM_TEXRECT_SCALE_Y
,
282 QUNIFORM_TEXTURE_BORDER_COLOR
,
284 QUNIFORM_BLEND_CONST_COLOR_X
,
285 QUNIFORM_BLEND_CONST_COLOR_Y
,
286 QUNIFORM_BLEND_CONST_COLOR_Z
,
287 QUNIFORM_BLEND_CONST_COLOR_W
,
288 QUNIFORM_BLEND_CONST_COLOR_RGBA
,
289 QUNIFORM_BLEND_CONST_COLOR_AAAA
,
294 QUNIFORM_SAMPLE_MASK
,
296 /* Placeholder uniform that will be updated by the kernel when used by
297 * an instruction writing to QPU_W_UNIFORMS_ADDRESS.
299 QUNIFORM_UNIFORMS_ADDRESS
,
302 struct vc4_varying_slot
{
307 struct vc4_compiler_ubo_range
{
309 * offset in bytes from the start of the ubo where this range is
312 * Only set once used is set.
317 * offset in bytes from the start of the gallium uniforms where the
322 /** size in bytes of this ubo range */
326 * Set if this range is used by the shader for indirect uniforms
333 struct vc4_uncompiled_shader
*shader_state
;
335 enum pipe_format format
;
339 unsigned compare_mode
:1;
340 unsigned compare_func
:3;
343 bool force_first_level
:1;
346 uint16_t msaa_width
, msaa_height
;
349 } tex
[VC4_MAX_TEXTURE_SAMPLERS
];
355 enum pipe_format color_format
;
357 bool stencil_enabled
;
358 bool stencil_twoside
;
359 bool stencil_full_writemasks
;
363 bool point_coord_upper_left
;
366 bool sample_coverage
;
367 bool sample_alpha_to_coverage
;
368 bool sample_alpha_to_one
;
369 uint8_t alpha_test_func
;
370 uint8_t logicop_func
;
371 uint32_t point_sprite_mask
;
373 struct pipe_rt_blend_state blend
;
379 const struct vc4_fs_inputs
*fs_inputs
;
380 enum pipe_format attr_formats
[8];
382 bool per_vertex_point_size
;
386 /** A basic block of QIR intructions. */
388 struct list_head link
;
390 struct list_head instructions
;
391 struct list_head qpu_inst_list
;
393 struct set
*predecessors
;
394 struct qblock
*successors
[2];
398 /* Instruction IPs for the first and last instruction of the block.
399 * Set by vc4_qpu_schedule.c.
401 uint32_t start_qpu_ip
;
404 /* Instruction IP for the branch instruction of the block. Set by
405 * vc4_qpu_schedule.c.
407 uint32_t branch_qpu_ip
;
409 /** @{ used by vc4_qir_live_variables.c */
412 BITSET_WORD
*live_in
;
413 BITSET_WORD
*live_out
;
414 int start_ip
, end_ip
;
419 struct vc4_context
*vc4
;
421 nir_function_impl
*impl
;
422 struct exec_list
*cf_node_list
;
425 * Mapping from nir_register * or nir_ssa_def * to array of struct
426 * qreg for the values.
428 struct hash_table
*def_ht
;
430 /* For each temp, the instruction generating its value. */
432 uint32_t defs_array_size
;
435 * Inputs to the shader, arranged by TGSI declaration order.
437 * Not all fragment shader QFILE_VARY reads are present in this array.
440 struct qreg
*outputs
;
441 bool msaa_per_sample_output
;
442 struct qreg color_reads
[VC4_MAX_SAMPLES
];
443 struct qreg sample_colors
[VC4_MAX_SAMPLES
];
444 uint32_t inputs_array_size
;
445 uint32_t outputs_array_size
;
446 uint32_t uniforms_array_size
;
448 struct vc4_compiler_ubo_range
*ubo_ranges
;
449 uint32_t ubo_ranges_array_size
;
450 /** Number of uniform areas declared in ubo_ranges. */
451 uint32_t num_uniform_ranges
;
452 /** Number of uniform areas used for indirect addressed loads. */
453 uint32_t num_ubo_ranges
;
454 uint32_t next_ubo_dst_offset
;
456 /* State for whether we're executing on each channel currently. 0 if
457 * yes, otherwise a block number + 1 that the channel jumped to.
461 struct qreg line_x
, point_x
, point_y
;
462 /** boolean (~0 -> true) if the fragment has been discarded. */
464 struct qreg payload_FRAG_Z
;
465 struct qreg payload_FRAG_W
;
467 uint8_t vattr_sizes
[8];
470 * Array of the VARYING_SLOT_* of all FS QFILE_VARY reads.
472 * This includes those that aren't part of the VPM varyings, like
473 * point/line coordinates.
475 struct vc4_varying_slot
*input_slots
;
476 uint32_t num_input_slots
;
477 uint32_t input_slots_array_size
;
480 * An entry per outputs[] in the VS indicating what the VARYING_SLOT_*
481 * of the output is. Used to emit from the VS in the order that the
484 struct vc4_varying_slot
*output_slots
;
486 struct pipe_shader_state
*shader_state
;
488 struct vc4_fs_key
*fs_key
;
489 struct vc4_vs_key
*vs_key
;
491 /* Live ranges of temps. */
492 int *temp_start
, *temp_end
;
494 uint32_t *uniform_data
;
495 enum quniform_contents
*uniform_contents
;
496 uint32_t uniform_array_size
;
497 uint32_t num_uniforms
;
498 uint32_t num_outputs
;
499 uint32_t num_texture_samples
;
500 uint32_t output_position_index
;
501 uint32_t output_color_index
;
502 uint32_t output_point_size_index
;
503 uint32_t output_sample_mask_index
;
509 struct list_head blocks
;
510 int next_block_index
;
511 struct qblock
*cur_block
;
512 struct qblock
*loop_cont_block
;
513 struct qblock
*loop_break_block
;
515 struct list_head qpu_inst_list
;
517 /* Pre-QPU-scheduled instruction containing the last THRSW */
518 uint64_t *last_thrsw
;
521 uint32_t qpu_inst_count
;
522 uint32_t qpu_inst_size
;
526 * Number of inputs from num_inputs remaining to be queued to the read
529 uint32_t num_inputs_remaining
;
531 /* Number of inputs currently in the read FIFO for the VS/CS */
532 uint32_t num_inputs_in_fifo
;
534 /** Next offset in the VPM to read from in the VS/CS */
535 uint32_t vpm_read_offset
;
540 /* Set to compile program in threaded FS mode, where SIG_THREAD_SWITCH
541 * is used to hide texturing latency at the cost of limiting ourselves
542 * to the bottom half of physical reg space.
546 bool last_thrsw_at_top_level
;
551 /* Special nir_load_input intrinsic index for loading the current TLB
554 #define VC4_NIR_TLB_COLOR_READ_INPUT 2000000000
556 #define VC4_NIR_MS_MASK_OUTPUT 2000000000
558 struct vc4_compile
*qir_compile_init(void);
559 void qir_compile_destroy(struct vc4_compile
*c
);
560 struct qblock
*qir_new_block(struct vc4_compile
*c
);
561 void qir_set_emit_block(struct vc4_compile
*c
, struct qblock
*block
);
562 void qir_link_blocks(struct qblock
*predecessor
, struct qblock
*successor
);
563 struct qblock
*qir_entry_block(struct vc4_compile
*c
);
564 struct qblock
*qir_exit_block(struct vc4_compile
*c
);
565 struct qinst
*qir_inst(enum qop op
, struct qreg dst
,
566 struct qreg src0
, struct qreg src1
);
567 void qir_remove_instruction(struct vc4_compile
*c
, struct qinst
*qinst
);
568 struct qreg
qir_uniform(struct vc4_compile
*c
,
569 enum quniform_contents contents
,
571 void qir_schedule_instructions(struct vc4_compile
*c
);
572 void qir_reorder_uniforms(struct vc4_compile
*c
);
573 void qir_emit_uniform_stream_resets(struct vc4_compile
*c
);
575 struct qreg
qir_emit_def(struct vc4_compile
*c
, struct qinst
*inst
);
576 struct qinst
*qir_emit_nondef(struct vc4_compile
*c
, struct qinst
*inst
);
578 struct qreg
qir_get_temp(struct vc4_compile
*c
);
579 void qir_calculate_live_intervals(struct vc4_compile
*c
);
580 int qir_get_nsrc(struct qinst
*inst
);
581 bool qir_reg_equals(struct qreg a
, struct qreg b
);
582 bool qir_has_side_effects(struct vc4_compile
*c
, struct qinst
*inst
);
583 bool qir_has_side_effect_reads(struct vc4_compile
*c
, struct qinst
*inst
);
584 bool qir_is_mul(struct qinst
*inst
);
585 bool qir_is_raw_mov(struct qinst
*inst
);
586 bool qir_is_tex(struct qinst
*inst
);
587 bool qir_is_float_input(struct qinst
*inst
);
588 bool qir_depends_on_flags(struct qinst
*inst
);
589 bool qir_writes_r4(struct qinst
*inst
);
590 struct qreg
qir_follow_movs(struct vc4_compile
*c
, struct qreg reg
);
591 uint8_t qir_channels_written(struct qinst
*inst
);
593 void qir_dump(struct vc4_compile
*c
);
594 void qir_dump_inst(struct vc4_compile
*c
, struct qinst
*inst
);
595 const char *qir_get_stage_name(enum qstage stage
);
597 void qir_validate(struct vc4_compile
*c
);
599 void qir_optimize(struct vc4_compile
*c
);
600 bool qir_opt_algebraic(struct vc4_compile
*c
);
601 bool qir_opt_constant_folding(struct vc4_compile
*c
);
602 bool qir_opt_copy_propagation(struct vc4_compile
*c
);
603 bool qir_opt_dead_code(struct vc4_compile
*c
);
604 bool qir_opt_peephole_sf(struct vc4_compile
*c
);
605 bool qir_opt_small_immediates(struct vc4_compile
*c
);
606 bool qir_opt_vpm(struct vc4_compile
*c
);
607 void vc4_nir_lower_blend(nir_shader
*s
, struct vc4_compile
*c
);
608 void vc4_nir_lower_io(nir_shader
*s
, struct vc4_compile
*c
);
609 nir_ssa_def
*vc4_nir_get_swizzled_channel(struct nir_builder
*b
,
610 nir_ssa_def
**srcs
, int swiz
);
611 void vc4_nir_lower_txf_ms(nir_shader
*s
, struct vc4_compile
*c
);
612 void qir_lower_uniforms(struct vc4_compile
*c
);
614 uint32_t qpu_schedule_instructions(struct vc4_compile
*c
);
616 void qir_SF(struct vc4_compile
*c
, struct qreg src
);
618 static inline struct qreg
619 qir_uniform_ui(struct vc4_compile
*c
, uint32_t ui
)
621 return qir_uniform(c
, QUNIFORM_CONSTANT
, ui
);
624 static inline struct qreg
625 qir_uniform_f(struct vc4_compile
*c
, float f
)
627 return qir_uniform(c
, QUNIFORM_CONSTANT
, fui(f
));
630 #define QIR_ALU0(name) \
631 static inline struct qreg \
632 qir_##name(struct vc4_compile *c) \
634 return qir_emit_def(c, qir_inst(QOP_##name, c->undef, \
635 c->undef, c->undef)); \
637 static inline struct qinst * \
638 qir_##name##_dest(struct vc4_compile *c, struct qreg dest) \
640 return qir_emit_nondef(c, qir_inst(QOP_##name, dest, \
641 c->undef, c->undef)); \
644 #define QIR_ALU1(name) \
645 static inline struct qreg \
646 qir_##name(struct vc4_compile *c, struct qreg a) \
648 return qir_emit_def(c, qir_inst(QOP_##name, c->undef, \
651 static inline struct qinst * \
652 qir_##name##_dest(struct vc4_compile *c, struct qreg dest, \
655 return qir_emit_nondef(c, qir_inst(QOP_##name, dest, a, \
659 #define QIR_ALU2(name) \
660 static inline struct qreg \
661 qir_##name(struct vc4_compile *c, struct qreg a, struct qreg b) \
663 return qir_emit_def(c, qir_inst(QOP_##name, c->undef, a, b)); \
665 static inline struct qinst * \
666 qir_##name##_dest(struct vc4_compile *c, struct qreg dest, \
667 struct qreg a, struct qreg b) \
669 return qir_emit_nondef(c, qir_inst(QOP_##name, dest, a, b)); \
672 #define QIR_NODST_1(name) \
673 static inline struct qinst * \
674 qir_##name(struct vc4_compile *c, struct qreg a) \
676 return qir_emit_nondef(c, qir_inst(QOP_##name, c->undef, \
680 #define QIR_NODST_2(name) \
681 static inline struct qinst * \
682 qir_##name(struct vc4_compile *c, struct qreg a, struct qreg b) \
684 return qir_emit_nondef(c, qir_inst(QOP_##name, c->undef, \
688 #define QIR_PAYLOAD(name) \
689 static inline struct qreg \
690 qir_##name(struct vc4_compile *c) \
692 struct qreg *payload = &c->payload_##name; \
693 if (payload->file != QFILE_NULL) \
695 *payload = qir_get_temp(c); \
696 struct qinst *inst = qir_inst(QOP_##name, *payload, \
697 c->undef, c->undef); \
698 struct qblock *entry = qir_entry_block(c); \
699 list_add(&inst->link, &entry->instructions); \
700 c->defs[payload->index] = inst; \
744 QIR_NODST_2(TEX_DIRECT
)
748 QIR_ALU0(TLB_COLOR_READ
)
751 static inline struct qreg
752 qir_SEL(struct vc4_compile
*c
, uint8_t cond
, struct qreg src0
, struct qreg src1
)
754 struct qreg t
= qir_get_temp(c
);
755 qir_MOV_dest(c
, t
, src1
);
756 qir_MOV_dest(c
, t
, src0
)->cond
= cond
;
760 static inline struct qreg
761 qir_UNPACK_8_F(struct vc4_compile
*c
, struct qreg src
, int i
)
763 struct qreg t
= qir_FMOV(c
, src
);
764 c
->defs
[t
.index
]->src
[0].pack
= QPU_UNPACK_8A
+ i
;
768 static inline struct qreg
769 qir_UNPACK_8_I(struct vc4_compile
*c
, struct qreg src
, int i
)
771 struct qreg t
= qir_MOV(c
, src
);
772 c
->defs
[t
.index
]->src
[0].pack
= QPU_UNPACK_8A
+ i
;
776 static inline struct qreg
777 qir_UNPACK_16_F(struct vc4_compile
*c
, struct qreg src
, int i
)
779 struct qreg t
= qir_FMOV(c
, src
);
780 c
->defs
[t
.index
]->src
[0].pack
= QPU_UNPACK_16A
+ i
;
784 static inline struct qreg
785 qir_UNPACK_16_I(struct vc4_compile
*c
, struct qreg src
, int i
)
787 struct qreg t
= qir_MOV(c
, src
);
788 c
->defs
[t
.index
]->src
[0].pack
= QPU_UNPACK_16A
+ i
;
793 qir_PACK_8_F(struct vc4_compile
*c
, struct qreg dest
, struct qreg val
, int chan
)
796 dest
.pack
= QPU_PACK_MUL_8A
+ chan
;
797 qir_emit_nondef(c
, qir_inst(QOP_MMOV
, dest
, val
, c
->undef
));
800 static inline struct qreg
801 qir_PACK_8888_F(struct vc4_compile
*c
, struct qreg val
)
803 struct qreg dest
= qir_MMOV(c
, val
);
804 c
->defs
[dest
.index
]->dst
.pack
= QPU_PACK_MUL_8888
;
808 static inline struct qreg
809 qir_POW(struct vc4_compile
*c
, struct qreg x
, struct qreg y
)
811 return qir_EXP2(c
, qir_FMUL(c
,
817 qir_VPM_WRITE(struct vc4_compile
*c
, struct qreg val
)
819 qir_MOV_dest(c
, qir_reg(QFILE_VPM
, 0), val
);
822 static inline struct qreg
823 qir_LOAD_IMM(struct vc4_compile
*c
, uint32_t val
)
825 return qir_emit_def(c
, qir_inst(QOP_LOAD_IMM
, c
->undef
,
826 qir_reg(QFILE_LOAD_IMM
, val
), c
->undef
));
829 static inline struct qreg
830 qir_LOAD_IMM_U2(struct vc4_compile
*c
, uint32_t val
)
832 return qir_emit_def(c
, qir_inst(QOP_LOAD_IMM_U2
, c
->undef
,
833 qir_reg(QFILE_LOAD_IMM
, val
),
837 static inline struct qreg
838 qir_LOAD_IMM_I2(struct vc4_compile
*c
, uint32_t val
)
840 return qir_emit_def(c
, qir_inst(QOP_LOAD_IMM_I2
, c
->undef
,
841 qir_reg(QFILE_LOAD_IMM
, val
),
845 /** Shifts the multiply output to the right by rot channels */
846 static inline struct qreg
847 qir_ROT_MUL(struct vc4_compile
*c
, struct qreg val
, uint32_t rot
)
849 return qir_emit_def(c
, qir_inst(QOP_ROT_MUL
, c
->undef
,
851 qir_reg(QFILE_LOAD_IMM
,
852 QPU_SMALL_IMM_MUL_ROT
+ rot
)));
855 static inline struct qinst
*
856 qir_MOV_cond(struct vc4_compile
*c
, uint8_t cond
,
857 struct qreg dest
, struct qreg src
)
859 struct qinst
*mov
= qir_MOV_dest(c
, dest
, src
);
864 static inline struct qinst
*
865 qir_BRANCH(struct vc4_compile
*c
, uint8_t cond
)
867 struct qinst
*inst
= qir_inst(QOP_BRANCH
, c
->undef
, c
->undef
, c
->undef
);
869 qir_emit_nondef(c
, inst
);
873 #define qir_for_each_block(block, c) \
874 list_for_each_entry(struct qblock, block, &c->blocks, link)
876 #define qir_for_each_block_rev(block, c) \
877 list_for_each_entry_rev(struct qblock, block, &c->blocks, link)
879 /* Loop over the non-NULL members of the successors array. */
880 #define qir_for_each_successor(succ, block) \
881 for (struct qblock *succ = block->successors[0]; \
883 succ = (succ == block->successors[1] ? NULL : \
884 block->successors[1]))
886 #define qir_for_each_inst(inst, block) \
887 list_for_each_entry(struct qinst, inst, &block->instructions, link)
889 #define qir_for_each_inst_rev(inst, block) \
890 list_for_each_entry_rev(struct qinst, inst, &block->instructions, link)
892 #define qir_for_each_inst_safe(inst, block) \
893 list_for_each_entry_safe(struct qinst, inst, &block->instructions, link)
895 #define qir_for_each_inst_inorder(inst, c) \
896 qir_for_each_block(_block, c) \
897 qir_for_each_inst(inst, _block)
899 #endif /* VC4_QIR_H */