2 * Copyright © 2014 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
34 #include "util/macros.h"
35 #include "glsl/nir/nir.h"
36 #include "util/list.h"
37 #include "util/u_math.h"
39 #include "vc4_screen.h"
40 #include "vc4_qpu_defines.h"
41 #include "kernel/vc4_packet.h"
42 #include "pipe/p_state.h"
54 * Stores an immediate value in the index field that can be turned
55 * into a small immediate field by qpu_encode_small_immediate().
96 /* Note: Orderings of these compares must be the same as in
97 * qpu_defines.h. Selects the src[0] if the ns flag bit is set,
105 /* Selects the src[0] if the ns flag bit is set, otherwise src[1]. */
121 QOP_TLB_DISCARD_SETUP
,
122 QOP_TLB_STENCIL_SETUP
,
125 QOP_TLB_COLOR_WRITE_MS
,
136 /** Texture x coordinate parameter write */
138 /** Texture y coordinate parameter write */
140 /** Texture border color parameter or cube map z coordinate write */
142 /** Texture LOD bias parameter write */
146 * Texture-unit 4-byte read with address provided direct in S
149 * The first operand is the offset from the start of the UBO, and the
150 * second is the uniform that has the UBO's base pointer.
155 * Signal of texture read being necessary and then reading r4 into
161 struct queued_qpu_inst
{
162 struct list_head link
;
167 struct list_head link
;
177 * Coordinate shader, runs during binning, before the VS, and just
185 enum quniform_contents
{
187 * Indicates that a constant 32-bit value is copied from the program's
192 * Indicates that the program's uniform contents are used as an index
193 * into the GL uniform storage.
198 * Scaling factors from clip coordinates to relative to the viewport
201 * This is used by the coordinate and vertex shaders to produce the
202 * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed
203 * point offsets from the viewport ccenter.
205 QUNIFORM_VIEWPORT_X_SCALE
,
206 QUNIFORM_VIEWPORT_Y_SCALE
,
209 QUNIFORM_VIEWPORT_Z_OFFSET
,
210 QUNIFORM_VIEWPORT_Z_SCALE
,
212 QUNIFORM_USER_CLIP_PLANE
,
215 * A reference to a texture config parameter 0 uniform.
217 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
218 * defines texture type, miplevels, and such. It will be found as a
219 * parameter to the first QOP_TEX_[STRB] instruction in a sequence.
221 QUNIFORM_TEXTURE_CONFIG_P0
,
224 * A reference to a texture config parameter 1 uniform.
226 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
227 * defines texture width, height, filters, and wrap modes. It will be
228 * found as a parameter to the second QOP_TEX_[STRB] instruction in a
231 QUNIFORM_TEXTURE_CONFIG_P1
,
233 /** A reference to a texture config parameter 2 cubemap stride uniform */
234 QUNIFORM_TEXTURE_CONFIG_P2
,
236 QUNIFORM_TEXTURE_MSAA_ADDR
,
240 QUNIFORM_TEXRECT_SCALE_X
,
241 QUNIFORM_TEXRECT_SCALE_Y
,
243 QUNIFORM_TEXTURE_BORDER_COLOR
,
245 QUNIFORM_BLEND_CONST_COLOR_X
,
246 QUNIFORM_BLEND_CONST_COLOR_Y
,
247 QUNIFORM_BLEND_CONST_COLOR_Z
,
248 QUNIFORM_BLEND_CONST_COLOR_W
,
249 QUNIFORM_BLEND_CONST_COLOR_RGBA
,
250 QUNIFORM_BLEND_CONST_COLOR_AAAA
,
255 QUNIFORM_SAMPLE_MASK
,
258 struct vc4_varying_slot
{
263 struct vc4_compiler_ubo_range
{
265 * offset in bytes from the start of the ubo where this range is
268 * Only set once used is set.
273 * offset in bytes from the start of the gallium uniforms where the
278 /** size in bytes of this ubo range */
282 * Set if this range is used by the shader for indirect uniforms
289 struct vc4_uncompiled_shader
*shader_state
;
291 enum pipe_format format
;
295 unsigned compare_mode
:1;
296 unsigned compare_func
:3;
301 uint16_t msaa_width
, msaa_height
;
304 } tex
[VC4_MAX_TEXTURE_SAMPLERS
];
310 enum pipe_format color_format
;
312 bool stencil_enabled
;
313 bool stencil_twoside
;
314 bool stencil_full_writemasks
;
318 bool point_coord_upper_left
;
321 bool sample_coverage
;
322 bool sample_alpha_to_coverage
;
323 bool sample_alpha_to_one
;
324 uint8_t alpha_test_func
;
325 uint8_t logicop_func
;
326 uint32_t point_sprite_mask
;
328 struct pipe_rt_blend_state blend
;
335 * This is a proxy for the array of FS input semantics, which is
336 * larger than we would want to put in the key.
338 uint64_t compiled_fs_id
;
340 enum pipe_format attr_formats
[8];
342 bool per_vertex_point_size
;
346 struct vc4_context
*vc4
;
348 nir_function_impl
*impl
;
349 struct exec_list
*cf_node_list
;
352 * Mapping from nir_register * or nir_ssa_def * to array of struct
353 * qreg for the values.
355 struct hash_table
*def_ht
;
357 /* For each temp, the instruction generating its value. */
359 uint32_t defs_array_size
;
362 * Inputs to the shader, arranged by TGSI declaration order.
364 * Not all fragment shader QFILE_VARY reads are present in this array.
367 struct qreg
*outputs
;
368 bool msaa_per_sample_output
;
369 struct qreg color_reads
[VC4_MAX_SAMPLES
];
370 struct qreg sample_colors
[VC4_MAX_SAMPLES
];
371 uint32_t inputs_array_size
;
372 uint32_t outputs_array_size
;
373 uint32_t uniforms_array_size
;
375 struct vc4_compiler_ubo_range
*ubo_ranges
;
376 uint32_t ubo_ranges_array_size
;
377 /** Number of uniform areas declared in ubo_ranges. */
378 uint32_t num_uniform_ranges
;
379 /** Number of uniform areas used for indirect addressed loads. */
380 uint32_t num_ubo_ranges
;
381 uint32_t next_ubo_dst_offset
;
383 struct qreg line_x
, point_x
, point_y
;
386 uint8_t vattr_sizes
[8];
389 * Array of the VARYING_SLOT_* of all FS QFILE_VARY reads.
391 * This includes those that aren't part of the VPM varyings, like
392 * point/line coordinates.
394 struct vc4_varying_slot
*input_slots
;
395 uint32_t num_input_slots
;
396 uint32_t input_slots_array_size
;
399 * An entry per outputs[] in the VS indicating what the VARYING_SLOT_*
400 * of the output is. Used to emit from the VS in the order that the
403 struct vc4_varying_slot
*output_slots
;
405 struct pipe_shader_state
*shader_state
;
407 struct vc4_fs_key
*fs_key
;
408 struct vc4_vs_key
*vs_key
;
410 uint32_t *uniform_data
;
411 enum quniform_contents
*uniform_contents
;
412 uint32_t uniform_array_size
;
413 uint32_t num_uniforms
;
414 uint32_t num_outputs
;
415 uint32_t num_texture_samples
;
416 uint32_t output_position_index
;
417 uint32_t output_color_index
;
418 uint32_t output_point_size_index
;
419 uint32_t output_sample_mask_index
;
424 struct list_head instructions
;
425 uint32_t immediates
[1024];
427 struct list_head qpu_inst_list
;
429 uint32_t qpu_inst_count
;
430 uint32_t qpu_inst_size
;
437 /* Special nir_load_input intrinsic index for loading the current TLB
440 #define VC4_NIR_TLB_COLOR_READ_INPUT 2000000000
442 #define VC4_NIR_MS_MASK_OUTPUT 2000000000
444 /* Special offset for nir_load_uniform values to get a QUNIFORM_*
445 * state-dependent value.
447 #define VC4_NIR_STATE_UNIFORM_OFFSET 1000000000
449 struct vc4_compile
*qir_compile_init(void);
450 void qir_compile_destroy(struct vc4_compile
*c
);
451 struct qinst
*qir_inst(enum qop op
, struct qreg dst
,
452 struct qreg src0
, struct qreg src1
);
453 struct qinst
*qir_inst4(enum qop op
, struct qreg dst
,
458 void qir_remove_instruction(struct vc4_compile
*c
, struct qinst
*qinst
);
459 struct qreg
qir_uniform(struct vc4_compile
*c
,
460 enum quniform_contents contents
,
462 void qir_schedule_instructions(struct vc4_compile
*c
);
463 void qir_reorder_uniforms(struct vc4_compile
*c
);
465 void qir_emit(struct vc4_compile
*c
, struct qinst
*inst
);
466 static inline void qir_emit_nodef(struct vc4_compile
*c
, struct qinst
*inst
)
468 list_addtail(&inst
->link
, &c
->instructions
);
471 struct qreg
qir_get_temp(struct vc4_compile
*c
);
472 int qir_get_op_nsrc(enum qop qop
);
473 bool qir_reg_equals(struct qreg a
, struct qreg b
);
474 bool qir_has_side_effects(struct vc4_compile
*c
, struct qinst
*inst
);
475 bool qir_has_side_effect_reads(struct vc4_compile
*c
, struct qinst
*inst
);
476 bool qir_is_multi_instruction(struct qinst
*inst
);
477 bool qir_is_mul(struct qinst
*inst
);
478 bool qir_is_raw_mov(struct qinst
*inst
);
479 bool qir_is_tex(struct qinst
*inst
);
480 bool qir_is_float_input(struct qinst
*inst
);
481 bool qir_depends_on_flags(struct qinst
*inst
);
482 bool qir_writes_r4(struct qinst
*inst
);
483 struct qreg
qir_follow_movs(struct vc4_compile
*c
, struct qreg reg
);
485 void qir_dump(struct vc4_compile
*c
);
486 void qir_dump_inst(struct vc4_compile
*c
, struct qinst
*inst
);
487 const char *qir_get_stage_name(enum qstage stage
);
489 void qir_optimize(struct vc4_compile
*c
);
490 bool qir_opt_algebraic(struct vc4_compile
*c
);
491 bool qir_opt_constant_folding(struct vc4_compile
*c
);
492 bool qir_opt_copy_propagation(struct vc4_compile
*c
);
493 bool qir_opt_cse(struct vc4_compile
*c
);
494 bool qir_opt_dead_code(struct vc4_compile
*c
);
495 bool qir_opt_small_immediates(struct vc4_compile
*c
);
496 bool qir_opt_vpm_writes(struct vc4_compile
*c
);
497 void vc4_nir_lower_blend(struct vc4_compile
*c
);
498 void vc4_nir_lower_io(struct vc4_compile
*c
);
499 nir_ssa_def
*vc4_nir_get_state_uniform(struct nir_builder
*b
,
500 enum quniform_contents contents
);
501 nir_ssa_def
*vc4_nir_get_swizzled_channel(struct nir_builder
*b
,
502 nir_ssa_def
**srcs
, int swiz
);
503 void vc4_nir_lower_txf_ms(struct vc4_compile
*c
);
504 void qir_lower_uniforms(struct vc4_compile
*c
);
506 uint32_t qpu_schedule_instructions(struct vc4_compile
*c
);
508 void qir_SF(struct vc4_compile
*c
, struct qreg src
);
510 static inline struct qreg
511 qir_uniform_ui(struct vc4_compile
*c
, uint32_t ui
)
513 return qir_uniform(c
, QUNIFORM_CONSTANT
, ui
);
516 static inline struct qreg
517 qir_uniform_f(struct vc4_compile
*c
, float f
)
519 return qir_uniform(c
, QUNIFORM_CONSTANT
, fui(f
));
522 #define QIR_ALU0(name) \
523 static inline struct qreg \
524 qir_##name(struct vc4_compile *c) \
526 struct qreg t = qir_get_temp(c); \
527 qir_emit(c, qir_inst(QOP_##name, t, c->undef, c->undef)); \
531 #define QIR_ALU1(name) \
532 static inline struct qreg \
533 qir_##name(struct vc4_compile *c, struct qreg a) \
535 struct qreg t = qir_get_temp(c); \
536 qir_emit(c, qir_inst(QOP_##name, t, a, c->undef)); \
540 qir_##name##_dest(struct vc4_compile *c, struct qreg dest, \
543 qir_emit_nodef(c, qir_inst(QOP_##name, dest, a, c->undef)); \
546 #define QIR_ALU2(name) \
547 static inline struct qreg \
548 qir_##name(struct vc4_compile *c, struct qreg a, struct qreg b) \
550 struct qreg t = qir_get_temp(c); \
551 qir_emit(c, qir_inst(QOP_##name, t, a, b)); \
555 qir_##name##_dest(struct vc4_compile *c, struct qreg dest, \
556 struct qreg a, struct qreg b) \
558 qir_emit_nodef(c, qir_inst(QOP_##name, dest, a, b)); \
561 #define QIR_NODST_1(name) \
563 qir_##name(struct vc4_compile *c, struct qreg a) \
565 qir_emit(c, qir_inst(QOP_##name, c->undef, a, c->undef)); \
568 #define QIR_NODST_2(name) \
570 qir_##name(struct vc4_compile *c, struct qreg a, struct qreg b) \
572 qir_emit(c, qir_inst(QOP_##name, c->undef, a, b)); \
575 #define QIR_PACK(name) \
576 static inline struct qreg \
577 qir_##name(struct vc4_compile *c, struct qreg dest, struct qreg a) \
579 qir_emit_nodef(c, qir_inst(QOP_##name, dest, a, c->undef)); \
635 QIR_NODST_2(TEX_DIRECT
)
640 QIR_ALU0(FRAG_REV_FLAG
)
642 QIR_ALU0(TLB_COLOR_READ
)
643 QIR_NODST_1(TLB_COLOR_WRITE
)
644 QIR_NODST_1(TLB_COLOR_WRITE_MS
)
645 QIR_NODST_1(TLB_Z_WRITE
)
646 QIR_NODST_1(TLB_DISCARD_SETUP
)
647 QIR_NODST_1(TLB_STENCIL_SETUP
)
650 static inline struct qreg
651 qir_UNPACK_8_F(struct vc4_compile
*c
, struct qreg src
, int i
)
653 struct qreg t
= qir_FMOV(c
, src
);
654 c
->defs
[t
.index
]->src
[0].pack
= QPU_UNPACK_8A
+ i
;
658 static inline struct qreg
659 qir_UNPACK_8_I(struct vc4_compile
*c
, struct qreg src
, int i
)
661 struct qreg t
= qir_MOV(c
, src
);
662 c
->defs
[t
.index
]->src
[0].pack
= QPU_UNPACK_8A
+ i
;
666 static inline struct qreg
667 qir_UNPACK_16_F(struct vc4_compile
*c
, struct qreg src
, int i
)
669 struct qreg t
= qir_FMOV(c
, src
);
670 c
->defs
[t
.index
]->src
[0].pack
= QPU_UNPACK_16A
+ i
;
674 static inline struct qreg
675 qir_UNPACK_16_I(struct vc4_compile
*c
, struct qreg src
, int i
)
677 struct qreg t
= qir_MOV(c
, src
);
678 c
->defs
[t
.index
]->src
[0].pack
= QPU_UNPACK_16A
+ i
;
683 qir_PACK_8_F(struct vc4_compile
*c
, struct qreg dest
, struct qreg val
, int chan
)
686 dest
.pack
= QPU_PACK_MUL_8A
+ chan
;
687 qir_emit(c
, qir_inst(QOP_MMOV
, dest
, val
, c
->undef
));
688 if (dest
.file
== QFILE_TEMP
)
689 c
->defs
[dest
.index
] = NULL
;
692 static inline struct qreg
693 qir_PACK_8888_F(struct vc4_compile
*c
, struct qreg val
)
695 struct qreg dest
= qir_MMOV(c
, val
);
696 c
->defs
[dest
.index
]->dst
.pack
= QPU_PACK_MUL_8888
;
700 static inline struct qreg
701 qir_POW(struct vc4_compile
*c
, struct qreg x
, struct qreg y
)
703 return qir_EXP2(c
, qir_FMUL(c
,
709 qir_VPM_WRITE(struct vc4_compile
*c
, struct qreg val
)
711 static const struct qreg vpm
= { QFILE_VPM
, 0 };
712 qir_emit(c
, qir_inst(QOP_MOV
, vpm
, val
, c
->undef
));
715 #endif /* VC4_QIR_H */