ddde96db6b4e1e7885bce9c34def5627d9b7d18f
[mesa.git] / src / gallium / drivers / vc4 / vc4_qir.h
1 /*
2 * Copyright © 2014 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef VC4_QIR_H
25 #define VC4_QIR_H
26
27 #include <assert.h>
28 #include <stdio.h>
29 #include <stdlib.h>
30 #include <stdbool.h>
31 #include <stdint.h>
32 #include <string.h>
33
34 #include "util/macros.h"
35 #include "glsl/nir/nir.h"
36 #include "util/list.h"
37 #include "util/u_math.h"
38
39 #include "vc4_screen.h"
40 #include "pipe/p_state.h"
41
42 struct nir_builder;
43
44 enum qfile {
45 QFILE_NULL,
46 QFILE_TEMP,
47 QFILE_VARY,
48 QFILE_UNIF,
49 QFILE_VPM,
50
51 /**
52 * Stores an immediate value in the index field that can be turned
53 * into a small immediate field by qpu_encode_small_immediate().
54 */
55 QFILE_SMALL_IMM,
56 };
57
58 struct qreg {
59 enum qfile file;
60 uint32_t index;
61 int pack;
62 };
63
64 enum qop {
65 QOP_UNDEF,
66 QOP_MOV,
67 QOP_FADD,
68 QOP_FSUB,
69 QOP_FMUL,
70 QOP_MUL24,
71 QOP_FMIN,
72 QOP_FMAX,
73 QOP_FMINABS,
74 QOP_FMAXABS,
75 QOP_ADD,
76 QOP_SUB,
77 QOP_SHL,
78 QOP_SHR,
79 QOP_ASR,
80 QOP_MIN,
81 QOP_MAX,
82 QOP_AND,
83 QOP_OR,
84 QOP_XOR,
85 QOP_NOT,
86
87 /* Note: Orderings of these compares must be the same as in
88 * qpu_defines.h. Selects the src[0] if the ns flag bit is set,
89 * otherwise 0. */
90 QOP_SEL_X_0_ZS,
91 QOP_SEL_X_0_ZC,
92 QOP_SEL_X_0_NS,
93 QOP_SEL_X_0_NC,
94 /* Selects the src[0] if the ns flag bit is set, otherwise src[1]. */
95 QOP_SEL_X_Y_ZS,
96 QOP_SEL_X_Y_ZC,
97 QOP_SEL_X_Y_NS,
98 QOP_SEL_X_Y_NC,
99
100 QOP_FTOI,
101 QOP_ITOF,
102 QOP_RCP,
103 QOP_RSQ,
104 QOP_EXP2,
105 QOP_LOG2,
106 QOP_VW_SETUP,
107 QOP_VR_SETUP,
108 QOP_PACK_8888_F,
109 QOP_PACK_8A_F,
110 QOP_PACK_8B_F,
111 QOP_PACK_8C_F,
112 QOP_PACK_8D_F,
113 QOP_TLB_DISCARD_SETUP,
114 QOP_TLB_STENCIL_SETUP,
115 QOP_TLB_Z_WRITE,
116 QOP_TLB_COLOR_WRITE,
117 QOP_TLB_COLOR_READ,
118 QOP_VARY_ADD_C,
119
120 QOP_FRAG_X,
121 QOP_FRAG_Y,
122 QOP_FRAG_Z,
123 QOP_FRAG_W,
124 QOP_FRAG_REV_FLAG,
125
126 QOP_UNPACK_8A_F,
127 QOP_UNPACK_8B_F,
128 QOP_UNPACK_8C_F,
129 QOP_UNPACK_8D_F,
130 QOP_UNPACK_16A_F,
131 QOP_UNPACK_16B_F,
132
133 QOP_UNPACK_8A_I,
134 QOP_UNPACK_8B_I,
135 QOP_UNPACK_8C_I,
136 QOP_UNPACK_8D_I,
137 QOP_UNPACK_16A_I,
138 QOP_UNPACK_16B_I,
139
140 /** Texture x coordinate parameter write */
141 QOP_TEX_S,
142 /** Texture y coordinate parameter write */
143 QOP_TEX_T,
144 /** Texture border color parameter or cube map z coordinate write */
145 QOP_TEX_R,
146 /** Texture LOD bias parameter write */
147 QOP_TEX_B,
148
149 /**
150 * Texture-unit 4-byte read with address provided direct in S
151 * cooordinate.
152 *
153 * The first operand is the offset from the start of the UBO, and the
154 * second is the uniform that has the UBO's base pointer.
155 */
156 QOP_TEX_DIRECT,
157
158 /**
159 * Signal of texture read being necessary and then reading r4 into
160 * the destination
161 */
162 QOP_TEX_RESULT,
163 };
164
165 struct queued_qpu_inst {
166 struct list_head link;
167 uint64_t inst;
168 };
169
170 struct qinst {
171 struct list_head link;
172
173 enum qop op;
174 struct qreg dst;
175 struct qreg *src;
176 bool sf;
177 };
178
179 enum qstage {
180 /**
181 * Coordinate shader, runs during binning, before the VS, and just
182 * outputs position.
183 */
184 QSTAGE_COORD,
185 QSTAGE_VERT,
186 QSTAGE_FRAG,
187 };
188
189 enum quniform_contents {
190 /**
191 * Indicates that a constant 32-bit value is copied from the program's
192 * uniform contents.
193 */
194 QUNIFORM_CONSTANT,
195 /**
196 * Indicates that the program's uniform contents are used as an index
197 * into the GL uniform storage.
198 */
199 QUNIFORM_UNIFORM,
200
201 /** @{
202 * Scaling factors from clip coordinates to relative to the viewport
203 * center.
204 *
205 * This is used by the coordinate and vertex shaders to produce the
206 * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed
207 * point offsets from the viewport ccenter.
208 */
209 QUNIFORM_VIEWPORT_X_SCALE,
210 QUNIFORM_VIEWPORT_Y_SCALE,
211 /** @} */
212
213 QUNIFORM_VIEWPORT_Z_OFFSET,
214 QUNIFORM_VIEWPORT_Z_SCALE,
215
216 QUNIFORM_USER_CLIP_PLANE,
217
218 /**
219 * A reference to a texture config parameter 0 uniform.
220 *
221 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
222 * defines texture type, miplevels, and such. It will be found as a
223 * parameter to the first QOP_TEX_[STRB] instruction in a sequence.
224 */
225 QUNIFORM_TEXTURE_CONFIG_P0,
226
227 /**
228 * A reference to a texture config parameter 1 uniform.
229 *
230 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
231 * defines texture width, height, filters, and wrap modes. It will be
232 * found as a parameter to the second QOP_TEX_[STRB] instruction in a
233 * sequence.
234 */
235 QUNIFORM_TEXTURE_CONFIG_P1,
236
237 /** A reference to a texture config parameter 2 cubemap stride uniform */
238 QUNIFORM_TEXTURE_CONFIG_P2,
239
240 QUNIFORM_UBO_ADDR,
241
242 QUNIFORM_TEXRECT_SCALE_X,
243 QUNIFORM_TEXRECT_SCALE_Y,
244
245 QUNIFORM_TEXTURE_BORDER_COLOR,
246
247 QUNIFORM_BLEND_CONST_COLOR_X,
248 QUNIFORM_BLEND_CONST_COLOR_Y,
249 QUNIFORM_BLEND_CONST_COLOR_Z,
250 QUNIFORM_BLEND_CONST_COLOR_W,
251
252 QUNIFORM_STENCIL,
253
254 QUNIFORM_ALPHA_REF,
255 };
256
257 struct vc4_varying_slot {
258 uint8_t slot;
259 uint8_t swizzle;
260 };
261
262 struct vc4_compiler_ubo_range {
263 /**
264 * offset in bytes from the start of the ubo where this range is
265 * uploaded.
266 *
267 * Only set once used is set.
268 */
269 uint32_t dst_offset;
270
271 /**
272 * offset in bytes from the start of the gallium uniforms where the
273 * data comes from.
274 */
275 uint32_t src_offset;
276
277 /** size in bytes of this ubo range */
278 uint32_t size;
279
280 /**
281 * Set if this range is used by the shader for indirect uniforms
282 * access.
283 */
284 bool used;
285 };
286
287 struct vc4_key {
288 struct vc4_uncompiled_shader *shader_state;
289 struct {
290 enum pipe_format format;
291 unsigned compare_mode:1;
292 unsigned compare_func:3;
293 unsigned wrap_s:3;
294 unsigned wrap_t:3;
295 uint8_t swizzle[4];
296 } tex[VC4_MAX_TEXTURE_SAMPLERS];
297 uint8_t ucp_enables;
298 };
299
300 struct vc4_fs_key {
301 struct vc4_key base;
302 enum pipe_format color_format;
303 bool depth_enabled;
304 bool stencil_enabled;
305 bool stencil_twoside;
306 bool stencil_full_writemasks;
307 bool is_points;
308 bool is_lines;
309 bool alpha_test;
310 bool point_coord_upper_left;
311 bool light_twoside;
312 uint8_t alpha_test_func;
313 uint8_t logicop_func;
314 uint32_t point_sprite_mask;
315
316 struct pipe_rt_blend_state blend;
317 };
318
319 struct vc4_vs_key {
320 struct vc4_key base;
321
322 /**
323 * This is a proxy for the array of FS input semantics, which is
324 * larger than we would want to put in the key.
325 */
326 uint64_t compiled_fs_id;
327
328 enum pipe_format attr_formats[8];
329 bool is_coord;
330 bool per_vertex_point_size;
331 };
332
333 struct vc4_compile {
334 struct vc4_context *vc4;
335 nir_shader *s;
336 nir_function_impl *impl;
337 struct exec_list *cf_node_list;
338
339 /**
340 * Mapping from nir_register * or nir_ssa_def * to array of struct
341 * qreg for the values.
342 */
343 struct hash_table *def_ht;
344
345 /* For each temp, the instruction generating its value. */
346 struct qinst **defs;
347 uint32_t defs_array_size;
348
349 /**
350 * Inputs to the shader, arranged by TGSI declaration order.
351 *
352 * Not all fragment shader QFILE_VARY reads are present in this array.
353 */
354 struct qreg *inputs;
355 struct qreg *outputs;
356 uint32_t inputs_array_size;
357 uint32_t outputs_array_size;
358 uint32_t uniforms_array_size;
359
360 struct vc4_compiler_ubo_range *ubo_ranges;
361 uint32_t ubo_ranges_array_size;
362 /** Number of uniform areas declared in ubo_ranges. */
363 uint32_t num_uniform_ranges;
364 /** Number of uniform areas used for indirect addressed loads. */
365 uint32_t num_ubo_ranges;
366 uint32_t next_ubo_dst_offset;
367
368 struct qreg line_x, point_x, point_y;
369 struct qreg discard;
370
371 uint8_t vattr_sizes[8];
372
373 /**
374 * Array of the VARYING_SLOT_* of all FS QFILE_VARY reads.
375 *
376 * This includes those that aren't part of the VPM varyings, like
377 * point/line coordinates.
378 */
379 struct vc4_varying_slot *input_slots;
380 uint32_t num_input_slots;
381 uint32_t input_slots_array_size;
382
383 /**
384 * An entry per outputs[] in the VS indicating what the VARYING_SLOT_*
385 * of the output is. Used to emit from the VS in the order that the
386 * FS needs.
387 */
388 struct vc4_varying_slot *output_slots;
389
390 struct pipe_shader_state *shader_state;
391 struct vc4_key *key;
392 struct vc4_fs_key *fs_key;
393 struct vc4_vs_key *vs_key;
394
395 uint32_t *uniform_data;
396 enum quniform_contents *uniform_contents;
397 uint32_t uniform_array_size;
398 uint32_t num_uniforms;
399 uint32_t num_outputs;
400 uint32_t num_texture_samples;
401 uint32_t output_position_index;
402 uint32_t output_clipvertex_index;
403 uint32_t output_color_index;
404 uint32_t output_point_size_index;
405
406 struct qreg undef;
407 enum qstage stage;
408 uint32_t num_temps;
409 struct list_head instructions;
410 uint32_t immediates[1024];
411
412 struct list_head qpu_inst_list;
413 uint64_t *qpu_insts;
414 uint32_t qpu_inst_count;
415 uint32_t qpu_inst_size;
416 uint32_t num_inputs;
417
418 uint32_t program_id;
419 uint32_t variant_id;
420 };
421
422 /* Special nir_load_input intrinsic index for loading the current TLB
423 * destination color.
424 */
425 #define VC4_NIR_TLB_COLOR_READ_INPUT 2000000000
426
427 /* Special offset for nir_load_uniform values to get a QUNIFORM_*
428 * state-dependent value.
429 */
430 #define VC4_NIR_STATE_UNIFORM_OFFSET 2000000000
431
432 struct vc4_compile *qir_compile_init(void);
433 void qir_compile_destroy(struct vc4_compile *c);
434 struct qinst *qir_inst(enum qop op, struct qreg dst,
435 struct qreg src0, struct qreg src1);
436 struct qinst *qir_inst4(enum qop op, struct qreg dst,
437 struct qreg a,
438 struct qreg b,
439 struct qreg c,
440 struct qreg d);
441 void qir_remove_instruction(struct vc4_compile *c, struct qinst *qinst);
442 struct qreg qir_uniform(struct vc4_compile *c,
443 enum quniform_contents contents,
444 uint32_t data);
445 void qir_reorder_uniforms(struct vc4_compile *c);
446
447 void qir_emit(struct vc4_compile *c, struct qinst *inst);
448 static inline void qir_emit_nodef(struct vc4_compile *c, struct qinst *inst)
449 {
450 list_addtail(&inst->link, &c->instructions);
451 }
452
453 struct qreg qir_get_temp(struct vc4_compile *c);
454 int qir_get_op_nsrc(enum qop qop);
455 bool qir_reg_equals(struct qreg a, struct qreg b);
456 bool qir_has_side_effects(struct vc4_compile *c, struct qinst *inst);
457 bool qir_has_side_effect_reads(struct vc4_compile *c, struct qinst *inst);
458 bool qir_is_multi_instruction(struct qinst *inst);
459 bool qir_is_mul(struct qinst *inst);
460 bool qir_is_tex(struct qinst *inst);
461 bool qir_depends_on_flags(struct qinst *inst);
462 bool qir_writes_r4(struct qinst *inst);
463 bool qir_src_needs_a_file(struct qinst *inst);
464 struct qreg qir_follow_movs(struct vc4_compile *c, struct qreg reg);
465
466 void qir_dump(struct vc4_compile *c);
467 void qir_dump_inst(struct vc4_compile *c, struct qinst *inst);
468 const char *qir_get_stage_name(enum qstage stage);
469
470 void qir_optimize(struct vc4_compile *c);
471 bool qir_opt_algebraic(struct vc4_compile *c);
472 bool qir_opt_constant_folding(struct vc4_compile *c);
473 bool qir_opt_copy_propagation(struct vc4_compile *c);
474 bool qir_opt_cse(struct vc4_compile *c);
475 bool qir_opt_dead_code(struct vc4_compile *c);
476 bool qir_opt_small_immediates(struct vc4_compile *c);
477 bool qir_opt_vpm_writes(struct vc4_compile *c);
478 void vc4_nir_lower_blend(struct vc4_compile *c);
479 void vc4_nir_lower_io(struct vc4_compile *c);
480 nir_ssa_def *vc4_nir_get_state_uniform(struct nir_builder *b,
481 enum quniform_contents contents);
482 nir_ssa_def *vc4_nir_get_swizzled_channel(struct nir_builder *b,
483 nir_ssa_def **srcs, int swiz);
484 void qir_lower_uniforms(struct vc4_compile *c);
485
486 void qpu_schedule_instructions(struct vc4_compile *c);
487
488 void qir_SF(struct vc4_compile *c, struct qreg src);
489
490 static inline struct qreg
491 qir_uniform_ui(struct vc4_compile *c, uint32_t ui)
492 {
493 return qir_uniform(c, QUNIFORM_CONSTANT, ui);
494 }
495
496 static inline struct qreg
497 qir_uniform_f(struct vc4_compile *c, float f)
498 {
499 return qir_uniform(c, QUNIFORM_CONSTANT, fui(f));
500 }
501
502 #define QIR_ALU0(name) \
503 static inline struct qreg \
504 qir_##name(struct vc4_compile *c) \
505 { \
506 struct qreg t = qir_get_temp(c); \
507 qir_emit(c, qir_inst(QOP_##name, t, c->undef, c->undef)); \
508 return t; \
509 }
510
511 #define QIR_ALU1(name) \
512 static inline struct qreg \
513 qir_##name(struct vc4_compile *c, struct qreg a) \
514 { \
515 struct qreg t = qir_get_temp(c); \
516 qir_emit(c, qir_inst(QOP_##name, t, a, c->undef)); \
517 return t; \
518 } \
519 static inline void \
520 qir_##name##_dest(struct vc4_compile *c, struct qreg dest, \
521 struct qreg a) \
522 { \
523 qir_emit_nodef(c, qir_inst(QOP_##name, dest, a, c->undef)); \
524 }
525
526 #define QIR_ALU2(name) \
527 static inline struct qreg \
528 qir_##name(struct vc4_compile *c, struct qreg a, struct qreg b) \
529 { \
530 struct qreg t = qir_get_temp(c); \
531 qir_emit(c, qir_inst(QOP_##name, t, a, b)); \
532 return t; \
533 } \
534 static inline void \
535 qir_##name##_dest(struct vc4_compile *c, struct qreg dest, \
536 struct qreg a, struct qreg b) \
537 { \
538 qir_emit_nodef(c, qir_inst(QOP_##name, dest, a, b)); \
539 }
540
541 #define QIR_NODST_1(name) \
542 static inline void \
543 qir_##name(struct vc4_compile *c, struct qreg a) \
544 { \
545 qir_emit(c, qir_inst(QOP_##name, c->undef, a, c->undef)); \
546 }
547
548 #define QIR_NODST_2(name) \
549 static inline void \
550 qir_##name(struct vc4_compile *c, struct qreg a, struct qreg b) \
551 { \
552 qir_emit(c, qir_inst(QOP_##name, c->undef, a, b)); \
553 }
554
555 #define QIR_PACK(name) \
556 static inline struct qreg \
557 qir_##name(struct vc4_compile *c, struct qreg dest, struct qreg a) \
558 { \
559 qir_emit_nodef(c, qir_inst(QOP_##name, dest, a, c->undef)); \
560 return dest; \
561 }
562
563 QIR_ALU1(MOV)
564 QIR_ALU2(FADD)
565 QIR_ALU2(FSUB)
566 QIR_ALU2(FMUL)
567 QIR_ALU2(MUL24)
568 QIR_ALU1(SEL_X_0_ZS)
569 QIR_ALU1(SEL_X_0_ZC)
570 QIR_ALU1(SEL_X_0_NS)
571 QIR_ALU1(SEL_X_0_NC)
572 QIR_ALU2(SEL_X_Y_ZS)
573 QIR_ALU2(SEL_X_Y_ZC)
574 QIR_ALU2(SEL_X_Y_NS)
575 QIR_ALU2(SEL_X_Y_NC)
576 QIR_ALU2(FMIN)
577 QIR_ALU2(FMAX)
578 QIR_ALU2(FMINABS)
579 QIR_ALU2(FMAXABS)
580 QIR_ALU1(FTOI)
581 QIR_ALU1(ITOF)
582
583 QIR_ALU2(ADD)
584 QIR_ALU2(SUB)
585 QIR_ALU2(SHL)
586 QIR_ALU2(SHR)
587 QIR_ALU2(ASR)
588 QIR_ALU2(MIN)
589 QIR_ALU2(MAX)
590 QIR_ALU2(AND)
591 QIR_ALU2(OR)
592 QIR_ALU2(XOR)
593 QIR_ALU1(NOT)
594
595 QIR_ALU1(RCP)
596 QIR_ALU1(RSQ)
597 QIR_ALU1(EXP2)
598 QIR_ALU1(LOG2)
599 QIR_ALU1(PACK_8888_F)
600 QIR_PACK(PACK_8A_F)
601 QIR_PACK(PACK_8B_F)
602 QIR_PACK(PACK_8C_F)
603 QIR_PACK(PACK_8D_F)
604 QIR_ALU1(VARY_ADD_C)
605 QIR_NODST_2(TEX_S)
606 QIR_NODST_2(TEX_T)
607 QIR_NODST_2(TEX_R)
608 QIR_NODST_2(TEX_B)
609 QIR_NODST_2(TEX_DIRECT)
610 QIR_ALU0(FRAG_X)
611 QIR_ALU0(FRAG_Y)
612 QIR_ALU0(FRAG_Z)
613 QIR_ALU0(FRAG_W)
614 QIR_ALU0(FRAG_REV_FLAG)
615 QIR_ALU0(TEX_RESULT)
616 QIR_ALU0(TLB_COLOR_READ)
617 QIR_NODST_1(TLB_COLOR_WRITE)
618 QIR_NODST_1(TLB_Z_WRITE)
619 QIR_NODST_1(TLB_DISCARD_SETUP)
620 QIR_NODST_1(TLB_STENCIL_SETUP)
621
622 static inline struct qreg
623 qir_UNPACK_8_F(struct vc4_compile *c, struct qreg src, int i)
624 {
625 struct qreg t = qir_get_temp(c);
626 qir_emit(c, qir_inst(QOP_UNPACK_8A_F + i, t, src, c->undef));
627 return t;
628 }
629
630 static inline struct qreg
631 qir_UNPACK_8_I(struct vc4_compile *c, struct qreg src, int i)
632 {
633 struct qreg t = qir_get_temp(c);
634 qir_emit(c, qir_inst(QOP_UNPACK_8A_I + i, t, src, c->undef));
635 return t;
636 }
637
638 static inline struct qreg
639 qir_UNPACK_16_F(struct vc4_compile *c, struct qreg src, int i)
640 {
641 struct qreg t = qir_get_temp(c);
642 qir_emit(c, qir_inst(QOP_UNPACK_16A_F + i, t, src, c->undef));
643 return t;
644 }
645
646 static inline struct qreg
647 qir_UNPACK_16_I(struct vc4_compile *c, struct qreg src, int i)
648 {
649 struct qreg t = qir_get_temp(c);
650 qir_emit(c, qir_inst(QOP_UNPACK_16A_I + i, t, src, c->undef));
651 return t;
652 }
653
654 static inline struct qreg
655 qir_PACK_8_F(struct vc4_compile *c, struct qreg dest, struct qreg val, int chan)
656 {
657 qir_emit(c, qir_inst(QOP_PACK_8A_F + chan, dest, val, c->undef));
658 if (dest.file == QFILE_TEMP)
659 c->defs[dest.index] = NULL;
660 return dest;
661 }
662
663 static inline struct qreg
664 qir_POW(struct vc4_compile *c, struct qreg x, struct qreg y)
665 {
666 return qir_EXP2(c, qir_FMUL(c,
667 y,
668 qir_LOG2(c, x)));
669 }
670
671 static inline void
672 qir_VPM_WRITE(struct vc4_compile *c, struct qreg val)
673 {
674 static const struct qreg vpm = { QFILE_VPM, 0 };
675 qir_emit(c, qir_inst(QOP_MOV, vpm, val, c->undef));
676 }
677
678 #endif /* VC4_QIR_H */