2 * Copyright © 2014 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
34 #include "util/macros.h"
35 #include "compiler/nir/nir.h"
36 #include "util/list.h"
37 #include "util/u_math.h"
39 #include "vc4_screen.h"
40 #include "vc4_qpu_defines.h"
42 #include "kernel/vc4_packet.h"
43 #include "pipe/p_state.h"
53 QFILE_TLB_COLOR_WRITE
,
54 QFILE_TLB_COLOR_WRITE_MS
,
56 QFILE_TLB_STENCIL_SETUP
,
58 /* Payload registers that aren't in the physical register file, so we
59 * can just use the corresponding qpu_reg at qpu_emit time.
66 * Stores an immediate value in the index field that will be used
67 * directly by qpu_load_imm().
72 * Stores an immediate value in the index field that can be turned
73 * into a small immediate field by qpu_encode_small_immediate().
84 static inline struct qreg
qir_reg(enum qfile file
, uint32_t index
)
86 return (struct qreg
){file
, index
};
134 /** Texture x coordinate parameter write */
136 /** Texture y coordinate parameter write */
138 /** Texture border color parameter or cube map z coordinate write */
140 /** Texture LOD bias parameter write */
144 * Texture-unit 4-byte read with address provided direct in S
147 * The first operand is the offset from the start of the UBO, and the
148 * second is the uniform that has the UBO's base pointer.
153 * Signal of texture read being necessary and then reading r4 into
160 /* Jumps to block->successor[0] if the qinst->cond (as a
161 * QPU_COND_BRANCH_*) passes, or block->successor[1] if not. Note
162 * that block->successor[1] may be unset if the condition is ALWAYS.
166 /* Emits an ADD from src[0] to src[1], where src[0] must be a
167 * QOP_LOAD_IMM result and src[1] is a QUNIFORM_UNIFORMS_ADDRESS,
168 * required by the kernel as part of its branch validation.
173 struct queued_qpu_inst
{
174 struct list_head link
;
179 struct list_head link
;
190 * Coordinate shader, runs during binning, before the VS, and just
198 enum quniform_contents
{
200 * Indicates that a constant 32-bit value is copied from the program's
205 * Indicates that the program's uniform contents are used as an index
206 * into the GL uniform storage.
211 * Scaling factors from clip coordinates to relative to the viewport
214 * This is used by the coordinate and vertex shaders to produce the
215 * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed
216 * point offsets from the viewport ccenter.
218 QUNIFORM_VIEWPORT_X_SCALE
,
219 QUNIFORM_VIEWPORT_Y_SCALE
,
222 QUNIFORM_VIEWPORT_Z_OFFSET
,
223 QUNIFORM_VIEWPORT_Z_SCALE
,
225 QUNIFORM_USER_CLIP_PLANE
,
228 * A reference to a texture config parameter 0 uniform.
230 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
231 * defines texture type, miplevels, and such. It will be found as a
232 * parameter to the first QOP_TEX_[STRB] instruction in a sequence.
234 QUNIFORM_TEXTURE_CONFIG_P0
,
237 * A reference to a texture config parameter 1 uniform.
239 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
240 * defines texture width, height, filters, and wrap modes. It will be
241 * found as a parameter to the second QOP_TEX_[STRB] instruction in a
244 QUNIFORM_TEXTURE_CONFIG_P1
,
246 /** A reference to a texture config parameter 2 cubemap stride uniform */
247 QUNIFORM_TEXTURE_CONFIG_P2
,
249 QUNIFORM_TEXTURE_FIRST_LEVEL
,
251 QUNIFORM_TEXTURE_MSAA_ADDR
,
255 QUNIFORM_TEXRECT_SCALE_X
,
256 QUNIFORM_TEXRECT_SCALE_Y
,
258 QUNIFORM_TEXTURE_BORDER_COLOR
,
260 QUNIFORM_BLEND_CONST_COLOR_X
,
261 QUNIFORM_BLEND_CONST_COLOR_Y
,
262 QUNIFORM_BLEND_CONST_COLOR_Z
,
263 QUNIFORM_BLEND_CONST_COLOR_W
,
264 QUNIFORM_BLEND_CONST_COLOR_RGBA
,
265 QUNIFORM_BLEND_CONST_COLOR_AAAA
,
270 QUNIFORM_SAMPLE_MASK
,
272 /* Placeholder uniform that will be updated by the kernel when used by
273 * an instruction writing to QPU_W_UNIFORMS_ADDRESS.
275 QUNIFORM_UNIFORMS_ADDRESS
,
278 struct vc4_varying_slot
{
283 struct vc4_compiler_ubo_range
{
285 * offset in bytes from the start of the ubo where this range is
288 * Only set once used is set.
293 * offset in bytes from the start of the gallium uniforms where the
298 /** size in bytes of this ubo range */
302 * Set if this range is used by the shader for indirect uniforms
309 struct vc4_uncompiled_shader
*shader_state
;
311 enum pipe_format format
;
315 unsigned compare_mode
:1;
316 unsigned compare_func
:3;
319 bool force_first_level
:1;
322 uint16_t msaa_width
, msaa_height
;
325 } tex
[VC4_MAX_TEXTURE_SAMPLERS
];
331 enum pipe_format color_format
;
333 bool stencil_enabled
;
334 bool stencil_twoside
;
335 bool stencil_full_writemasks
;
339 bool point_coord_upper_left
;
342 bool sample_coverage
;
343 bool sample_alpha_to_coverage
;
344 bool sample_alpha_to_one
;
345 uint8_t alpha_test_func
;
346 uint8_t logicop_func
;
347 uint32_t point_sprite_mask
;
349 struct pipe_rt_blend_state blend
;
355 const struct vc4_fs_inputs
*fs_inputs
;
356 enum pipe_format attr_formats
[8];
358 bool per_vertex_point_size
;
362 /** A basic block of QIR intructions. */
364 struct list_head link
;
366 struct list_head instructions
;
367 struct list_head qpu_inst_list
;
369 struct set
*predecessors
;
370 struct qblock
*successors
[2];
374 /* Instruction IPs for the first and last instruction of the block.
375 * Set by vc4_qpu_schedule.c.
377 uint32_t start_qpu_ip
;
380 /* Instruction IP for the branch instruction of the block. Set by
381 * vc4_qpu_schedule.c.
383 uint32_t branch_qpu_ip
;
385 /** @{ used by vc4_qir_live_variables.c */
388 BITSET_WORD
*live_in
;
389 BITSET_WORD
*live_out
;
390 int start_ip
, end_ip
;
395 struct vc4_context
*vc4
;
397 nir_function_impl
*impl
;
398 struct exec_list
*cf_node_list
;
401 * Mapping from nir_register * or nir_ssa_def * to array of struct
402 * qreg for the values.
404 struct hash_table
*def_ht
;
406 /* For each temp, the instruction generating its value. */
408 uint32_t defs_array_size
;
411 * Inputs to the shader, arranged by TGSI declaration order.
413 * Not all fragment shader QFILE_VARY reads are present in this array.
416 struct qreg
*outputs
;
417 bool msaa_per_sample_output
;
418 struct qreg color_reads
[VC4_MAX_SAMPLES
];
419 struct qreg sample_colors
[VC4_MAX_SAMPLES
];
420 uint32_t inputs_array_size
;
421 uint32_t outputs_array_size
;
422 uint32_t uniforms_array_size
;
424 struct vc4_compiler_ubo_range
*ubo_ranges
;
425 uint32_t ubo_ranges_array_size
;
426 /** Number of uniform areas declared in ubo_ranges. */
427 uint32_t num_uniform_ranges
;
428 /** Number of uniform areas used for indirect addressed loads. */
429 uint32_t num_ubo_ranges
;
430 uint32_t next_ubo_dst_offset
;
432 /* State for whether we're executing on each channel currently. 0 if
433 * yes, otherwise a block number + 1 that the channel jumped to.
437 struct qreg line_x
, point_x
, point_y
;
439 struct qreg payload_FRAG_Z
;
440 struct qreg payload_FRAG_W
;
442 uint8_t vattr_sizes
[8];
445 * Array of the VARYING_SLOT_* of all FS QFILE_VARY reads.
447 * This includes those that aren't part of the VPM varyings, like
448 * point/line coordinates.
450 struct vc4_varying_slot
*input_slots
;
451 uint32_t num_input_slots
;
452 uint32_t input_slots_array_size
;
455 * An entry per outputs[] in the VS indicating what the VARYING_SLOT_*
456 * of the output is. Used to emit from the VS in the order that the
459 struct vc4_varying_slot
*output_slots
;
461 struct pipe_shader_state
*shader_state
;
463 struct vc4_fs_key
*fs_key
;
464 struct vc4_vs_key
*vs_key
;
466 /* Live ranges of temps. */
467 int *temp_start
, *temp_end
;
469 uint32_t *uniform_data
;
470 enum quniform_contents
*uniform_contents
;
471 uint32_t uniform_array_size
;
472 uint32_t num_uniforms
;
473 uint32_t num_outputs
;
474 uint32_t num_texture_samples
;
475 uint32_t output_position_index
;
476 uint32_t output_color_index
;
477 uint32_t output_point_size_index
;
478 uint32_t output_sample_mask_index
;
484 struct list_head blocks
;
485 int next_block_index
;
486 struct qblock
*cur_block
;
487 struct qblock
*loop_cont_block
;
488 struct qblock
*loop_break_block
;
490 struct list_head qpu_inst_list
;
493 uint32_t qpu_inst_count
;
494 uint32_t qpu_inst_size
;
501 /* Special nir_load_input intrinsic index for loading the current TLB
504 #define VC4_NIR_TLB_COLOR_READ_INPUT 2000000000
506 #define VC4_NIR_MS_MASK_OUTPUT 2000000000
508 /* Special offset for nir_load_uniform values to get a QUNIFORM_*
509 * state-dependent value.
511 #define VC4_NIR_STATE_UNIFORM_OFFSET 1000000000
513 struct vc4_compile
*qir_compile_init(void);
514 void qir_compile_destroy(struct vc4_compile
*c
);
515 struct qblock
*qir_new_block(struct vc4_compile
*c
);
516 void qir_set_emit_block(struct vc4_compile
*c
, struct qblock
*block
);
517 void qir_link_blocks(struct qblock
*predecessor
, struct qblock
*successor
);
518 struct qblock
*qir_entry_block(struct vc4_compile
*c
);
519 struct qblock
*qir_exit_block(struct vc4_compile
*c
);
520 struct qinst
*qir_inst(enum qop op
, struct qreg dst
,
521 struct qreg src0
, struct qreg src1
);
522 struct qinst
*qir_inst4(enum qop op
, struct qreg dst
,
527 void qir_remove_instruction(struct vc4_compile
*c
, struct qinst
*qinst
);
528 struct qreg
qir_uniform(struct vc4_compile
*c
,
529 enum quniform_contents contents
,
531 void qir_schedule_instructions(struct vc4_compile
*c
);
532 void qir_reorder_uniforms(struct vc4_compile
*c
);
533 void qir_emit_uniform_stream_resets(struct vc4_compile
*c
);
535 struct qreg
qir_emit_def(struct vc4_compile
*c
, struct qinst
*inst
);
536 struct qinst
*qir_emit_nondef(struct vc4_compile
*c
, struct qinst
*inst
);
538 struct qreg
qir_get_temp(struct vc4_compile
*c
);
539 void qir_calculate_live_intervals(struct vc4_compile
*c
);
540 int qir_get_op_nsrc(enum qop qop
);
541 bool qir_reg_equals(struct qreg a
, struct qreg b
);
542 bool qir_has_side_effects(struct vc4_compile
*c
, struct qinst
*inst
);
543 bool qir_has_side_effect_reads(struct vc4_compile
*c
, struct qinst
*inst
);
544 bool qir_is_mul(struct qinst
*inst
);
545 bool qir_is_raw_mov(struct qinst
*inst
);
546 bool qir_is_tex(struct qinst
*inst
);
547 bool qir_is_float_input(struct qinst
*inst
);
548 bool qir_depends_on_flags(struct qinst
*inst
);
549 bool qir_writes_r4(struct qinst
*inst
);
550 struct qreg
qir_follow_movs(struct vc4_compile
*c
, struct qreg reg
);
551 uint8_t qir_channels_written(struct qinst
*inst
);
553 void qir_dump(struct vc4_compile
*c
);
554 void qir_dump_inst(struct vc4_compile
*c
, struct qinst
*inst
);
555 const char *qir_get_stage_name(enum qstage stage
);
557 void qir_validate(struct vc4_compile
*c
);
559 void qir_optimize(struct vc4_compile
*c
);
560 bool qir_opt_algebraic(struct vc4_compile
*c
);
561 bool qir_opt_constant_folding(struct vc4_compile
*c
);
562 bool qir_opt_copy_propagation(struct vc4_compile
*c
);
563 bool qir_opt_dead_code(struct vc4_compile
*c
);
564 bool qir_opt_peephole_sf(struct vc4_compile
*c
);
565 bool qir_opt_small_immediates(struct vc4_compile
*c
);
566 bool qir_opt_vpm(struct vc4_compile
*c
);
567 void vc4_nir_lower_blend(nir_shader
*s
, struct vc4_compile
*c
);
568 void vc4_nir_lower_io(nir_shader
*s
, struct vc4_compile
*c
);
569 nir_ssa_def
*vc4_nir_get_state_uniform(struct nir_builder
*b
,
570 enum quniform_contents contents
);
571 nir_ssa_def
*vc4_nir_get_swizzled_channel(struct nir_builder
*b
,
572 nir_ssa_def
**srcs
, int swiz
);
573 void vc4_nir_lower_txf_ms(nir_shader
*s
, struct vc4_compile
*c
);
574 void qir_lower_uniforms(struct vc4_compile
*c
);
576 uint32_t qpu_schedule_instructions(struct vc4_compile
*c
);
578 void qir_SF(struct vc4_compile
*c
, struct qreg src
);
580 static inline struct qreg
581 qir_uniform_ui(struct vc4_compile
*c
, uint32_t ui
)
583 return qir_uniform(c
, QUNIFORM_CONSTANT
, ui
);
586 static inline struct qreg
587 qir_uniform_f(struct vc4_compile
*c
, float f
)
589 return qir_uniform(c
, QUNIFORM_CONSTANT
, fui(f
));
592 #define QIR_ALU0(name) \
593 static inline struct qreg \
594 qir_##name(struct vc4_compile *c) \
596 return qir_emit_def(c, qir_inst(QOP_##name, c->undef, \
597 c->undef, c->undef)); \
599 static inline struct qinst * \
600 qir_##name##_dest(struct vc4_compile *c, struct qreg dest) \
602 return qir_emit_nondef(c, qir_inst(QOP_##name, dest, \
603 c->undef, c->undef)); \
606 #define QIR_ALU1(name) \
607 static inline struct qreg \
608 qir_##name(struct vc4_compile *c, struct qreg a) \
610 return qir_emit_def(c, qir_inst(QOP_##name, c->undef, \
613 static inline struct qinst * \
614 qir_##name##_dest(struct vc4_compile *c, struct qreg dest, \
617 return qir_emit_nondef(c, qir_inst(QOP_##name, dest, a, \
621 #define QIR_ALU2(name) \
622 static inline struct qreg \
623 qir_##name(struct vc4_compile *c, struct qreg a, struct qreg b) \
625 return qir_emit_def(c, qir_inst(QOP_##name, c->undef, a, b)); \
627 static inline struct qinst * \
628 qir_##name##_dest(struct vc4_compile *c, struct qreg dest, \
629 struct qreg a, struct qreg b) \
631 return qir_emit_nondef(c, qir_inst(QOP_##name, dest, a, b)); \
634 #define QIR_NODST_1(name) \
635 static inline struct qinst * \
636 qir_##name(struct vc4_compile *c, struct qreg a) \
638 return qir_emit_nondef(c, qir_inst(QOP_##name, c->undef, \
642 #define QIR_NODST_2(name) \
643 static inline struct qinst * \
644 qir_##name(struct vc4_compile *c, struct qreg a, struct qreg b) \
646 return qir_emit_nondef(c, qir_inst(QOP_##name, c->undef, \
650 #define QIR_PAYLOAD(name) \
651 static inline struct qreg \
652 qir_##name(struct vc4_compile *c) \
654 struct qreg *payload = &c->payload_##name; \
655 if (payload->file != QFILE_NULL) \
657 *payload = qir_get_temp(c); \
658 struct qinst *inst = qir_inst(QOP_##name, *payload, \
659 c->undef, c->undef); \
660 struct qblock *entry = qir_entry_block(c); \
661 list_add(&inst->link, &entry->instructions); \
662 c->defs[payload->index] = inst; \
706 QIR_NODST_2(TEX_DIRECT
)
710 QIR_ALU0(TLB_COLOR_READ
)
713 static inline struct qreg
714 qir_SEL(struct vc4_compile
*c
, uint8_t cond
, struct qreg src0
, struct qreg src1
)
716 struct qreg t
= qir_get_temp(c
);
717 struct qinst
*a
= qir_MOV_dest(c
, t
, src0
);
718 struct qinst
*b
= qir_MOV_dest(c
, t
, src1
);
720 b
->cond
= qpu_cond_complement(cond
);
724 static inline struct qreg
725 qir_UNPACK_8_F(struct vc4_compile
*c
, struct qreg src
, int i
)
727 struct qreg t
= qir_FMOV(c
, src
);
728 c
->defs
[t
.index
]->src
[0].pack
= QPU_UNPACK_8A
+ i
;
732 static inline struct qreg
733 qir_UNPACK_8_I(struct vc4_compile
*c
, struct qreg src
, int i
)
735 struct qreg t
= qir_MOV(c
, src
);
736 c
->defs
[t
.index
]->src
[0].pack
= QPU_UNPACK_8A
+ i
;
740 static inline struct qreg
741 qir_UNPACK_16_F(struct vc4_compile
*c
, struct qreg src
, int i
)
743 struct qreg t
= qir_FMOV(c
, src
);
744 c
->defs
[t
.index
]->src
[0].pack
= QPU_UNPACK_16A
+ i
;
748 static inline struct qreg
749 qir_UNPACK_16_I(struct vc4_compile
*c
, struct qreg src
, int i
)
751 struct qreg t
= qir_MOV(c
, src
);
752 c
->defs
[t
.index
]->src
[0].pack
= QPU_UNPACK_16A
+ i
;
757 qir_PACK_8_F(struct vc4_compile
*c
, struct qreg dest
, struct qreg val
, int chan
)
760 dest
.pack
= QPU_PACK_MUL_8A
+ chan
;
761 qir_emit_nondef(c
, qir_inst(QOP_MMOV
, dest
, val
, c
->undef
));
764 static inline struct qreg
765 qir_PACK_8888_F(struct vc4_compile
*c
, struct qreg val
)
767 struct qreg dest
= qir_MMOV(c
, val
);
768 c
->defs
[dest
.index
]->dst
.pack
= QPU_PACK_MUL_8888
;
772 static inline struct qreg
773 qir_POW(struct vc4_compile
*c
, struct qreg x
, struct qreg y
)
775 return qir_EXP2(c
, qir_FMUL(c
,
781 qir_VPM_WRITE(struct vc4_compile
*c
, struct qreg val
)
783 qir_MOV_dest(c
, qir_reg(QFILE_VPM
, 0), val
);
786 static inline struct qreg
787 qir_LOAD_IMM(struct vc4_compile
*c
, uint32_t val
)
789 return qir_emit_def(c
, qir_inst(QOP_LOAD_IMM
, c
->undef
,
790 qir_reg(QFILE_LOAD_IMM
, val
), c
->undef
));
794 qir_MOV_cond(struct vc4_compile
*c
, uint8_t cond
,
795 struct qreg dest
, struct qreg src
)
797 qir_MOV_dest(c
, dest
, src
)->cond
= cond
;
800 static inline struct qinst
*
801 qir_BRANCH(struct vc4_compile
*c
, uint8_t cond
)
803 struct qinst
*inst
= qir_inst(QOP_BRANCH
, c
->undef
, c
->undef
, c
->undef
);
805 qir_emit_nondef(c
, inst
);
809 #define qir_for_each_block(block, c) \
810 list_for_each_entry(struct qblock, block, &c->blocks, link)
812 #define qir_for_each_block_rev(block, c) \
813 list_for_each_entry_rev(struct qblock, block, &c->blocks, link)
815 /* Loop over the non-NULL members of the successors array. */
816 #define qir_for_each_successor(succ, block) \
817 for (struct qblock *succ = block->successors[0]; \
819 succ = (succ == block->successors[1] ? NULL : \
820 block->successors[1]))
822 #define qir_for_each_inst(inst, block) \
823 list_for_each_entry(struct qinst, inst, &block->instructions, link)
825 #define qir_for_each_inst_rev(inst, block) \
826 list_for_each_entry_rev(struct qinst, inst, &block->instructions, link)
828 #define qir_for_each_inst_safe(inst, block) \
829 list_for_each_entry_safe(struct qinst, inst, &block->instructions, link)
831 #define qir_for_each_inst_inorder(inst, c) \
832 qir_for_each_block(_block, c) \
833 qir_for_each_inst(inst, _block)
835 #endif /* VC4_QIR_H */