Merge remote-tracking branch 'mesa-public/master' into vulkan
[mesa.git] / src / gallium / drivers / vc4 / vc4_qir.h
1 /*
2 * Copyright © 2014 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef VC4_QIR_H
25 #define VC4_QIR_H
26
27 #include <assert.h>
28 #include <stdio.h>
29 #include <stdlib.h>
30 #include <stdbool.h>
31 #include <stdint.h>
32 #include <string.h>
33
34 #include "util/macros.h"
35 #include "glsl/nir/nir.h"
36 #include "util/list.h"
37 #include "util/u_math.h"
38
39 #include "vc4_screen.h"
40 #include "vc4_qpu_defines.h"
41 #include "pipe/p_state.h"
42
43 struct nir_builder;
44
45 enum qfile {
46 QFILE_NULL,
47 QFILE_TEMP,
48 QFILE_VARY,
49 QFILE_UNIF,
50 QFILE_VPM,
51
52 /**
53 * Stores an immediate value in the index field that can be turned
54 * into a small immediate field by qpu_encode_small_immediate().
55 */
56 QFILE_SMALL_IMM,
57 };
58
59 struct qreg {
60 enum qfile file;
61 uint32_t index;
62 int pack;
63 };
64
65 enum qop {
66 QOP_UNDEF,
67 QOP_MOV,
68 QOP_FMOV,
69 QOP_MMOV,
70 QOP_FADD,
71 QOP_FSUB,
72 QOP_FMUL,
73 QOP_V8MULD,
74 QOP_V8MIN,
75 QOP_V8MAX,
76 QOP_V8ADDS,
77 QOP_V8SUBS,
78 QOP_MUL24,
79 QOP_FMIN,
80 QOP_FMAX,
81 QOP_FMINABS,
82 QOP_FMAXABS,
83 QOP_ADD,
84 QOP_SUB,
85 QOP_SHL,
86 QOP_SHR,
87 QOP_ASR,
88 QOP_MIN,
89 QOP_MAX,
90 QOP_AND,
91 QOP_OR,
92 QOP_XOR,
93 QOP_NOT,
94
95 /* Note: Orderings of these compares must be the same as in
96 * qpu_defines.h. Selects the src[0] if the ns flag bit is set,
97 * otherwise 0. */
98 QOP_SEL_X_0_ZS,
99 QOP_SEL_X_0_ZC,
100 QOP_SEL_X_0_NS,
101 QOP_SEL_X_0_NC,
102 QOP_SEL_X_0_CS,
103 QOP_SEL_X_0_CC,
104 /* Selects the src[0] if the ns flag bit is set, otherwise src[1]. */
105 QOP_SEL_X_Y_ZS,
106 QOP_SEL_X_Y_ZC,
107 QOP_SEL_X_Y_NS,
108 QOP_SEL_X_Y_NC,
109 QOP_SEL_X_Y_CS,
110 QOP_SEL_X_Y_CC,
111
112 QOP_FTOI,
113 QOP_ITOF,
114 QOP_RCP,
115 QOP_RSQ,
116 QOP_EXP2,
117 QOP_LOG2,
118 QOP_VW_SETUP,
119 QOP_VR_SETUP,
120 QOP_TLB_DISCARD_SETUP,
121 QOP_TLB_STENCIL_SETUP,
122 QOP_TLB_Z_WRITE,
123 QOP_TLB_COLOR_WRITE,
124 QOP_TLB_COLOR_READ,
125 QOP_VARY_ADD_C,
126
127 QOP_FRAG_X,
128 QOP_FRAG_Y,
129 QOP_FRAG_Z,
130 QOP_FRAG_W,
131 QOP_FRAG_REV_FLAG,
132
133 /** Texture x coordinate parameter write */
134 QOP_TEX_S,
135 /** Texture y coordinate parameter write */
136 QOP_TEX_T,
137 /** Texture border color parameter or cube map z coordinate write */
138 QOP_TEX_R,
139 /** Texture LOD bias parameter write */
140 QOP_TEX_B,
141
142 /**
143 * Texture-unit 4-byte read with address provided direct in S
144 * cooordinate.
145 *
146 * The first operand is the offset from the start of the UBO, and the
147 * second is the uniform that has the UBO's base pointer.
148 */
149 QOP_TEX_DIRECT,
150
151 /**
152 * Signal of texture read being necessary and then reading r4 into
153 * the destination
154 */
155 QOP_TEX_RESULT,
156 };
157
158 struct queued_qpu_inst {
159 struct list_head link;
160 uint64_t inst;
161 };
162
163 struct qinst {
164 struct list_head link;
165
166 enum qop op;
167 struct qreg dst;
168 struct qreg *src;
169 bool sf;
170 };
171
172 enum qstage {
173 /**
174 * Coordinate shader, runs during binning, before the VS, and just
175 * outputs position.
176 */
177 QSTAGE_COORD,
178 QSTAGE_VERT,
179 QSTAGE_FRAG,
180 };
181
182 enum quniform_contents {
183 /**
184 * Indicates that a constant 32-bit value is copied from the program's
185 * uniform contents.
186 */
187 QUNIFORM_CONSTANT,
188 /**
189 * Indicates that the program's uniform contents are used as an index
190 * into the GL uniform storage.
191 */
192 QUNIFORM_UNIFORM,
193
194 /** @{
195 * Scaling factors from clip coordinates to relative to the viewport
196 * center.
197 *
198 * This is used by the coordinate and vertex shaders to produce the
199 * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed
200 * point offsets from the viewport ccenter.
201 */
202 QUNIFORM_VIEWPORT_X_SCALE,
203 QUNIFORM_VIEWPORT_Y_SCALE,
204 /** @} */
205
206 QUNIFORM_VIEWPORT_Z_OFFSET,
207 QUNIFORM_VIEWPORT_Z_SCALE,
208
209 QUNIFORM_USER_CLIP_PLANE,
210
211 /**
212 * A reference to a texture config parameter 0 uniform.
213 *
214 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
215 * defines texture type, miplevels, and such. It will be found as a
216 * parameter to the first QOP_TEX_[STRB] instruction in a sequence.
217 */
218 QUNIFORM_TEXTURE_CONFIG_P0,
219
220 /**
221 * A reference to a texture config parameter 1 uniform.
222 *
223 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
224 * defines texture width, height, filters, and wrap modes. It will be
225 * found as a parameter to the second QOP_TEX_[STRB] instruction in a
226 * sequence.
227 */
228 QUNIFORM_TEXTURE_CONFIG_P1,
229
230 /** A reference to a texture config parameter 2 cubemap stride uniform */
231 QUNIFORM_TEXTURE_CONFIG_P2,
232
233 QUNIFORM_UBO_ADDR,
234
235 QUNIFORM_TEXRECT_SCALE_X,
236 QUNIFORM_TEXRECT_SCALE_Y,
237
238 QUNIFORM_TEXTURE_BORDER_COLOR,
239
240 QUNIFORM_BLEND_CONST_COLOR_X,
241 QUNIFORM_BLEND_CONST_COLOR_Y,
242 QUNIFORM_BLEND_CONST_COLOR_Z,
243 QUNIFORM_BLEND_CONST_COLOR_W,
244 QUNIFORM_BLEND_CONST_COLOR_RGBA,
245 QUNIFORM_BLEND_CONST_COLOR_AAAA,
246
247 QUNIFORM_STENCIL,
248
249 QUNIFORM_ALPHA_REF,
250 };
251
252 struct vc4_varying_slot {
253 uint8_t slot;
254 uint8_t swizzle;
255 };
256
257 struct vc4_compiler_ubo_range {
258 /**
259 * offset in bytes from the start of the ubo where this range is
260 * uploaded.
261 *
262 * Only set once used is set.
263 */
264 uint32_t dst_offset;
265
266 /**
267 * offset in bytes from the start of the gallium uniforms where the
268 * data comes from.
269 */
270 uint32_t src_offset;
271
272 /** size in bytes of this ubo range */
273 uint32_t size;
274
275 /**
276 * Set if this range is used by the shader for indirect uniforms
277 * access.
278 */
279 bool used;
280 };
281
282 struct vc4_key {
283 struct vc4_uncompiled_shader *shader_state;
284 struct {
285 enum pipe_format format;
286 unsigned compare_mode:1;
287 unsigned compare_func:3;
288 unsigned wrap_s:3;
289 unsigned wrap_t:3;
290 uint8_t swizzle[4];
291 } tex[VC4_MAX_TEXTURE_SAMPLERS];
292 uint8_t ucp_enables;
293 };
294
295 struct vc4_fs_key {
296 struct vc4_key base;
297 enum pipe_format color_format;
298 bool depth_enabled;
299 bool stencil_enabled;
300 bool stencil_twoside;
301 bool stencil_full_writemasks;
302 bool is_points;
303 bool is_lines;
304 bool alpha_test;
305 bool point_coord_upper_left;
306 bool light_twoside;
307 uint8_t alpha_test_func;
308 uint8_t logicop_func;
309 uint32_t point_sprite_mask;
310
311 struct pipe_rt_blend_state blend;
312 };
313
314 struct vc4_vs_key {
315 struct vc4_key base;
316
317 /**
318 * This is a proxy for the array of FS input semantics, which is
319 * larger than we would want to put in the key.
320 */
321 uint64_t compiled_fs_id;
322
323 enum pipe_format attr_formats[8];
324 bool is_coord;
325 bool per_vertex_point_size;
326 };
327
328 struct vc4_compile {
329 struct vc4_context *vc4;
330 nir_shader *s;
331 nir_function_impl *impl;
332 struct exec_list *cf_node_list;
333
334 /**
335 * Mapping from nir_register * or nir_ssa_def * to array of struct
336 * qreg for the values.
337 */
338 struct hash_table *def_ht;
339
340 /* For each temp, the instruction generating its value. */
341 struct qinst **defs;
342 uint32_t defs_array_size;
343
344 /**
345 * Inputs to the shader, arranged by TGSI declaration order.
346 *
347 * Not all fragment shader QFILE_VARY reads are present in this array.
348 */
349 struct qreg *inputs;
350 struct qreg *outputs;
351 uint32_t inputs_array_size;
352 uint32_t outputs_array_size;
353 uint32_t uniforms_array_size;
354
355 struct vc4_compiler_ubo_range *ubo_ranges;
356 uint32_t ubo_ranges_array_size;
357 /** Number of uniform areas declared in ubo_ranges. */
358 uint32_t num_uniform_ranges;
359 /** Number of uniform areas used for indirect addressed loads. */
360 uint32_t num_ubo_ranges;
361 uint32_t next_ubo_dst_offset;
362
363 struct qreg line_x, point_x, point_y;
364 struct qreg discard;
365
366 uint8_t vattr_sizes[8];
367
368 /**
369 * Array of the VARYING_SLOT_* of all FS QFILE_VARY reads.
370 *
371 * This includes those that aren't part of the VPM varyings, like
372 * point/line coordinates.
373 */
374 struct vc4_varying_slot *input_slots;
375 uint32_t num_input_slots;
376 uint32_t input_slots_array_size;
377
378 /**
379 * An entry per outputs[] in the VS indicating what the VARYING_SLOT_*
380 * of the output is. Used to emit from the VS in the order that the
381 * FS needs.
382 */
383 struct vc4_varying_slot *output_slots;
384
385 struct pipe_shader_state *shader_state;
386 struct vc4_key *key;
387 struct vc4_fs_key *fs_key;
388 struct vc4_vs_key *vs_key;
389
390 uint32_t *uniform_data;
391 enum quniform_contents *uniform_contents;
392 uint32_t uniform_array_size;
393 uint32_t num_uniforms;
394 uint32_t num_outputs;
395 uint32_t num_texture_samples;
396 uint32_t output_position_index;
397 uint32_t output_color_index;
398 uint32_t output_point_size_index;
399
400 struct qreg undef;
401 enum qstage stage;
402 uint32_t num_temps;
403 struct list_head instructions;
404 uint32_t immediates[1024];
405
406 struct list_head qpu_inst_list;
407 uint64_t *qpu_insts;
408 uint32_t qpu_inst_count;
409 uint32_t qpu_inst_size;
410 uint32_t num_inputs;
411
412 uint32_t program_id;
413 uint32_t variant_id;
414 };
415
416 /* Special nir_load_input intrinsic index for loading the current TLB
417 * destination color.
418 */
419 #define VC4_NIR_TLB_COLOR_READ_INPUT 2000000000
420
421 /* Special offset for nir_load_uniform values to get a QUNIFORM_*
422 * state-dependent value.
423 */
424 #define VC4_NIR_STATE_UNIFORM_OFFSET 2000000000
425
426 struct vc4_compile *qir_compile_init(void);
427 void qir_compile_destroy(struct vc4_compile *c);
428 struct qinst *qir_inst(enum qop op, struct qreg dst,
429 struct qreg src0, struct qreg src1);
430 struct qinst *qir_inst4(enum qop op, struct qreg dst,
431 struct qreg a,
432 struct qreg b,
433 struct qreg c,
434 struct qreg d);
435 void qir_remove_instruction(struct vc4_compile *c, struct qinst *qinst);
436 struct qreg qir_uniform(struct vc4_compile *c,
437 enum quniform_contents contents,
438 uint32_t data);
439 void qir_reorder_uniforms(struct vc4_compile *c);
440
441 void qir_emit(struct vc4_compile *c, struct qinst *inst);
442 static inline void qir_emit_nodef(struct vc4_compile *c, struct qinst *inst)
443 {
444 list_addtail(&inst->link, &c->instructions);
445 }
446
447 struct qreg qir_get_temp(struct vc4_compile *c);
448 int qir_get_op_nsrc(enum qop qop);
449 bool qir_reg_equals(struct qreg a, struct qreg b);
450 bool qir_has_side_effects(struct vc4_compile *c, struct qinst *inst);
451 bool qir_has_side_effect_reads(struct vc4_compile *c, struct qinst *inst);
452 bool qir_is_multi_instruction(struct qinst *inst);
453 bool qir_is_mul(struct qinst *inst);
454 bool qir_is_raw_mov(struct qinst *inst);
455 bool qir_is_tex(struct qinst *inst);
456 bool qir_is_float_input(struct qinst *inst);
457 bool qir_depends_on_flags(struct qinst *inst);
458 bool qir_writes_r4(struct qinst *inst);
459 struct qreg qir_follow_movs(struct vc4_compile *c, struct qreg reg);
460
461 void qir_dump(struct vc4_compile *c);
462 void qir_dump_inst(struct vc4_compile *c, struct qinst *inst);
463 const char *qir_get_stage_name(enum qstage stage);
464
465 void qir_optimize(struct vc4_compile *c);
466 bool qir_opt_algebraic(struct vc4_compile *c);
467 bool qir_opt_constant_folding(struct vc4_compile *c);
468 bool qir_opt_copy_propagation(struct vc4_compile *c);
469 bool qir_opt_cse(struct vc4_compile *c);
470 bool qir_opt_dead_code(struct vc4_compile *c);
471 bool qir_opt_small_immediates(struct vc4_compile *c);
472 bool qir_opt_vpm_writes(struct vc4_compile *c);
473 void vc4_nir_lower_blend(struct vc4_compile *c);
474 void vc4_nir_lower_io(struct vc4_compile *c);
475 nir_ssa_def *vc4_nir_get_state_uniform(struct nir_builder *b,
476 enum quniform_contents contents);
477 nir_ssa_def *vc4_nir_get_swizzled_channel(struct nir_builder *b,
478 nir_ssa_def **srcs, int swiz);
479 void qir_lower_uniforms(struct vc4_compile *c);
480
481 void qpu_schedule_instructions(struct vc4_compile *c);
482
483 void qir_SF(struct vc4_compile *c, struct qreg src);
484
485 static inline struct qreg
486 qir_uniform_ui(struct vc4_compile *c, uint32_t ui)
487 {
488 return qir_uniform(c, QUNIFORM_CONSTANT, ui);
489 }
490
491 static inline struct qreg
492 qir_uniform_f(struct vc4_compile *c, float f)
493 {
494 return qir_uniform(c, QUNIFORM_CONSTANT, fui(f));
495 }
496
497 #define QIR_ALU0(name) \
498 static inline struct qreg \
499 qir_##name(struct vc4_compile *c) \
500 { \
501 struct qreg t = qir_get_temp(c); \
502 qir_emit(c, qir_inst(QOP_##name, t, c->undef, c->undef)); \
503 return t; \
504 }
505
506 #define QIR_ALU1(name) \
507 static inline struct qreg \
508 qir_##name(struct vc4_compile *c, struct qreg a) \
509 { \
510 struct qreg t = qir_get_temp(c); \
511 qir_emit(c, qir_inst(QOP_##name, t, a, c->undef)); \
512 return t; \
513 } \
514 static inline void \
515 qir_##name##_dest(struct vc4_compile *c, struct qreg dest, \
516 struct qreg a) \
517 { \
518 qir_emit_nodef(c, qir_inst(QOP_##name, dest, a, c->undef)); \
519 }
520
521 #define QIR_ALU2(name) \
522 static inline struct qreg \
523 qir_##name(struct vc4_compile *c, struct qreg a, struct qreg b) \
524 { \
525 struct qreg t = qir_get_temp(c); \
526 qir_emit(c, qir_inst(QOP_##name, t, a, b)); \
527 return t; \
528 } \
529 static inline void \
530 qir_##name##_dest(struct vc4_compile *c, struct qreg dest, \
531 struct qreg a, struct qreg b) \
532 { \
533 qir_emit_nodef(c, qir_inst(QOP_##name, dest, a, b)); \
534 }
535
536 #define QIR_NODST_1(name) \
537 static inline void \
538 qir_##name(struct vc4_compile *c, struct qreg a) \
539 { \
540 qir_emit(c, qir_inst(QOP_##name, c->undef, a, c->undef)); \
541 }
542
543 #define QIR_NODST_2(name) \
544 static inline void \
545 qir_##name(struct vc4_compile *c, struct qreg a, struct qreg b) \
546 { \
547 qir_emit(c, qir_inst(QOP_##name, c->undef, a, b)); \
548 }
549
550 #define QIR_PACK(name) \
551 static inline struct qreg \
552 qir_##name(struct vc4_compile *c, struct qreg dest, struct qreg a) \
553 { \
554 qir_emit_nodef(c, qir_inst(QOP_##name, dest, a, c->undef)); \
555 return dest; \
556 }
557
558 QIR_ALU1(MOV)
559 QIR_ALU1(FMOV)
560 QIR_ALU1(MMOV)
561 QIR_ALU2(FADD)
562 QIR_ALU2(FSUB)
563 QIR_ALU2(FMUL)
564 QIR_ALU2(V8MULD)
565 QIR_ALU2(V8MIN)
566 QIR_ALU2(V8MAX)
567 QIR_ALU2(V8ADDS)
568 QIR_ALU2(V8SUBS)
569 QIR_ALU2(MUL24)
570 QIR_ALU1(SEL_X_0_ZS)
571 QIR_ALU1(SEL_X_0_ZC)
572 QIR_ALU1(SEL_X_0_NS)
573 QIR_ALU1(SEL_X_0_NC)
574 QIR_ALU1(SEL_X_0_CS)
575 QIR_ALU1(SEL_X_0_CC)
576 QIR_ALU2(SEL_X_Y_ZS)
577 QIR_ALU2(SEL_X_Y_ZC)
578 QIR_ALU2(SEL_X_Y_NS)
579 QIR_ALU2(SEL_X_Y_NC)
580 QIR_ALU2(SEL_X_Y_CS)
581 QIR_ALU2(SEL_X_Y_CC)
582 QIR_ALU2(FMIN)
583 QIR_ALU2(FMAX)
584 QIR_ALU2(FMINABS)
585 QIR_ALU2(FMAXABS)
586 QIR_ALU1(FTOI)
587 QIR_ALU1(ITOF)
588
589 QIR_ALU2(ADD)
590 QIR_ALU2(SUB)
591 QIR_ALU2(SHL)
592 QIR_ALU2(SHR)
593 QIR_ALU2(ASR)
594 QIR_ALU2(MIN)
595 QIR_ALU2(MAX)
596 QIR_ALU2(AND)
597 QIR_ALU2(OR)
598 QIR_ALU2(XOR)
599 QIR_ALU1(NOT)
600
601 QIR_ALU1(RCP)
602 QIR_ALU1(RSQ)
603 QIR_ALU1(EXP2)
604 QIR_ALU1(LOG2)
605 QIR_ALU1(VARY_ADD_C)
606 QIR_NODST_2(TEX_S)
607 QIR_NODST_2(TEX_T)
608 QIR_NODST_2(TEX_R)
609 QIR_NODST_2(TEX_B)
610 QIR_NODST_2(TEX_DIRECT)
611 QIR_ALU0(FRAG_X)
612 QIR_ALU0(FRAG_Y)
613 QIR_ALU0(FRAG_Z)
614 QIR_ALU0(FRAG_W)
615 QIR_ALU0(FRAG_REV_FLAG)
616 QIR_ALU0(TEX_RESULT)
617 QIR_ALU0(TLB_COLOR_READ)
618 QIR_NODST_1(TLB_COLOR_WRITE)
619 QIR_NODST_1(TLB_Z_WRITE)
620 QIR_NODST_1(TLB_DISCARD_SETUP)
621 QIR_NODST_1(TLB_STENCIL_SETUP)
622
623 static inline struct qreg
624 qir_UNPACK_8_F(struct vc4_compile *c, struct qreg src, int i)
625 {
626 struct qreg t = qir_FMOV(c, src);
627 c->defs[t.index]->src[0].pack = QPU_UNPACK_8A + i;
628 return t;
629 }
630
631 static inline struct qreg
632 qir_UNPACK_8_I(struct vc4_compile *c, struct qreg src, int i)
633 {
634 struct qreg t = qir_MOV(c, src);
635 c->defs[t.index]->src[0].pack = QPU_UNPACK_8A + i;
636 return t;
637 }
638
639 static inline struct qreg
640 qir_UNPACK_16_F(struct vc4_compile *c, struct qreg src, int i)
641 {
642 struct qreg t = qir_FMOV(c, src);
643 c->defs[t.index]->src[0].pack = QPU_UNPACK_16A + i;
644 return t;
645 }
646
647 static inline struct qreg
648 qir_UNPACK_16_I(struct vc4_compile *c, struct qreg src, int i)
649 {
650 struct qreg t = qir_MOV(c, src);
651 c->defs[t.index]->src[0].pack = QPU_UNPACK_16A + i;
652 return t;
653 }
654
655 static inline void
656 qir_PACK_8_F(struct vc4_compile *c, struct qreg dest, struct qreg val, int chan)
657 {
658 assert(!dest.pack);
659 dest.pack = QPU_PACK_MUL_8A + chan;
660 qir_emit(c, qir_inst(QOP_MMOV, dest, val, c->undef));
661 if (dest.file == QFILE_TEMP)
662 c->defs[dest.index] = NULL;
663 }
664
665 static inline struct qreg
666 qir_PACK_8888_F(struct vc4_compile *c, struct qreg val)
667 {
668 struct qreg dest = qir_MMOV(c, val);
669 c->defs[dest.index]->dst.pack = QPU_PACK_MUL_8888;
670 return dest;
671 }
672
673 static inline struct qreg
674 qir_POW(struct vc4_compile *c, struct qreg x, struct qreg y)
675 {
676 return qir_EXP2(c, qir_FMUL(c,
677 y,
678 qir_LOG2(c, x)));
679 }
680
681 static inline void
682 qir_VPM_WRITE(struct vc4_compile *c, struct qreg val)
683 {
684 static const struct qreg vpm = { QFILE_VPM, 0 };
685 qir_emit(c, qir_inst(QOP_MOV, vpm, val, c->undef));
686 }
687
688 #endif /* VC4_QIR_H */