vc4: Add a helper for making driver-specific NIR load_uniform for GL state
[mesa.git] / src / gallium / drivers / vc4 / vc4_qir.h
1 /*
2 * Copyright © 2014 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef VC4_QIR_H
25 #define VC4_QIR_H
26
27 #include <assert.h>
28 #include <stdio.h>
29 #include <stdlib.h>
30 #include <stdbool.h>
31 #include <stdint.h>
32 #include <string.h>
33
34 #include "util/macros.h"
35 #include "glsl/nir/nir.h"
36 #include "util/list.h"
37 #include "util/u_math.h"
38
39 #include "vc4_screen.h"
40 #include "pipe/p_state.h"
41
42 enum qfile {
43 QFILE_NULL,
44 QFILE_TEMP,
45 QFILE_VARY,
46 QFILE_UNIF,
47 QFILE_VPM,
48
49 /**
50 * Stores an immediate value in the index field that can be turned
51 * into a small immediate field by qpu_encode_small_immediate().
52 */
53 QFILE_SMALL_IMM,
54 };
55
56 struct qreg {
57 enum qfile file;
58 uint32_t index;
59 };
60
61 enum qop {
62 QOP_UNDEF,
63 QOP_MOV,
64 QOP_FADD,
65 QOP_FSUB,
66 QOP_FMUL,
67 QOP_MUL24,
68 QOP_FMIN,
69 QOP_FMAX,
70 QOP_FMINABS,
71 QOP_FMAXABS,
72 QOP_ADD,
73 QOP_SUB,
74 QOP_SHL,
75 QOP_SHR,
76 QOP_ASR,
77 QOP_MIN,
78 QOP_MAX,
79 QOP_AND,
80 QOP_OR,
81 QOP_XOR,
82 QOP_NOT,
83
84 /* Note: Orderings of these compares must be the same as in
85 * qpu_defines.h. Selects the src[0] if the ns flag bit is set,
86 * otherwise 0. */
87 QOP_SEL_X_0_ZS,
88 QOP_SEL_X_0_ZC,
89 QOP_SEL_X_0_NS,
90 QOP_SEL_X_0_NC,
91 /* Selects the src[0] if the ns flag bit is set, otherwise src[1]. */
92 QOP_SEL_X_Y_ZS,
93 QOP_SEL_X_Y_ZC,
94 QOP_SEL_X_Y_NS,
95 QOP_SEL_X_Y_NC,
96
97 QOP_FTOI,
98 QOP_ITOF,
99 QOP_RCP,
100 QOP_RSQ,
101 QOP_EXP2,
102 QOP_LOG2,
103 QOP_VW_SETUP,
104 QOP_VR_SETUP,
105 QOP_PACK_SCALED,
106 QOP_PACK_8888_F,
107 QOP_PACK_8A_F,
108 QOP_PACK_8B_F,
109 QOP_PACK_8C_F,
110 QOP_PACK_8D_F,
111 QOP_TLB_DISCARD_SETUP,
112 QOP_TLB_STENCIL_SETUP,
113 QOP_TLB_Z_WRITE,
114 QOP_TLB_COLOR_WRITE,
115 QOP_TLB_COLOR_READ,
116 QOP_VARY_ADD_C,
117
118 QOP_FRAG_X,
119 QOP_FRAG_Y,
120 QOP_FRAG_Z,
121 QOP_FRAG_W,
122 QOP_FRAG_REV_FLAG,
123
124 QOP_UNPACK_8A_F,
125 QOP_UNPACK_8B_F,
126 QOP_UNPACK_8C_F,
127 QOP_UNPACK_8D_F,
128 QOP_UNPACK_16A_F,
129 QOP_UNPACK_16B_F,
130
131 QOP_UNPACK_8A_I,
132 QOP_UNPACK_8B_I,
133 QOP_UNPACK_8C_I,
134 QOP_UNPACK_8D_I,
135 QOP_UNPACK_16A_I,
136 QOP_UNPACK_16B_I,
137
138 /** Texture x coordinate parameter write */
139 QOP_TEX_S,
140 /** Texture y coordinate parameter write */
141 QOP_TEX_T,
142 /** Texture border color parameter or cube map z coordinate write */
143 QOP_TEX_R,
144 /** Texture LOD bias parameter write */
145 QOP_TEX_B,
146
147 /**
148 * Texture-unit 4-byte read with address provided direct in S
149 * cooordinate.
150 *
151 * The first operand is the offset from the start of the UBO, and the
152 * second is the uniform that has the UBO's base pointer.
153 */
154 QOP_TEX_DIRECT,
155
156 /**
157 * Signal of texture read being necessary and then reading r4 into
158 * the destination
159 */
160 QOP_TEX_RESULT,
161 };
162
163 struct queued_qpu_inst {
164 struct list_head link;
165 uint64_t inst;
166 };
167
168 struct qinst {
169 struct list_head link;
170
171 enum qop op;
172 struct qreg dst;
173 struct qreg *src;
174 bool sf;
175 };
176
177 enum qstage {
178 /**
179 * Coordinate shader, runs during binning, before the VS, and just
180 * outputs position.
181 */
182 QSTAGE_COORD,
183 QSTAGE_VERT,
184 QSTAGE_FRAG,
185 };
186
187 enum quniform_contents {
188 /**
189 * Indicates that a constant 32-bit value is copied from the program's
190 * uniform contents.
191 */
192 QUNIFORM_CONSTANT,
193 /**
194 * Indicates that the program's uniform contents are used as an index
195 * into the GL uniform storage.
196 */
197 QUNIFORM_UNIFORM,
198
199 /** @{
200 * Scaling factors from clip coordinates to relative to the viewport
201 * center.
202 *
203 * This is used by the coordinate and vertex shaders to produce the
204 * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed
205 * point offsets from the viewport ccenter.
206 */
207 QUNIFORM_VIEWPORT_X_SCALE,
208 QUNIFORM_VIEWPORT_Y_SCALE,
209 /** @} */
210
211 QUNIFORM_VIEWPORT_Z_OFFSET,
212 QUNIFORM_VIEWPORT_Z_SCALE,
213
214 QUNIFORM_USER_CLIP_PLANE,
215
216 /**
217 * A reference to a texture config parameter 0 uniform.
218 *
219 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
220 * defines texture type, miplevels, and such. It will be found as a
221 * parameter to the first QOP_TEX_[STRB] instruction in a sequence.
222 */
223 QUNIFORM_TEXTURE_CONFIG_P0,
224
225 /**
226 * A reference to a texture config parameter 1 uniform.
227 *
228 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
229 * defines texture width, height, filters, and wrap modes. It will be
230 * found as a parameter to the second QOP_TEX_[STRB] instruction in a
231 * sequence.
232 */
233 QUNIFORM_TEXTURE_CONFIG_P1,
234
235 /** A reference to a texture config parameter 2 cubemap stride uniform */
236 QUNIFORM_TEXTURE_CONFIG_P2,
237
238 QUNIFORM_UBO_ADDR,
239
240 QUNIFORM_TEXRECT_SCALE_X,
241 QUNIFORM_TEXRECT_SCALE_Y,
242
243 QUNIFORM_TEXTURE_BORDER_COLOR,
244
245 QUNIFORM_BLEND_CONST_COLOR,
246 QUNIFORM_STENCIL,
247
248 QUNIFORM_ALPHA_REF,
249 };
250
251 struct vc4_varying_semantic {
252 uint8_t semantic;
253 uint8_t index;
254 uint8_t swizzle;
255 };
256
257 struct vc4_compiler_ubo_range {
258 /**
259 * offset in bytes from the start of the ubo where this range is
260 * uploaded.
261 *
262 * Only set once used is set.
263 */
264 uint32_t dst_offset;
265
266 /**
267 * offset in bytes from the start of the gallium uniforms where the
268 * data comes from.
269 */
270 uint32_t src_offset;
271
272 /** size in bytes of this ubo range */
273 uint32_t size;
274
275 /**
276 * Set if this range is used by the shader for indirect uniforms
277 * access.
278 */
279 bool used;
280 };
281
282 struct vc4_key {
283 struct vc4_uncompiled_shader *shader_state;
284 struct {
285 enum pipe_format format;
286 unsigned compare_mode:1;
287 unsigned compare_func:3;
288 unsigned wrap_s:3;
289 unsigned wrap_t:3;
290 uint8_t swizzle[4];
291 } tex[VC4_MAX_TEXTURE_SAMPLERS];
292 uint8_t ucp_enables;
293 };
294
295 struct vc4_fs_key {
296 struct vc4_key base;
297 enum pipe_format color_format;
298 bool depth_enabled;
299 bool stencil_enabled;
300 bool stencil_twoside;
301 bool stencil_full_writemasks;
302 bool is_points;
303 bool is_lines;
304 bool alpha_test;
305 bool point_coord_upper_left;
306 bool light_twoside;
307 uint8_t alpha_test_func;
308 uint8_t logicop_func;
309 uint32_t point_sprite_mask;
310
311 struct pipe_rt_blend_state blend;
312 };
313
314 struct vc4_vs_key {
315 struct vc4_key base;
316
317 /**
318 * This is a proxy for the array of FS input semantics, which is
319 * larger than we would want to put in the key.
320 */
321 uint64_t compiled_fs_id;
322
323 enum pipe_format attr_formats[8];
324 bool is_coord;
325 bool per_vertex_point_size;
326 };
327
328 struct vc4_compile {
329 struct vc4_context *vc4;
330 nir_shader *s;
331 nir_function_impl *impl;
332 struct exec_list *cf_node_list;
333
334 /**
335 * Mapping from nir_register * or nir_ssa_def * to array of struct
336 * qreg for the values.
337 */
338 struct hash_table *def_ht;
339
340 /* For each temp, the instruction generating its value. */
341 struct qinst **defs;
342 uint32_t defs_array_size;
343
344 /**
345 * Inputs to the shader, arranged by TGSI declaration order.
346 *
347 * Not all fragment shader QFILE_VARY reads are present in this array.
348 */
349 struct qreg *inputs;
350 struct qreg *outputs;
351 uint32_t inputs_array_size;
352 uint32_t outputs_array_size;
353 uint32_t uniforms_array_size;
354
355 struct vc4_compiler_ubo_range *ubo_ranges;
356 uint32_t ubo_ranges_array_size;
357 /** Number of uniform areas declared in ubo_ranges. */
358 uint32_t num_uniform_ranges;
359 /** Number of uniform areas used for indirect addressed loads. */
360 uint32_t num_ubo_ranges;
361 uint32_t next_ubo_dst_offset;
362
363 struct qreg line_x, point_x, point_y;
364 struct qreg discard;
365
366 uint8_t vattr_sizes[8];
367
368 /**
369 * Array of the TGSI semantics of all FS QFILE_VARY reads.
370 *
371 * This includes those that aren't part of the VPM varyings, like
372 * point/line coordinates.
373 */
374 struct vc4_varying_semantic *input_semantics;
375 uint32_t num_input_semantics;
376 uint32_t input_semantics_array_size;
377
378 /**
379 * An entry per outputs[] in the VS indicating what the semantic of
380 * the output is. Used to emit from the VS in the order that the FS
381 * needs.
382 */
383 struct vc4_varying_semantic *output_semantics;
384
385 struct pipe_shader_state *shader_state;
386 struct vc4_key *key;
387 struct vc4_fs_key *fs_key;
388 struct vc4_vs_key *vs_key;
389
390 uint32_t *uniform_data;
391 enum quniform_contents *uniform_contents;
392 uint32_t uniform_array_size;
393 uint32_t num_uniforms;
394 uint32_t num_outputs;
395 uint32_t num_texture_samples;
396 uint32_t output_position_index;
397 uint32_t output_clipvertex_index;
398 uint32_t output_color_index;
399 uint32_t output_point_size_index;
400
401 struct qreg undef;
402 enum qstage stage;
403 uint32_t num_temps;
404 struct list_head instructions;
405 uint32_t immediates[1024];
406
407 struct list_head qpu_inst_list;
408 uint64_t *qpu_insts;
409 uint32_t qpu_inst_count;
410 uint32_t qpu_inst_size;
411 uint32_t num_inputs;
412
413 uint32_t program_id;
414 uint32_t variant_id;
415 };
416
417 /* Special offset for nir_load_uniform values to get a QUNIFORM_*
418 * state-dependent value.
419 */
420 #define VC4_NIR_STATE_UNIFORM_OFFSET 2000000000
421
422 struct vc4_compile *qir_compile_init(void);
423 void qir_compile_destroy(struct vc4_compile *c);
424 struct qinst *qir_inst(enum qop op, struct qreg dst,
425 struct qreg src0, struct qreg src1);
426 struct qinst *qir_inst4(enum qop op, struct qreg dst,
427 struct qreg a,
428 struct qreg b,
429 struct qreg c,
430 struct qreg d);
431 void qir_remove_instruction(struct vc4_compile *c, struct qinst *qinst);
432 struct qreg qir_uniform(struct vc4_compile *c,
433 enum quniform_contents contents,
434 uint32_t data);
435 void qir_reorder_uniforms(struct vc4_compile *c);
436 void qir_emit(struct vc4_compile *c, struct qinst *inst);
437 struct qreg qir_get_temp(struct vc4_compile *c);
438 int qir_get_op_nsrc(enum qop qop);
439 bool qir_reg_equals(struct qreg a, struct qreg b);
440 bool qir_has_side_effects(struct vc4_compile *c, struct qinst *inst);
441 bool qir_has_side_effect_reads(struct vc4_compile *c, struct qinst *inst);
442 bool qir_is_multi_instruction(struct qinst *inst);
443 bool qir_is_tex(struct qinst *inst);
444 bool qir_depends_on_flags(struct qinst *inst);
445 bool qir_writes_r4(struct qinst *inst);
446 bool qir_src_needs_a_file(struct qinst *inst);
447 struct qreg qir_follow_movs(struct vc4_compile *c, struct qreg reg);
448
449 void qir_dump(struct vc4_compile *c);
450 void qir_dump_inst(struct vc4_compile *c, struct qinst *inst);
451 const char *qir_get_stage_name(enum qstage stage);
452
453 void qir_optimize(struct vc4_compile *c);
454 bool qir_opt_algebraic(struct vc4_compile *c);
455 bool qir_opt_constant_folding(struct vc4_compile *c);
456 bool qir_opt_copy_propagation(struct vc4_compile *c);
457 bool qir_opt_cse(struct vc4_compile *c);
458 bool qir_opt_dead_code(struct vc4_compile *c);
459 bool qir_opt_small_immediates(struct vc4_compile *c);
460 bool qir_opt_vpm_writes(struct vc4_compile *c);
461 void vc4_nir_lower_io(struct vc4_compile *c);
462 nir_ssa_def *vc4_nir_get_state_uniform(struct nir_builder *b,
463 enum quniform_contents contents);
464 void qir_lower_uniforms(struct vc4_compile *c);
465
466 void qpu_schedule_instructions(struct vc4_compile *c);
467
468 void qir_SF(struct vc4_compile *c, struct qreg src);
469
470 static inline struct qreg
471 qir_uniform_ui(struct vc4_compile *c, uint32_t ui)
472 {
473 return qir_uniform(c, QUNIFORM_CONSTANT, ui);
474 }
475
476 static inline struct qreg
477 qir_uniform_f(struct vc4_compile *c, float f)
478 {
479 return qir_uniform(c, QUNIFORM_CONSTANT, fui(f));
480 }
481
482 #define QIR_ALU0(name) \
483 static inline struct qreg \
484 qir_##name(struct vc4_compile *c) \
485 { \
486 struct qreg t = qir_get_temp(c); \
487 qir_emit(c, qir_inst(QOP_##name, t, c->undef, c->undef)); \
488 return t; \
489 }
490
491 #define QIR_ALU1(name) \
492 static inline struct qreg \
493 qir_##name(struct vc4_compile *c, struct qreg a) \
494 { \
495 struct qreg t = qir_get_temp(c); \
496 qir_emit(c, qir_inst(QOP_##name, t, a, c->undef)); \
497 return t; \
498 }
499
500 #define QIR_ALU2(name) \
501 static inline struct qreg \
502 qir_##name(struct vc4_compile *c, struct qreg a, struct qreg b) \
503 { \
504 struct qreg t = qir_get_temp(c); \
505 qir_emit(c, qir_inst(QOP_##name, t, a, b)); \
506 return t; \
507 }
508
509 #define QIR_NODST_1(name) \
510 static inline void \
511 qir_##name(struct vc4_compile *c, struct qreg a) \
512 { \
513 qir_emit(c, qir_inst(QOP_##name, c->undef, a, c->undef)); \
514 }
515
516 #define QIR_NODST_2(name) \
517 static inline void \
518 qir_##name(struct vc4_compile *c, struct qreg a, struct qreg b) \
519 { \
520 qir_emit(c, qir_inst(QOP_##name, c->undef, a, b)); \
521 }
522
523 QIR_ALU1(MOV)
524 QIR_ALU2(FADD)
525 QIR_ALU2(FSUB)
526 QIR_ALU2(FMUL)
527 QIR_ALU2(MUL24)
528 QIR_ALU1(SEL_X_0_ZS)
529 QIR_ALU1(SEL_X_0_ZC)
530 QIR_ALU1(SEL_X_0_NS)
531 QIR_ALU1(SEL_X_0_NC)
532 QIR_ALU2(SEL_X_Y_ZS)
533 QIR_ALU2(SEL_X_Y_ZC)
534 QIR_ALU2(SEL_X_Y_NS)
535 QIR_ALU2(SEL_X_Y_NC)
536 QIR_ALU2(FMIN)
537 QIR_ALU2(FMAX)
538 QIR_ALU2(FMINABS)
539 QIR_ALU2(FMAXABS)
540 QIR_ALU1(FTOI)
541 QIR_ALU1(ITOF)
542
543 QIR_ALU2(ADD)
544 QIR_ALU2(SUB)
545 QIR_ALU2(SHL)
546 QIR_ALU2(SHR)
547 QIR_ALU2(ASR)
548 QIR_ALU2(MIN)
549 QIR_ALU2(MAX)
550 QIR_ALU2(AND)
551 QIR_ALU2(OR)
552 QIR_ALU2(XOR)
553 QIR_ALU1(NOT)
554
555 QIR_ALU1(RCP)
556 QIR_ALU1(RSQ)
557 QIR_ALU1(EXP2)
558 QIR_ALU1(LOG2)
559 QIR_ALU2(PACK_SCALED)
560 QIR_ALU1(PACK_8888_F)
561 QIR_ALU2(PACK_8A_F)
562 QIR_ALU2(PACK_8B_F)
563 QIR_ALU2(PACK_8C_F)
564 QIR_ALU2(PACK_8D_F)
565 QIR_ALU1(VARY_ADD_C)
566 QIR_NODST_2(TEX_S)
567 QIR_NODST_2(TEX_T)
568 QIR_NODST_2(TEX_R)
569 QIR_NODST_2(TEX_B)
570 QIR_NODST_2(TEX_DIRECT)
571 QIR_ALU0(FRAG_X)
572 QIR_ALU0(FRAG_Y)
573 QIR_ALU0(FRAG_Z)
574 QIR_ALU0(FRAG_W)
575 QIR_ALU0(FRAG_REV_FLAG)
576 QIR_ALU0(TEX_RESULT)
577 QIR_ALU0(TLB_COLOR_READ)
578 QIR_NODST_1(TLB_COLOR_WRITE)
579 QIR_NODST_1(TLB_Z_WRITE)
580 QIR_NODST_1(TLB_DISCARD_SETUP)
581 QIR_NODST_1(TLB_STENCIL_SETUP)
582
583 static inline struct qreg
584 qir_UNPACK_8_F(struct vc4_compile *c, struct qreg src, int i)
585 {
586 struct qreg t = qir_get_temp(c);
587 qir_emit(c, qir_inst(QOP_UNPACK_8A_F + i, t, src, c->undef));
588 return t;
589 }
590
591 static inline struct qreg
592 qir_UNPACK_8_I(struct vc4_compile *c, struct qreg src, int i)
593 {
594 struct qreg t = qir_get_temp(c);
595 qir_emit(c, qir_inst(QOP_UNPACK_8A_I + i, t, src, c->undef));
596 return t;
597 }
598
599 static inline struct qreg
600 qir_UNPACK_16_F(struct vc4_compile *c, struct qreg src, int i)
601 {
602 struct qreg t = qir_get_temp(c);
603 qir_emit(c, qir_inst(QOP_UNPACK_16A_F + i, t, src, c->undef));
604 return t;
605 }
606
607 static inline struct qreg
608 qir_UNPACK_16_I(struct vc4_compile *c, struct qreg src, int i)
609 {
610 struct qreg t = qir_get_temp(c);
611 qir_emit(c, qir_inst(QOP_UNPACK_16A_I + i, t, src, c->undef));
612 return t;
613 }
614
615 static inline struct qreg
616 qir_PACK_8_F(struct vc4_compile *c, struct qreg rest, struct qreg val, int chan)
617 {
618 struct qreg t = qir_get_temp(c);
619 qir_emit(c, qir_inst(QOP_PACK_8A_F + chan, t, rest, val));
620 return t;
621 }
622
623 static inline struct qreg
624 qir_POW(struct vc4_compile *c, struct qreg x, struct qreg y)
625 {
626 return qir_EXP2(c, qir_FMUL(c,
627 y,
628 qir_LOG2(c, x)));
629 }
630
631 static inline void
632 qir_VPM_WRITE(struct vc4_compile *c, struct qreg val)
633 {
634 static const struct qreg vpm = { QFILE_VPM, 0 };
635 qir_emit(c, qir_inst(QOP_MOV, vpm, val, c->undef));
636 }
637
638 #endif /* VC4_QIR_H */