2 * Copyright © 2010 Intel Corporation
3 * Copyright © 2014-2015 Broadcom
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26 * @file vc4_qir_schedule.c
28 * The basic model of the list scheduler is to take a basic block, compute a
29 * DAG of the dependencies from the bottom up, and make a list of the DAG
30 * heads. Heuristically pick a DAG head and schedule (remove) it, then put
31 * all the parents that are now DAG heads into the list of things to
34 * The goal of scheduling here, before register allocation and conversion to
35 * QPU instructions, is to reduce register pressure by reordering instructions
36 * to consume values when possible.
43 struct schedule_node
{
44 struct list_head link
;
47 struct schedule_node
**children
;
49 uint32_t child_array_size
;
50 uint32_t parent_count
;
52 /* Length of the longest (latency) chain from a DAG head to the this
57 /* Longest time + latency_between(parent, this) of any parent of this
60 uint32_t unblocked_time
;
63 struct schedule_state
{
64 /* List of struct schedule_node *. This starts out with all
65 * instructions, and after dependency updates it's trimmed to be just
68 struct list_head worklist
;
72 uint32_t *temp_writes
;
74 BITSET_WORD
*temp_live
;
77 /* When walking the instructions in reverse, we need to swap before/after in
80 enum direction
{ F
, R
};
83 * Marks a dependency between two intructions, that @after must appear after
86 * Our dependencies are tracked as a DAG. Since we're scheduling bottom-up,
87 * the latest instructions with nothing left to schedule are the DAG heads,
88 * and their inputs are their children.
91 add_dep(enum direction dir
,
92 struct schedule_node
*before
,
93 struct schedule_node
*after
)
95 if (!before
|| !after
)
98 assert(before
!= after
);
101 struct schedule_node
*t
= before
;
106 for (int i
= 0; i
< after
->child_count
; i
++) {
107 if (after
->children
[i
] == after
)
111 if (after
->child_array_size
<= after
->child_count
) {
112 after
->child_array_size
= MAX2(after
->child_array_size
* 2, 16);
113 after
->children
= reralloc(after
, after
->children
,
114 struct schedule_node
*,
115 after
->child_array_size
);
118 after
->children
[after
->child_count
] = before
;
119 after
->child_count
++;
120 before
->parent_count
++;
124 add_write_dep(enum direction dir
,
125 struct schedule_node
**before
,
126 struct schedule_node
*after
)
128 add_dep(dir
, *before
, after
);
132 struct schedule_setup_state
{
133 struct schedule_node
**last_temp_write
;
134 struct schedule_node
*last_sf
;
135 struct schedule_node
*last_vary_read
;
136 struct schedule_node
*last_vpm_read
;
137 struct schedule_node
*last_vpm_write
;
138 struct schedule_node
*last_tex_coord
;
139 struct schedule_node
*last_tex_result
;
140 struct schedule_node
*last_tlb
;
144 * Texture FIFO tracking. This is done top-to-bottom, and is used to
145 * track the QOP_TEX_RESULTs and add dependencies on previous ones
146 * when trying to submit texture coords with TFREQ full or new texture
147 * fetches with TXRCV full.
150 struct schedule_node
*node
;
153 int tfreq_count
; /**< Number of texture coords outstanding. */
154 int tfrcv_count
; /**< Number of texture results outstanding. */
159 block_until_tex_result(struct schedule_setup_state
*state
, struct schedule_node
*n
)
161 add_dep(state
->dir
, state
->tex_fifo
[0].node
, n
);
163 state
->tfreq_count
-= state
->tex_fifo
[0].coords
;
164 state
->tfrcv_count
--;
166 memmove(&state
->tex_fifo
[0],
168 state
->tex_fifo_pos
* sizeof(state
->tex_fifo
[0]));
169 state
->tex_fifo_pos
--;
173 * Common code for dependencies that need to be tracked both forward and
176 * This is for things like "all VPM reads have to happen in order."
179 calculate_deps(struct schedule_setup_state
*state
, struct schedule_node
*n
)
181 struct qinst
*inst
= n
->inst
;
182 enum direction dir
= state
->dir
;
185 /* Add deps for temp registers and varyings accesses. Note that we
186 * ignore uniforms accesses, because qir_reorder_uniforms() happens
189 for (int i
= 0; i
< qir_get_op_nsrc(inst
->op
); i
++) {
190 switch (inst
->src
[i
].file
) {
193 state
->last_temp_write
[inst
->src
[i
].index
], n
);
197 add_write_dep(dir
, &state
->last_vary_read
, n
);
201 add_write_dep(dir
, &state
->last_vpm_read
, n
);
211 add_dep(dir
, state
->last_vary_read
, n
);
219 /* Texturing setup gets scheduled in order, because
220 * the uniforms referenced by them have to land in a
223 add_write_dep(dir
, &state
->last_tex_coord
, n
);
227 /* Results have to be fetched in order. */
228 add_write_dep(dir
, &state
->last_tex_result
, n
);
231 case QOP_TLB_COLOR_WRITE
:
232 case QOP_TLB_COLOR_READ
:
233 case QOP_TLB_Z_WRITE
:
234 case QOP_TLB_STENCIL_SETUP
:
236 add_write_dep(dir
, &state
->last_tlb
, n
);
239 case QOP_TLB_DISCARD_SETUP
:
240 add_write_dep(dir
, &state
->last_sf
, n
);
241 add_write_dep(dir
, &state
->last_tlb
, n
);
248 if (inst
->dst
.file
== QFILE_VPM
)
249 add_write_dep(dir
, &state
->last_vpm_write
, n
);
250 else if (inst
->dst
.file
== QFILE_TEMP
)
251 add_write_dep(dir
, &state
->last_temp_write
[inst
->dst
.index
], n
);
254 add_write_dep(dir
, &state
->last_sf
, n
);
256 if (qir_depends_on_flags(inst
)) {
257 add_dep(dir
, state
->last_sf
, n
);
262 calculate_forward_deps(struct vc4_compile
*c
, void *mem_ctx
,
263 struct list_head
*schedule_list
)
265 struct schedule_setup_state state
;
267 memset(&state
, 0, sizeof(state
));
268 state
.last_temp_write
= rzalloc_array(mem_ctx
, struct schedule_node
*,
272 list_for_each_entry(struct schedule_node
, n
, schedule_list
, link
) {
273 struct qinst
*inst
= n
->inst
;
275 calculate_deps(&state
, n
);
283 /* If the texture coordinate fifo is full,
284 * block this on the last QOP_TEX_RESULT.
286 if (state
.tfreq_count
== 8) {
287 block_until_tex_result(&state
, n
);
290 /* If the texture result fifo is full, block
291 * adding any more to it until the last
294 if (inst
->op
== QOP_TEX_S
||
295 inst
->op
== QOP_TEX_DIRECT
) {
296 if (state
.tfrcv_count
== 4)
297 block_until_tex_result(&state
, n
);
301 state
.tex_fifo
[state
.tex_fifo_pos
].coords
++;
306 /* Results have to be fetched after the
307 * coordinate setup. Note that we're assuming
308 * here that our input shader has the texture
309 * coord setup and result fetch in order,
310 * which is true initially but not of our
311 * instruction stream after this pass.
313 add_dep(state
.dir
, state
.last_tex_coord
, n
);
315 state
.tex_fifo
[state
.tex_fifo_pos
].node
= n
;
317 state
.tex_fifo_pos
++;
318 memset(&state
.tex_fifo
[state
.tex_fifo_pos
], 0,
319 sizeof(state
.tex_fifo
[0]));
322 assert(!qir_is_tex(inst
));
329 calculate_reverse_deps(struct vc4_compile
*c
, void *mem_ctx
,
330 struct list_head
*schedule_list
)
332 struct schedule_setup_state state
;
334 memset(&state
, 0, sizeof(state
));
336 state
.last_temp_write
= rzalloc_array(mem_ctx
, struct schedule_node
*,
339 list_for_each_entry_rev(struct schedule_node
, n
, schedule_list
, link
) {
340 calculate_deps(&state
, n
);
345 get_register_pressure_cost(struct schedule_state
*state
, struct qinst
*inst
)
349 if (inst
->dst
.file
== QFILE_TEMP
&&
350 state
->temp_writes
[inst
->dst
.index
] == 1)
353 for (int i
= 0; i
< qir_get_op_nsrc(inst
->op
); i
++) {
354 if (inst
->src
[i
].file
== QFILE_TEMP
&&
355 !BITSET_TEST(state
->temp_live
, inst
->src
[i
].index
)) {
364 locks_scoreboard(struct qinst
*inst
)
367 case QOP_TLB_Z_WRITE
:
368 case QOP_TLB_COLOR_WRITE
:
369 case QOP_TLB_COLOR_WRITE_MS
:
370 case QOP_TLB_COLOR_READ
:
377 static struct schedule_node
*
378 choose_instruction(struct schedule_state
*state
)
380 struct schedule_node
*chosen
= NULL
;
382 list_for_each_entry(struct schedule_node
, n
, &state
->worklist
, link
) {
388 /* Prefer scheduling things that lock the scoreboard, so that
389 * they appear late in the program and we get more parallelism
390 * between shaders on multiple QPUs hitting the same fragment.
392 if (locks_scoreboard(n
->inst
) &&
393 !locks_scoreboard(chosen
->inst
)) {
396 } else if (!locks_scoreboard(n
->inst
) &&
397 locks_scoreboard(chosen
->inst
)) {
401 /* If we would block on the previously chosen node, but would
402 * block less on this one, then then prefer it.
404 if (chosen
->unblocked_time
> state
->time
&&
405 n
->unblocked_time
< chosen
->unblocked_time
) {
408 } else if (n
->unblocked_time
> state
->time
&&
409 n
->unblocked_time
> chosen
->unblocked_time
) {
413 /* If we can definitely reduce register pressure, do so
416 int register_pressure_cost
=
417 get_register_pressure_cost(state
, n
->inst
);
418 int chosen_register_pressure_cost
=
419 get_register_pressure_cost(state
, chosen
->inst
);
421 if (register_pressure_cost
< chosen_register_pressure_cost
) {
424 } else if (register_pressure_cost
>
425 chosen_register_pressure_cost
) {
429 /* Otherwise, prefer instructions with the deepest chain to
430 * the end of the program. This avoids the problem of
431 * "everything generates a temp, nothing finishes freeing one,
432 * guess I'll just keep emitting varying mul/adds".
434 if (n
->delay
> chosen
->delay
) {
437 } else if (n
->delay
< chosen
->delay
) {
446 dump_state(struct vc4_compile
*c
, struct schedule_state
*state
)
449 list_for_each_entry(struct schedule_node
, n
, &state
->worklist
, link
) {
450 fprintf(stderr
, "%3d: ", i
++);
451 qir_dump_inst(c
, n
->inst
);
452 fprintf(stderr
, " (%d cost)\n",
453 get_register_pressure_cost(state
, n
->inst
));
455 for (int i
= 0; i
< n
->child_count
; i
++) {
456 struct schedule_node
*child
= n
->children
[i
];
457 fprintf(stderr
, " - ");
458 qir_dump_inst(c
, child
->inst
);
459 fprintf(stderr
, " (%d parents)\n", child
->parent_count
);
464 /* Estimate of how many instructions we should schedule between operations.
466 * These aren't in real cycle counts, because we're just estimating cycle
467 * times anyway. QIR instructions will get paired up when turned into QPU
468 * instructions, or extra NOP delays will have to be added due to register
469 * allocation choices.
472 latency_between(struct schedule_node
*before
, struct schedule_node
*after
)
474 if ((before
->inst
->op
== QOP_TEX_S
||
475 before
->inst
->op
== QOP_TEX_DIRECT
) &&
476 after
->inst
->op
== QOP_TEX_RESULT
)
482 /** Recursive computation of the delay member of a node. */
484 compute_delay(struct schedule_node
*n
)
486 if (!n
->child_count
) {
487 /* The color read needs to be scheduled late, to avoid locking
488 * the scoreboard early. This is our best tool for
489 * encouraging that. The other scoreboard locking ops will
490 * have this happen by default, since they are generally the
491 * DAG heads or close to them.
493 if (n
->inst
->op
== QOP_TLB_COLOR_READ
)
498 for (int i
= 0; i
< n
->child_count
; i
++) {
499 if (!n
->children
[i
]->delay
)
500 compute_delay(n
->children
[i
]);
501 n
->delay
= MAX2(n
->delay
,
502 n
->children
[i
]->delay
+
503 latency_between(n
, n
->children
[i
]));
509 schedule_instructions(struct vc4_compile
*c
, struct schedule_state
*state
)
512 fprintf(stderr
, "initial deps:\n");
513 dump_state(c
, state
);
516 /* Remove non-DAG heads from the list. */
517 list_for_each_entry_safe(struct schedule_node
, n
,
518 &state
->worklist
, link
) {
519 if (n
->parent_count
!= 0)
524 while (!list_empty(&state
->worklist
)) {
525 struct schedule_node
*chosen
= choose_instruction(state
);
526 struct qinst
*inst
= chosen
->inst
;
529 fprintf(stderr
, "current list:\n");
530 dump_state(c
, state
);
531 fprintf(stderr
, "chose: ");
532 qir_dump_inst(c
, inst
);
533 fprintf(stderr
, " (%d cost)\n",
534 get_register_pressure_cost(state
, inst
));
537 state
->time
= MAX2(state
->time
, chosen
->unblocked_time
);
539 /* Schedule this instruction back onto the QIR list. */
540 list_del(&chosen
->link
);
541 list_add(&inst
->link
, &c
->instructions
);
543 /* Now that we've scheduled a new instruction, some of its
544 * children can be promoted to the list of instructions ready to
545 * be scheduled. Update the children's unblocked time for this
546 * DAG edge as we do so.
548 for (int i
= chosen
->child_count
- 1; i
>= 0; i
--) {
549 struct schedule_node
*child
= chosen
->children
[i
];
551 child
->unblocked_time
= MAX2(child
->unblocked_time
,
553 latency_between(chosen
,
555 child
->parent_count
--;
556 if (child
->parent_count
== 0)
557 list_add(&child
->link
, &state
->worklist
);
560 /* Update our tracking of register pressure. */
561 for (int i
= 0; i
< qir_get_op_nsrc(inst
->op
); i
++) {
562 if (inst
->src
[i
].file
== QFILE_TEMP
)
563 BITSET_SET(state
->temp_live
, inst
->src
[i
].index
);
565 if (inst
->dst
.file
== QFILE_TEMP
) {
566 state
->temp_writes
[inst
->dst
.index
]--;
567 if (state
->temp_writes
[inst
->dst
.index
] == 0)
568 BITSET_CLEAR(state
->temp_live
, inst
->dst
.index
);
576 qir_schedule_instructions(struct vc4_compile
*c
)
578 void *mem_ctx
= ralloc_context(NULL
);
579 struct schedule_state state
= { 0 };
582 fprintf(stderr
, "Pre-schedule instructions\n");
586 state
.temp_writes
= rzalloc_array(mem_ctx
, uint32_t, c
->num_temps
);
587 state
.temp_live
= rzalloc_array(mem_ctx
, BITSET_WORD
,
588 BITSET_WORDS(c
->num_temps
));
589 list_inithead(&state
.worklist
);
591 /* Wrap each instruction in a scheduler structure. */
592 list_for_each_entry_safe(struct qinst
, inst
, &c
->instructions
, link
) {
593 struct schedule_node
*n
= rzalloc(mem_ctx
, struct schedule_node
);
596 list_del(&inst
->link
);
597 list_addtail(&n
->link
, &state
.worklist
);
599 if (inst
->dst
.file
== QFILE_TEMP
)
600 state
.temp_writes
[inst
->dst
.index
]++;
603 /* Dependencies tracked top-to-bottom. */
604 calculate_forward_deps(c
, mem_ctx
, &state
.worklist
);
605 /* Dependencies tracked bottom-to-top. */
606 calculate_reverse_deps(c
, mem_ctx
, &state
.worklist
);
608 list_for_each_entry(struct schedule_node
, n
, &state
.worklist
, link
)
611 schedule_instructions(c
, &state
);
614 fprintf(stderr
, "Post-schedule instructions\n");
618 ralloc_free(mem_ctx
);