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vc4: Add support for the 2-bit LOAD_IMM variants.
[mesa.git] / src / gallium / drivers / vc4 / vc4_qpu.c
1 /*
2 * Copyright © 2014 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <stdbool.h>
25 #include "util/ralloc.h"
26 #include "vc4_qir.h"
27 #include "vc4_qpu.h"
28
29 #define QPU_MUX(mux, muxfield) \
30 QPU_SET_FIELD(mux != QPU_MUX_SMALL_IMM ? mux : QPU_MUX_B, muxfield)
31
32 static uint64_t
33 set_src_raddr(uint64_t inst, struct qpu_reg src)
34 {
35 if (src.mux == QPU_MUX_A) {
36 assert(QPU_GET_FIELD(inst, QPU_RADDR_A) == QPU_R_NOP ||
37 QPU_GET_FIELD(inst, QPU_RADDR_A) == src.addr);
38 return QPU_UPDATE_FIELD(inst, src.addr, QPU_RADDR_A);
39 }
40
41 if (src.mux == QPU_MUX_B) {
42 assert((QPU_GET_FIELD(inst, QPU_RADDR_B) == QPU_R_NOP ||
43 QPU_GET_FIELD(inst, QPU_RADDR_B) == src.addr) &&
44 QPU_GET_FIELD(inst, QPU_SIG) != QPU_SIG_SMALL_IMM);
45 return QPU_UPDATE_FIELD(inst, src.addr, QPU_RADDR_B);
46 }
47
48 if (src.mux == QPU_MUX_SMALL_IMM) {
49 if (QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_SMALL_IMM) {
50 assert(QPU_GET_FIELD(inst, QPU_RADDR_B) == src.addr);
51 } else {
52 inst = qpu_set_sig(inst, QPU_SIG_SMALL_IMM);
53 assert(QPU_GET_FIELD(inst, QPU_RADDR_B) == QPU_R_NOP);
54 }
55 return ((inst & ~QPU_RADDR_B_MASK) |
56 QPU_SET_FIELD(src.addr, QPU_RADDR_B));
57 }
58
59 return inst;
60 }
61
62 uint64_t
63 qpu_NOP()
64 {
65 uint64_t inst = 0;
66
67 inst |= QPU_SET_FIELD(QPU_A_NOP, QPU_OP_ADD);
68 inst |= QPU_SET_FIELD(QPU_M_NOP, QPU_OP_MUL);
69
70 /* Note: These field values are actually non-zero */
71 inst |= QPU_SET_FIELD(QPU_W_NOP, QPU_WADDR_ADD);
72 inst |= QPU_SET_FIELD(QPU_W_NOP, QPU_WADDR_MUL);
73 inst |= QPU_SET_FIELD(QPU_R_NOP, QPU_RADDR_A);
74 inst |= QPU_SET_FIELD(QPU_R_NOP, QPU_RADDR_B);
75 inst |= QPU_SET_FIELD(QPU_SIG_NONE, QPU_SIG);
76
77 return inst;
78 }
79
80 static uint64_t
81 qpu_a_dst(struct qpu_reg dst)
82 {
83 uint64_t inst = 0;
84
85 if (dst.mux <= QPU_MUX_R5) {
86 /* Translate the mux to the ACCn values. */
87 inst |= QPU_SET_FIELD(32 + dst.mux, QPU_WADDR_ADD);
88 } else {
89 inst |= QPU_SET_FIELD(dst.addr, QPU_WADDR_ADD);
90 if (dst.mux == QPU_MUX_B)
91 inst |= QPU_WS;
92 }
93
94 return inst;
95 }
96
97 static uint64_t
98 qpu_m_dst(struct qpu_reg dst)
99 {
100 uint64_t inst = 0;
101
102 if (dst.mux <= QPU_MUX_R5) {
103 /* Translate the mux to the ACCn values. */
104 inst |= QPU_SET_FIELD(32 + dst.mux, QPU_WADDR_MUL);
105 } else {
106 inst |= QPU_SET_FIELD(dst.addr, QPU_WADDR_MUL);
107 if (dst.mux == QPU_MUX_A)
108 inst |= QPU_WS;
109 }
110
111 return inst;
112 }
113
114 uint64_t
115 qpu_a_MOV(struct qpu_reg dst, struct qpu_reg src)
116 {
117 uint64_t inst = 0;
118
119 inst |= QPU_SET_FIELD(QPU_SIG_NONE, QPU_SIG);
120 inst |= QPU_SET_FIELD(QPU_A_OR, QPU_OP_ADD);
121 inst |= QPU_SET_FIELD(QPU_R_NOP, QPU_RADDR_A);
122 inst |= QPU_SET_FIELD(QPU_R_NOP, QPU_RADDR_B);
123 inst |= qpu_a_dst(dst);
124 inst |= QPU_SET_FIELD(QPU_COND_ALWAYS, QPU_COND_ADD);
125 inst |= QPU_MUX(src.mux, QPU_ADD_A);
126 inst |= QPU_MUX(src.mux, QPU_ADD_B);
127 inst = set_src_raddr(inst, src);
128 inst |= QPU_SET_FIELD(QPU_W_NOP, QPU_WADDR_MUL);
129
130 return inst;
131 }
132
133 uint64_t
134 qpu_m_MOV(struct qpu_reg dst, struct qpu_reg src)
135 {
136 uint64_t inst = 0;
137
138 inst |= QPU_SET_FIELD(QPU_SIG_NONE, QPU_SIG);
139 inst |= QPU_SET_FIELD(QPU_M_V8MIN, QPU_OP_MUL);
140 inst |= QPU_SET_FIELD(QPU_R_NOP, QPU_RADDR_A);
141 inst |= QPU_SET_FIELD(QPU_R_NOP, QPU_RADDR_B);
142 inst |= qpu_m_dst(dst);
143 inst |= QPU_SET_FIELD(QPU_COND_ALWAYS, QPU_COND_MUL);
144 inst |= QPU_MUX(src.mux, QPU_MUL_A);
145 inst |= QPU_MUX(src.mux, QPU_MUL_B);
146 inst = set_src_raddr(inst, src);
147 inst |= QPU_SET_FIELD(QPU_W_NOP, QPU_WADDR_ADD);
148
149 return inst;
150 }
151
152 uint64_t
153 qpu_load_imm_ui(struct qpu_reg dst, uint32_t val)
154 {
155 uint64_t inst = 0;
156
157 inst |= qpu_a_dst(dst);
158 inst |= QPU_SET_FIELD(QPU_W_NOP, QPU_WADDR_MUL);
159 inst |= QPU_SET_FIELD(QPU_COND_ALWAYS, QPU_COND_ADD);
160 inst |= QPU_SET_FIELD(QPU_COND_ALWAYS, QPU_COND_MUL);
161 inst |= QPU_SET_FIELD(QPU_SIG_LOAD_IMM, QPU_SIG);
162 inst |= val;
163
164 return inst;
165 }
166
167 uint64_t
168 qpu_load_imm_u2(struct qpu_reg dst, uint32_t val)
169 {
170 return qpu_load_imm_ui(dst, val) | QPU_SET_FIELD(QPU_LOAD_IMM_MODE_U2,
171 QPU_LOAD_IMM_MODE);
172 }
173
174 uint64_t
175 qpu_load_imm_i2(struct qpu_reg dst, uint32_t val)
176 {
177 return qpu_load_imm_ui(dst, val) | QPU_SET_FIELD(QPU_LOAD_IMM_MODE_I2,
178 QPU_LOAD_IMM_MODE);
179 }
180
181 uint64_t
182 qpu_branch(uint32_t cond, uint32_t target)
183 {
184 uint64_t inst = 0;
185
186 inst |= qpu_a_dst(qpu_ra(QPU_W_NOP));
187 inst |= qpu_m_dst(qpu_rb(QPU_W_NOP));
188 inst |= QPU_SET_FIELD(cond, QPU_BRANCH_COND);
189 inst |= QPU_SET_FIELD(QPU_SIG_BRANCH, QPU_SIG);
190 inst |= QPU_SET_FIELD(target, QPU_BRANCH_TARGET);
191
192 return inst;
193 }
194
195 uint64_t
196 qpu_a_alu2(enum qpu_op_add op,
197 struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1)
198 {
199 uint64_t inst = 0;
200
201 inst |= QPU_SET_FIELD(QPU_SIG_NONE, QPU_SIG);
202 inst |= QPU_SET_FIELD(op, QPU_OP_ADD);
203 inst |= QPU_SET_FIELD(QPU_R_NOP, QPU_RADDR_A);
204 inst |= QPU_SET_FIELD(QPU_R_NOP, QPU_RADDR_B);
205 inst |= qpu_a_dst(dst);
206 inst |= QPU_SET_FIELD(QPU_COND_ALWAYS, QPU_COND_ADD);
207 inst |= QPU_MUX(src0.mux, QPU_ADD_A);
208 inst = set_src_raddr(inst, src0);
209 inst |= QPU_MUX(src1.mux, QPU_ADD_B);
210 inst = set_src_raddr(inst, src1);
211 inst |= QPU_SET_FIELD(QPU_W_NOP, QPU_WADDR_MUL);
212
213 return inst;
214 }
215
216 uint64_t
217 qpu_m_alu2(enum qpu_op_mul op,
218 struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1)
219 {
220 uint64_t inst = 0;
221
222 inst |= QPU_SET_FIELD(QPU_SIG_NONE, QPU_SIG);
223 inst |= QPU_SET_FIELD(op, QPU_OP_MUL);
224 inst |= QPU_SET_FIELD(QPU_R_NOP, QPU_RADDR_A);
225 inst |= QPU_SET_FIELD(QPU_R_NOP, QPU_RADDR_B);
226 inst |= qpu_m_dst(dst);
227 inst |= QPU_SET_FIELD(QPU_COND_ALWAYS, QPU_COND_MUL);
228 inst |= QPU_MUX(src0.mux, QPU_MUL_A);
229 inst = set_src_raddr(inst, src0);
230 inst |= QPU_MUX(src1.mux, QPU_MUL_B);
231 inst = set_src_raddr(inst, src1);
232 inst |= QPU_SET_FIELD(QPU_W_NOP, QPU_WADDR_ADD);
233
234 return inst;
235 }
236
237 static bool
238 merge_fields(uint64_t *merge,
239 uint64_t a, uint64_t b,
240 uint64_t mask, uint64_t ignore)
241 {
242 if ((a & mask) == ignore) {
243 *merge = (*merge & ~mask) | (b & mask);
244 } else if ((b & mask) == ignore) {
245 *merge = (*merge & ~mask) | (a & mask);
246 } else {
247 if ((a & mask) != (b & mask))
248 return false;
249 }
250
251 return true;
252 }
253
254 int
255 qpu_num_sf_accesses(uint64_t inst)
256 {
257 int accesses = 0;
258 static const uint32_t specials[] = {
259 QPU_W_TLB_COLOR_MS,
260 QPU_W_TLB_COLOR_ALL,
261 QPU_W_TLB_Z,
262 QPU_W_TMU0_S,
263 QPU_W_TMU0_T,
264 QPU_W_TMU0_R,
265 QPU_W_TMU0_B,
266 QPU_W_TMU1_S,
267 QPU_W_TMU1_T,
268 QPU_W_TMU1_R,
269 QPU_W_TMU1_B,
270 QPU_W_SFU_RECIP,
271 QPU_W_SFU_RECIPSQRT,
272 QPU_W_SFU_EXP,
273 QPU_W_SFU_LOG,
274 };
275 uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
276 uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
277 uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
278 uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
279
280 for (int j = 0; j < ARRAY_SIZE(specials); j++) {
281 if (waddr_add == specials[j])
282 accesses++;
283 if (waddr_mul == specials[j])
284 accesses++;
285 }
286
287 if (raddr_a == QPU_R_MUTEX_ACQUIRE)
288 accesses++;
289 if (raddr_b == QPU_R_MUTEX_ACQUIRE &&
290 QPU_GET_FIELD(inst, QPU_SIG) != QPU_SIG_SMALL_IMM)
291 accesses++;
292
293 /* XXX: semaphore, combined color read/write? */
294 switch (QPU_GET_FIELD(inst, QPU_SIG)) {
295 case QPU_SIG_COLOR_LOAD:
296 case QPU_SIG_COLOR_LOAD_END:
297 case QPU_SIG_LOAD_TMU0:
298 case QPU_SIG_LOAD_TMU1:
299 accesses++;
300 }
301
302 return accesses;
303 }
304
305 static bool
306 qpu_waddr_ignores_ws(uint32_t waddr)
307 {
308 switch(waddr) {
309 case QPU_W_ACC0:
310 case QPU_W_ACC1:
311 case QPU_W_ACC2:
312 case QPU_W_ACC3:
313 case QPU_W_TLB_Z:
314 case QPU_W_TLB_COLOR_MS:
315 case QPU_W_TLB_COLOR_ALL:
316 case QPU_W_TLB_ALPHA_MASK:
317 case QPU_W_VPM:
318 case QPU_W_SFU_RECIP:
319 case QPU_W_SFU_RECIPSQRT:
320 case QPU_W_SFU_EXP:
321 case QPU_W_SFU_LOG:
322 case QPU_W_TMU0_S:
323 case QPU_W_TMU0_T:
324 case QPU_W_TMU0_R:
325 case QPU_W_TMU0_B:
326 case QPU_W_TMU1_S:
327 case QPU_W_TMU1_T:
328 case QPU_W_TMU1_R:
329 case QPU_W_TMU1_B:
330 return true;
331 }
332
333 return false;
334 }
335
336 static void
337 swap_ra_file_mux_helper(uint64_t *merge, uint64_t *a, uint32_t mux_shift)
338 {
339 uint64_t mux_mask = (uint64_t)0x7 << mux_shift;
340 uint64_t mux_a_val = (uint64_t)QPU_MUX_A << mux_shift;
341 uint64_t mux_b_val = (uint64_t)QPU_MUX_B << mux_shift;
342
343 if ((*a & mux_mask) == mux_a_val) {
344 *a = (*a & ~mux_mask) | mux_b_val;
345 *merge = (*merge & ~mux_mask) | mux_b_val;
346 }
347 }
348
349 static bool
350 try_swap_ra_file(uint64_t *merge, uint64_t *a, uint64_t *b)
351 {
352 uint32_t raddr_a_a = QPU_GET_FIELD(*a, QPU_RADDR_A);
353 uint32_t raddr_a_b = QPU_GET_FIELD(*a, QPU_RADDR_B);
354 uint32_t raddr_b_a = QPU_GET_FIELD(*b, QPU_RADDR_A);
355 uint32_t raddr_b_b = QPU_GET_FIELD(*b, QPU_RADDR_B);
356
357 if (raddr_a_b != QPU_R_NOP)
358 return false;
359
360 switch (raddr_a_a) {
361 case QPU_R_UNIF:
362 case QPU_R_VARY:
363 break;
364 default:
365 return false;
366 }
367
368 if (!(*merge & QPU_PM) &&
369 QPU_GET_FIELD(*merge, QPU_UNPACK) != QPU_UNPACK_NOP) {
370 return false;
371 }
372
373 if (raddr_b_b != QPU_R_NOP &&
374 raddr_b_b != raddr_a_a)
375 return false;
376
377 /* Move raddr A to B in instruction a. */
378 *a = (*a & ~QPU_RADDR_A_MASK) | QPU_SET_FIELD(QPU_R_NOP, QPU_RADDR_A);
379 *a = (*a & ~QPU_RADDR_B_MASK) | QPU_SET_FIELD(raddr_a_a, QPU_RADDR_B);
380 *merge = QPU_UPDATE_FIELD(*merge, raddr_b_a, QPU_RADDR_A);
381 *merge = QPU_UPDATE_FIELD(*merge, raddr_a_a, QPU_RADDR_B);
382 swap_ra_file_mux_helper(merge, a, QPU_ADD_A_SHIFT);
383 swap_ra_file_mux_helper(merge, a, QPU_ADD_B_SHIFT);
384 swap_ra_file_mux_helper(merge, a, QPU_MUL_A_SHIFT);
385 swap_ra_file_mux_helper(merge, a, QPU_MUL_B_SHIFT);
386
387 return true;
388 }
389
390 static bool
391 convert_mov(uint64_t *inst)
392 {
393 uint32_t add_a = QPU_GET_FIELD(*inst, QPU_ADD_A);
394 uint32_t waddr_add = QPU_GET_FIELD(*inst, QPU_WADDR_ADD);
395 uint32_t cond_add = QPU_GET_FIELD(*inst, QPU_COND_ADD);
396
397 /* Is it a MOV? */
398 if (QPU_GET_FIELD(*inst, QPU_OP_ADD) != QPU_A_OR ||
399 (add_a != QPU_GET_FIELD(*inst, QPU_ADD_B))) {
400 return false;
401 }
402
403 if (QPU_GET_FIELD(*inst, QPU_SIG) != QPU_SIG_NONE)
404 return false;
405
406 /* We could maybe support this in the .8888 and .8a-.8d cases. */
407 if (*inst & QPU_PM)
408 return false;
409
410 *inst = QPU_UPDATE_FIELD(*inst, QPU_A_NOP, QPU_OP_ADD);
411 *inst = QPU_UPDATE_FIELD(*inst, QPU_M_V8MIN, QPU_OP_MUL);
412
413 *inst = QPU_UPDATE_FIELD(*inst, add_a, QPU_MUL_A);
414 *inst = QPU_UPDATE_FIELD(*inst, add_a, QPU_MUL_B);
415 *inst = QPU_UPDATE_FIELD(*inst, QPU_MUX_R0, QPU_ADD_A);
416 *inst = QPU_UPDATE_FIELD(*inst, QPU_MUX_R0, QPU_ADD_B);
417
418 *inst = QPU_UPDATE_FIELD(*inst, waddr_add, QPU_WADDR_MUL);
419 *inst = QPU_UPDATE_FIELD(*inst, QPU_W_NOP, QPU_WADDR_ADD);
420
421 *inst = QPU_UPDATE_FIELD(*inst, cond_add, QPU_COND_MUL);
422 *inst = QPU_UPDATE_FIELD(*inst, QPU_COND_NEVER, QPU_COND_ADD);
423
424 if (!qpu_waddr_ignores_ws(waddr_add))
425 *inst ^= QPU_WS;
426
427 return true;
428 }
429
430 static bool
431 writes_a_file(uint64_t inst)
432 {
433 if (!(inst & QPU_WS))
434 return QPU_GET_FIELD(inst, QPU_WADDR_ADD) < 32;
435 else
436 return QPU_GET_FIELD(inst, QPU_WADDR_MUL) < 32;
437 }
438
439 static bool
440 reads_r4(uint64_t inst)
441 {
442 return (QPU_GET_FIELD(inst, QPU_ADD_A) == QPU_MUX_R4 ||
443 QPU_GET_FIELD(inst, QPU_ADD_B) == QPU_MUX_R4 ||
444 QPU_GET_FIELD(inst, QPU_MUL_A) == QPU_MUX_R4 ||
445 QPU_GET_FIELD(inst, QPU_MUL_B) == QPU_MUX_R4);
446 }
447
448 uint64_t
449 qpu_merge_inst(uint64_t a, uint64_t b)
450 {
451 uint64_t merge = a | b;
452 bool ok = true;
453 uint32_t a_sig = QPU_GET_FIELD(a, QPU_SIG);
454 uint32_t b_sig = QPU_GET_FIELD(b, QPU_SIG);
455
456 if (QPU_GET_FIELD(a, QPU_OP_ADD) != QPU_A_NOP &&
457 QPU_GET_FIELD(b, QPU_OP_ADD) != QPU_A_NOP) {
458 if (QPU_GET_FIELD(a, QPU_OP_MUL) != QPU_M_NOP ||
459 QPU_GET_FIELD(b, QPU_OP_MUL) != QPU_M_NOP ||
460 !(convert_mov(&a) || convert_mov(&b))) {
461 return 0;
462 } else {
463 merge = a | b;
464 }
465 }
466
467 if (QPU_GET_FIELD(a, QPU_OP_MUL) != QPU_M_NOP &&
468 QPU_GET_FIELD(b, QPU_OP_MUL) != QPU_M_NOP)
469 return 0;
470
471 if (qpu_num_sf_accesses(a) && qpu_num_sf_accesses(b))
472 return 0;
473
474 if (a_sig == QPU_SIG_LOAD_IMM ||
475 b_sig == QPU_SIG_LOAD_IMM ||
476 a_sig == QPU_SIG_SMALL_IMM ||
477 b_sig == QPU_SIG_SMALL_IMM ||
478 a_sig == QPU_SIG_BRANCH ||
479 b_sig == QPU_SIG_BRANCH) {
480 return 0;
481 }
482
483 ok = ok && merge_fields(&merge, a, b, QPU_SIG_MASK,
484 QPU_SET_FIELD(QPU_SIG_NONE, QPU_SIG));
485
486 /* Misc fields that have to match exactly. */
487 ok = ok && merge_fields(&merge, a, b, QPU_SF, ~0);
488
489 if (!merge_fields(&merge, a, b, QPU_RADDR_A_MASK,
490 QPU_SET_FIELD(QPU_R_NOP, QPU_RADDR_A))) {
491 /* Since we tend to use regfile A by default both for register
492 * allocation and for our special values (uniforms and
493 * varyings), try swapping uniforms and varyings to regfile B
494 * to resolve raddr A conflicts.
495 */
496 if (!try_swap_ra_file(&merge, &a, &b) &&
497 !try_swap_ra_file(&merge, &b, &a)) {
498 return 0;
499 }
500 }
501
502 ok = ok && merge_fields(&merge, a, b, QPU_RADDR_B_MASK,
503 QPU_SET_FIELD(QPU_R_NOP, QPU_RADDR_B));
504
505 ok = ok && merge_fields(&merge, a, b, QPU_WADDR_ADD_MASK,
506 QPU_SET_FIELD(QPU_W_NOP, QPU_WADDR_ADD));
507 ok = ok && merge_fields(&merge, a, b, QPU_WADDR_MUL_MASK,
508 QPU_SET_FIELD(QPU_W_NOP, QPU_WADDR_MUL));
509
510 /* Allow disagreement on WS (swapping A vs B physical reg file as the
511 * destination for ADD/MUL) if one of the original instructions
512 * ignores it (probably because it's just writing to accumulators).
513 */
514 if (qpu_waddr_ignores_ws(QPU_GET_FIELD(a, QPU_WADDR_ADD)) &&
515 qpu_waddr_ignores_ws(QPU_GET_FIELD(a, QPU_WADDR_MUL))) {
516 merge = (merge & ~QPU_WS) | (b & QPU_WS);
517 } else if (qpu_waddr_ignores_ws(QPU_GET_FIELD(b, QPU_WADDR_ADD)) &&
518 qpu_waddr_ignores_ws(QPU_GET_FIELD(b, QPU_WADDR_MUL))) {
519 merge = (merge & ~QPU_WS) | (a & QPU_WS);
520 } else {
521 if ((a & QPU_WS) != (b & QPU_WS))
522 return 0;
523 }
524
525 if (!merge_fields(&merge, a, b, QPU_PM, ~0)) {
526 /* If one instruction has PM bit set and the other not, the
527 * one without PM shouldn't do packing/unpacking, and we
528 * have to make sure non-NOP packing/unpacking from PM
529 * instruction aren't added to it.
530 */
531 uint64_t temp;
532
533 /* Let a be the one with PM bit */
534 if (!(a & QPU_PM)) {
535 temp = a;
536 a = b;
537 b = temp;
538 }
539
540 if ((b & (QPU_PACK_MASK | QPU_UNPACK_MASK)) != 0)
541 return 0;
542
543 if ((a & QPU_PACK_MASK) != 0 &&
544 QPU_GET_FIELD(b, QPU_OP_MUL) != QPU_M_NOP)
545 return 0;
546
547 if ((a & QPU_UNPACK_MASK) != 0 && reads_r4(b))
548 return 0;
549 } else {
550 /* packing: Make sure that non-NOP packs agree, then deal with
551 * special-case failing of adding a non-NOP pack to something
552 * with a NOP pack.
553 */
554 if (!merge_fields(&merge, a, b, QPU_PACK_MASK, 0))
555 return 0;
556 bool new_a_pack = (QPU_GET_FIELD(a, QPU_PACK) !=
557 QPU_GET_FIELD(merge, QPU_PACK));
558 bool new_b_pack = (QPU_GET_FIELD(b, QPU_PACK) !=
559 QPU_GET_FIELD(merge, QPU_PACK));
560 if (!(merge & QPU_PM)) {
561 /* Make sure we're not going to be putting a new
562 * a-file packing on either half.
563 */
564 if (new_a_pack && writes_a_file(a))
565 return 0;
566
567 if (new_b_pack && writes_a_file(b))
568 return 0;
569 } else {
570 /* Make sure we're not going to be putting new MUL
571 * packing oneither half.
572 */
573 if (new_a_pack &&
574 QPU_GET_FIELD(a, QPU_OP_MUL) != QPU_M_NOP)
575 return 0;
576
577 if (new_b_pack &&
578 QPU_GET_FIELD(b, QPU_OP_MUL) != QPU_M_NOP)
579 return 0;
580 }
581
582 /* unpacking: Make sure that non-NOP unpacks agree, then deal
583 * with special-case failing of adding a non-NOP unpack to
584 * something with a NOP unpack.
585 */
586 if (!merge_fields(&merge, a, b, QPU_UNPACK_MASK, 0))
587 return 0;
588 bool new_a_unpack = (QPU_GET_FIELD(a, QPU_UNPACK) !=
589 QPU_GET_FIELD(merge, QPU_UNPACK));
590 bool new_b_unpack = (QPU_GET_FIELD(b, QPU_UNPACK) !=
591 QPU_GET_FIELD(merge, QPU_UNPACK));
592 if (!(merge & QPU_PM)) {
593 /* Make sure we're not going to be putting a new
594 * a-file packing on either half.
595 */
596 if (new_a_unpack &&
597 QPU_GET_FIELD(a, QPU_RADDR_A) != QPU_R_NOP)
598 return 0;
599
600 if (new_b_unpack &&
601 QPU_GET_FIELD(b, QPU_RADDR_A) != QPU_R_NOP)
602 return 0;
603 } else {
604 /* Make sure we're not going to be putting new r4
605 * unpack on either half.
606 */
607 if (new_a_unpack && reads_r4(a))
608 return 0;
609
610 if (new_b_unpack && reads_r4(b))
611 return 0;
612 }
613 }
614
615 if (ok)
616 return merge;
617 else
618 return 0;
619 }
620
621 uint64_t
622 qpu_set_sig(uint64_t inst, uint32_t sig)
623 {
624 assert(QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_NONE);
625 return QPU_UPDATE_FIELD(inst, sig, QPU_SIG);
626 }
627
628 uint64_t
629 qpu_set_cond_add(uint64_t inst, uint32_t cond)
630 {
631 assert(QPU_GET_FIELD(inst, QPU_COND_ADD) == QPU_COND_ALWAYS);
632 return QPU_UPDATE_FIELD(inst, cond, QPU_COND_ADD);
633 }
634
635 uint64_t
636 qpu_set_cond_mul(uint64_t inst, uint32_t cond)
637 {
638 assert(QPU_GET_FIELD(inst, QPU_COND_MUL) == QPU_COND_ALWAYS);
639 return QPU_UPDATE_FIELD(inst, cond, QPU_COND_MUL);
640 }
641
642 bool
643 qpu_waddr_is_tlb(uint32_t waddr)
644 {
645 switch (waddr) {
646 case QPU_W_TLB_COLOR_ALL:
647 case QPU_W_TLB_COLOR_MS:
648 case QPU_W_TLB_Z:
649 return true;
650 default:
651 return false;
652 }
653 }
654
655 bool
656 qpu_inst_is_tlb(uint64_t inst)
657 {
658 uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
659
660 return (qpu_waddr_is_tlb(QPU_GET_FIELD(inst, QPU_WADDR_ADD)) ||
661 qpu_waddr_is_tlb(QPU_GET_FIELD(inst, QPU_WADDR_MUL)) ||
662 sig == QPU_SIG_COLOR_LOAD ||
663 sig == QPU_SIG_WAIT_FOR_SCOREBOARD);
664 }
665
666 /**
667 * Returns the small immediate value to be encoded in to the raddr b field if
668 * the argument can be represented as one, or ~0 otherwise.
669 */
670 uint32_t
671 qpu_encode_small_immediate(uint32_t i)
672 {
673 if (i <= 15)
674 return i;
675 if ((int)i < 0 && (int)i >= -16)
676 return i + 32;
677
678 switch (i) {
679 case 0x3f800000:
680 return 32;
681 case 0x40000000:
682 return 33;
683 case 0x40800000:
684 return 34;
685 case 0x41000000:
686 return 35;
687 case 0x41800000:
688 return 36;
689 case 0x42000000:
690 return 37;
691 case 0x42800000:
692 return 38;
693 case 0x43000000:
694 return 39;
695 case 0x3b800000:
696 return 40;
697 case 0x3c000000:
698 return 41;
699 case 0x3c800000:
700 return 42;
701 case 0x3d000000:
702 return 43;
703 case 0x3d800000:
704 return 44;
705 case 0x3e000000:
706 return 45;
707 case 0x3e800000:
708 return 46;
709 case 0x3f000000:
710 return 47;
711 }
712
713 return ~0;
714 }
715
716 void
717 qpu_serialize_one_inst(struct vc4_compile *c, uint64_t inst)
718 {
719 if (c->qpu_inst_count >= c->qpu_inst_size) {
720 c->qpu_inst_size = MAX2(16, c->qpu_inst_size * 2);
721 c->qpu_insts = reralloc(c, c->qpu_insts,
722 uint64_t, c->qpu_inst_size);
723 }
724 c->qpu_insts[c->qpu_inst_count++] = inst;
725 }