src/gallium/drivers/vc4/vc4_qpu.h

   1 /*
   2  * Copyright © 2014 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef VC4_QPU_H
  25 #define VC4_QPU_H
  26
  27 #include <stdint.h>
  28
  29 #include "util/u_math.h"
  30
  31 #include "vc4_qpu_defines.h"
  32
  33 struct qpu_reg {
  34         enum qpu_mux mux;
  35         uint8_t addr;
  36 };
  37
  38 static inline struct qpu_reg
  39 qpu_rn(int n)
  40 {
  41         struct qpu_reg r = {
  42                 QPU_MUX_R0 + n,
  43                 0,
  44         };
  45
  46         return r;
  47 }
  48
  49 static inline struct qpu_reg
  50 qpu_ra(int addr)
  51 {
  52         struct qpu_reg r = {
  53                 QPU_MUX_A,
  54                 addr,
  55         };
  56
  57         return r;
  58 }
  59
  60 static inline struct qpu_reg
  61 qpu_rb(int addr)
  62 {
  63         struct qpu_reg r = {
  64                 QPU_MUX_B,
  65                 addr,
  66         };
  67
  68         return r;
  69 }
  70
  71 static inline struct qpu_reg
  72 qpu_vary()
  73 {
  74         struct qpu_reg r = {
  75                 QPU_MUX_A,
  76                 QPU_R_VARY,
  77         };
  78
  79         return r;
  80 }
  81
  82 static inline struct qpu_reg
  83 qpu_unif()
  84 {
  85         struct qpu_reg r = {
  86                 QPU_MUX_A,
  87                 QPU_R_UNIF,
  88         };
  89
  90         return r;
  91 }
  92
  93 static inline struct qpu_reg
  94 qpu_vrsetup()
  95 {
  96         return qpu_ra(QPU_W_VPMVCD_SETUP);
  97 }
  98
  99 static inline struct qpu_reg
 100 qpu_vwsetup()
 101 {
 102         return qpu_rb(QPU_W_VPMVCD_SETUP);
 103 }
 104
 105 static inline struct qpu_reg
 106 qpu_tlbc()
 107 {
 108         struct qpu_reg r = {
 109                 QPU_MUX_A,
 110                 QPU_W_TLB_COLOR_ALL,
 111         };
 112
 113         return r;
 114 }
 115
 116 static inline struct qpu_reg qpu_r0(void) { return qpu_rn(0); }
 117 static inline struct qpu_reg qpu_r1(void) { return qpu_rn(1); }
 118 static inline struct qpu_reg qpu_r2(void) { return qpu_rn(2); }
 119 static inline struct qpu_reg qpu_r3(void) { return qpu_rn(3); }
 120 static inline struct qpu_reg qpu_r4(void) { return qpu_rn(4); }
 121 static inline struct qpu_reg qpu_r5(void) { return qpu_rn(5); }
 122
 123 uint64_t qpu_NOP(void);
 124 uint64_t qpu_a_MOV(struct qpu_reg dst, struct qpu_reg src);
 125 uint64_t qpu_m_MOV(struct qpu_reg dst, struct qpu_reg src);
 126 uint64_t qpu_a_alu2(enum qpu_op_add op, struct qpu_reg dst,
 127                     struct qpu_reg src0, struct qpu_reg src1);
 128 uint64_t qpu_m_alu2(enum qpu_op_mul op, struct qpu_reg dst,
 129                     struct qpu_reg src0, struct qpu_reg src1);
 130 uint64_t qpu_inst(uint64_t add, uint64_t mul);
 131 uint64_t qpu_load_imm_ui(struct qpu_reg dst, uint32_t val);
 132 uint64_t qpu_set_sig(uint64_t inst, uint32_t sig);
 133 uint64_t qpu_set_cond_add(uint64_t inst, uint32_t cond);
 134 uint64_t qpu_set_cond_mul(uint64_t inst, uint32_t cond);
 135
 136 static inline uint64_t
 137 qpu_load_imm_f(struct qpu_reg dst, float val)
 138 {
 139         return qpu_load_imm_ui(dst, fui(val));
 140 }
 141
 142 #define A_ALU2(op)                                                       \
 143 static inline uint64_t                                                   \
 144 qpu_a_##op(struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) \
 145 {                                                                        \
 146         return qpu_a_alu2(QPU_A_##op, dst, src0, src1);                  \
 147 }
 148
 149 #define M_ALU2(op)                                                       \
 150 static inline uint64_t                                                   \
 151 qpu_m_##op(struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) \
 152 {                                                                        \
 153         return qpu_m_alu2(QPU_M_##op, dst, src0, src1);                  \
 154 }
 155
 156 #define A_ALU1(op)                                                       \
 157 static inline uint64_t                                                   \
 158 qpu_a_##op(struct qpu_reg dst, struct qpu_reg src0)                      \
 159 {                                                                        \
 160         return qpu_a_alu2(QPU_A_##op, dst, src0, src0);                  \
 161 }
 162
 163 /*A_ALU2(NOP) */
 164 A_ALU2(FADD)
 165 A_ALU2(FSUB)
 166 A_ALU2(FMIN)
 167 A_ALU2(FMAX)
 168 A_ALU2(FMINABS)
 169 A_ALU2(FMAXABS)
 170 A_ALU1(FTOI)
 171 A_ALU1(ITOF)
 172 A_ALU2(ADD)
 173 A_ALU2(SUB)
 174 A_ALU2(SHR)
 175 A_ALU2(ASR)
 176 A_ALU2(ROR)
 177 A_ALU2(SHL)
 178 A_ALU2(MIN)
 179 A_ALU2(MAX)
 180 A_ALU2(AND)
 181 A_ALU2(OR)
 182 A_ALU2(XOR)
 183 A_ALU1(NOT)
 184 A_ALU1(CLZ)
 185 A_ALU2(V8ADDS)
 186 A_ALU2(V8SUBS)
 187
 188 /* M_ALU2(NOP) */
 189 M_ALU2(FMUL)
 190 M_ALU2(MUL24)
 191 M_ALU2(V8MULD)
 192 M_ALU2(V8MIN)
 193 M_ALU2(V8MAX)
 194 M_ALU2(V8ADDS)
 195 M_ALU2(V8SUBS)
 196
 197 void
 198 vc4_qpu_disasm(const uint64_t *instructions, int num_instructions);
 199
 200 void
 201 vc4_qpu_validate(uint64_t *insts, uint32_t num_inst);
 202
 203 #endif /* VC4_QPU_H */