45aac0e135bb8b41b450c09a3f00b54b2b2835cc
2 * Copyright © 2014 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #include "util/u_math.h"
31 #include "vc4_qpu_defines.h"
38 static inline struct qpu_reg
49 static inline struct qpu_reg
60 static inline struct qpu_reg
71 static inline struct qpu_reg
82 static inline struct qpu_reg
93 static inline struct qpu_reg
96 return qpu_ra(QPU_W_VPMVCD_SETUP
);
99 static inline struct qpu_reg
102 return qpu_rb(QPU_W_VPMVCD_SETUP
);
105 static inline struct qpu_reg
116 static inline struct qpu_reg
qpu_r0(void) { return qpu_rn(0); }
117 static inline struct qpu_reg
qpu_r1(void) { return qpu_rn(1); }
118 static inline struct qpu_reg
qpu_r2(void) { return qpu_rn(2); }
119 static inline struct qpu_reg
qpu_r3(void) { return qpu_rn(3); }
120 static inline struct qpu_reg
qpu_r4(void) { return qpu_rn(4); }
121 static inline struct qpu_reg
qpu_r5(void) { return qpu_rn(5); }
123 uint64_t qpu_a_MOV(struct qpu_reg dst
, struct qpu_reg src
);
124 uint64_t qpu_m_MOV(struct qpu_reg dst
, struct qpu_reg src
);
125 uint64_t qpu_a_NOP(void);
126 uint64_t qpu_m_NOP(void);
127 uint64_t qpu_a_alu2(enum qpu_op_add op
, struct qpu_reg dst
,
128 struct qpu_reg src0
, struct qpu_reg src1
);
129 uint64_t qpu_m_alu2(enum qpu_op_mul op
, struct qpu_reg dst
,
130 struct qpu_reg src0
, struct qpu_reg src1
);
131 uint64_t qpu_inst(uint64_t add
, uint64_t mul
);
132 uint64_t qpu_load_imm_ui(struct qpu_reg dst
, uint32_t val
);
133 uint64_t qpu_set_sig(uint64_t inst
, uint32_t sig
);
135 static inline uint64_t
136 qpu_load_imm_f(struct qpu_reg dst
, float val
)
138 return qpu_load_imm_ui(dst
, fui(val
));
142 static inline uint64_t \
143 qpu_a_##op(struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) \
145 return qpu_a_alu2(QPU_A_##op, dst, src0, src1); \
149 static inline uint64_t \
150 qpu_m_##op(struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) \
152 return qpu_m_alu2(QPU_M_##op, dst, src0, src1); \
156 static inline uint64_t \
157 qpu_a_##op(struct qpu_reg dst, struct qpu_reg src0) \
159 return qpu_a_alu2(QPU_A_##op, dst, src0, src0); \
197 vc4_qpu_disasm(const uint64_t *instructions
, int num_instructions
);
200 vc4_qpu_validate(uint64_t *insts
, uint32_t num_inst
);
202 #endif /* VC4_QPU_H */