2 * Copyright © 2014 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "util/u_math.h"
32 #include "vc4_qpu_defines.h"
41 static inline struct qpu_reg
52 static inline struct qpu_reg
63 static inline struct qpu_reg
74 static inline struct qpu_reg
85 static inline struct qpu_reg
96 static inline struct qpu_reg
99 return qpu_ra(QPU_W_VPMVCD_SETUP
);
102 static inline struct qpu_reg
105 return qpu_rb(QPU_W_VPMVCD_SETUP
);
108 static inline struct qpu_reg
119 static inline struct qpu_reg
qpu_r0(void) { return qpu_rn(0); }
120 static inline struct qpu_reg
qpu_r1(void) { return qpu_rn(1); }
121 static inline struct qpu_reg
qpu_r2(void) { return qpu_rn(2); }
122 static inline struct qpu_reg
qpu_r3(void) { return qpu_rn(3); }
123 static inline struct qpu_reg
qpu_r4(void) { return qpu_rn(4); }
124 static inline struct qpu_reg
qpu_r5(void) { return qpu_rn(5); }
126 uint64_t qpu_NOP(void) ATTRIBUTE_CONST
;
127 uint64_t qpu_a_MOV(struct qpu_reg dst
, struct qpu_reg src
) ATTRIBUTE_CONST
;
128 uint64_t qpu_m_MOV(struct qpu_reg dst
, struct qpu_reg src
) ATTRIBUTE_CONST
;
129 uint64_t qpu_a_alu2(enum qpu_op_add op
, struct qpu_reg dst
,
130 struct qpu_reg src0
, struct qpu_reg src1
) ATTRIBUTE_CONST
;
131 uint64_t qpu_m_alu2(enum qpu_op_mul op
, struct qpu_reg dst
,
132 struct qpu_reg src0
, struct qpu_reg src1
) ATTRIBUTE_CONST
;
133 uint64_t qpu_merge_inst(uint64_t a
, uint64_t b
) ATTRIBUTE_CONST
;
134 uint64_t qpu_load_imm_ui(struct qpu_reg dst
, uint32_t val
) ATTRIBUTE_CONST
;
135 uint64_t qpu_set_sig(uint64_t inst
, uint32_t sig
) ATTRIBUTE_CONST
;
136 uint64_t qpu_set_cond_add(uint64_t inst
, uint32_t cond
) ATTRIBUTE_CONST
;
137 uint64_t qpu_set_cond_mul(uint64_t inst
, uint32_t cond
) ATTRIBUTE_CONST
;
138 uint32_t qpu_encode_small_immediate(uint32_t i
) ATTRIBUTE_CONST
;
140 bool qpu_waddr_is_tlb(uint32_t waddr
) ATTRIBUTE_CONST
;
141 bool qpu_inst_is_tlb(uint64_t inst
) ATTRIBUTE_CONST
;
142 int qpu_num_sf_accesses(uint64_t inst
) ATTRIBUTE_CONST
;
143 void qpu_serialize_one_inst(struct vc4_compile
*c
, uint64_t inst
);
145 static inline uint64_t
146 qpu_load_imm_f(struct qpu_reg dst
, float val
)
148 return qpu_load_imm_ui(dst
, fui(val
));
152 static inline uint64_t \
153 qpu_a_##op(struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) \
155 return qpu_a_alu2(QPU_A_##op, dst, src0, src1); \
159 static inline uint64_t \
160 qpu_m_##op(struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) \
162 return qpu_m_alu2(QPU_M_##op, dst, src0, src1); \
166 static inline uint64_t \
167 qpu_a_##op(struct qpu_reg dst, struct qpu_reg src0) \
169 return qpu_a_alu2(QPU_A_##op, dst, src0, src0); \
207 vc4_qpu_disasm(const uint64_t *instructions
, int num_instructions
);
210 vc4_qpu_disasm_pack_mul(FILE *out
, uint32_t pack
);
213 vc4_qpu_disasm_pack_a(FILE *out
, uint32_t pack
);
216 vc4_qpu_disasm_unpack(FILE *out
, uint32_t pack
);
219 vc4_qpu_validate(uint64_t *insts
, uint32_t num_inst
);
221 #endif /* VC4_QPU_H */