src/gallium/drivers/vc4/vc4_qpu.h

   1 /*
   2  * Copyright © 2014 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef VC4_QPU_H
  25 #define VC4_QPU_H
  26
  27 #include <stdint.h>
  28
  29 #include "util/u_math.h"
  30
  31 #include "vc4_qpu_defines.h"
  32
  33 struct vc4_compile;
  34
  35 struct qpu_reg {
  36         enum qpu_mux mux;
  37         uint8_t addr;
  38 };
  39
  40 static inline struct qpu_reg
  41 qpu_rn(int n)
  42 {
  43         struct qpu_reg r = {
  44                 QPU_MUX_R0 + n,
  45                 0,
  46         };
  47
  48         return r;
  49 }
  50
  51 static inline struct qpu_reg
  52 qpu_ra(int addr)
  53 {
  54         struct qpu_reg r = {
  55                 QPU_MUX_A,
  56                 addr,
  57         };
  58
  59         return r;
  60 }
  61
  62 static inline struct qpu_reg
  63 qpu_rb(int addr)
  64 {
  65         struct qpu_reg r = {
  66                 QPU_MUX_B,
  67                 addr,
  68         };
  69
  70         return r;
  71 }
  72
  73 static inline struct qpu_reg
  74 qpu_vary()
  75 {
  76         struct qpu_reg r = {
  77                 QPU_MUX_A,
  78                 QPU_R_VARY,
  79         };
  80
  81         return r;
  82 }
  83
  84 static inline struct qpu_reg
  85 qpu_unif()
  86 {
  87         struct qpu_reg r = {
  88                 QPU_MUX_A,
  89                 QPU_R_UNIF,
  90         };
  91
  92         return r;
  93 }
  94
  95 static inline struct qpu_reg
  96 qpu_vrsetup()
  97 {
  98         return qpu_ra(QPU_W_VPMVCD_SETUP);
  99 }
 100
 101 static inline struct qpu_reg
 102 qpu_vwsetup()
 103 {
 104         return qpu_rb(QPU_W_VPMVCD_SETUP);
 105 }
 106
 107 static inline struct qpu_reg
 108 qpu_tlbc()
 109 {
 110         struct qpu_reg r = {
 111                 QPU_MUX_A,
 112                 QPU_W_TLB_COLOR_ALL,
 113         };
 114
 115         return r;
 116 }
 117
 118 static inline struct qpu_reg qpu_r0(void) { return qpu_rn(0); }
 119 static inline struct qpu_reg qpu_r1(void) { return qpu_rn(1); }
 120 static inline struct qpu_reg qpu_r2(void) { return qpu_rn(2); }
 121 static inline struct qpu_reg qpu_r3(void) { return qpu_rn(3); }
 122 static inline struct qpu_reg qpu_r4(void) { return qpu_rn(4); }
 123 static inline struct qpu_reg qpu_r5(void) { return qpu_rn(5); }
 124
 125 uint64_t qpu_NOP(void) ATTRIBUTE_CONST;
 126 uint64_t qpu_a_MOV(struct qpu_reg dst, struct qpu_reg src) ATTRIBUTE_CONST;
 127 uint64_t qpu_m_MOV(struct qpu_reg dst, struct qpu_reg src) ATTRIBUTE_CONST;
 128 uint64_t qpu_a_alu2(enum qpu_op_add op, struct qpu_reg dst,
 129                     struct qpu_reg src0, struct qpu_reg src1) ATTRIBUTE_CONST;
 130 uint64_t qpu_m_alu2(enum qpu_op_mul op, struct qpu_reg dst,
 131                     struct qpu_reg src0, struct qpu_reg src1) ATTRIBUTE_CONST;
 132 uint64_t qpu_merge_inst(uint64_t a, uint64_t b) ATTRIBUTE_CONST;
 133 uint64_t qpu_load_imm_ui(struct qpu_reg dst, uint32_t val) ATTRIBUTE_CONST;
 134 uint64_t qpu_set_sig(uint64_t inst, uint32_t sig) ATTRIBUTE_CONST;
 135 uint64_t qpu_set_cond_add(uint64_t inst, uint32_t cond) ATTRIBUTE_CONST;
 136 uint64_t qpu_set_cond_mul(uint64_t inst, uint32_t cond) ATTRIBUTE_CONST;
 137 uint32_t qpu_encode_small_immediate(uint32_t i) ATTRIBUTE_CONST;
 138
 139 bool qpu_waddr_is_tlb(uint32_t waddr) ATTRIBUTE_CONST;
 140 bool qpu_inst_is_tlb(uint64_t inst) ATTRIBUTE_CONST;
 141 int qpu_num_sf_accesses(uint64_t inst) ATTRIBUTE_CONST;
 142 void qpu_serialize_one_inst(struct vc4_compile *c, uint64_t inst);
 143
 144 static inline uint64_t
 145 qpu_load_imm_f(struct qpu_reg dst, float val)
 146 {
 147         return qpu_load_imm_ui(dst, fui(val));
 148 }
 149
 150 #define A_ALU2(op)                                                       \
 151 static inline uint64_t                                                   \
 152 qpu_a_##op(struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) \
 153 {                                                                        \
 154         return qpu_a_alu2(QPU_A_##op, dst, src0, src1);                  \
 155 }
 156
 157 #define M_ALU2(op)                                                       \
 158 static inline uint64_t                                                   \
 159 qpu_m_##op(struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) \
 160 {                                                                        \
 161         return qpu_m_alu2(QPU_M_##op, dst, src0, src1);                  \
 162 }
 163
 164 #define A_ALU1(op)                                                       \
 165 static inline uint64_t                                                   \
 166 qpu_a_##op(struct qpu_reg dst, struct qpu_reg src0)                      \
 167 {                                                                        \
 168         return qpu_a_alu2(QPU_A_##op, dst, src0, src0);                  \
 169 }
 170
 171 /*A_ALU2(NOP) */
 172 A_ALU2(FADD)
 173 A_ALU2(FSUB)
 174 A_ALU2(FMIN)
 175 A_ALU2(FMAX)
 176 A_ALU2(FMINABS)
 177 A_ALU2(FMAXABS)
 178 A_ALU1(FTOI)
 179 A_ALU1(ITOF)
 180 A_ALU2(ADD)
 181 A_ALU2(SUB)
 182 A_ALU2(SHR)
 183 A_ALU2(ASR)
 184 A_ALU2(ROR)
 185 A_ALU2(SHL)
 186 A_ALU2(MIN)
 187 A_ALU2(MAX)
 188 A_ALU2(AND)
 189 A_ALU2(OR)
 190 A_ALU2(XOR)
 191 A_ALU1(NOT)
 192 A_ALU1(CLZ)
 193 A_ALU2(V8ADDS)
 194 A_ALU2(V8SUBS)
 195
 196 /* M_ALU2(NOP) */
 197 M_ALU2(FMUL)
 198 M_ALU2(MUL24)
 199 M_ALU2(V8MULD)
 200 M_ALU2(V8MIN)
 201 M_ALU2(V8MAX)
 202 M_ALU2(V8ADDS)
 203 M_ALU2(V8SUBS)
 204
 205 void
 206 vc4_qpu_disasm(const uint64_t *instructions, int num_instructions);
 207
 208 void
 209 vc4_qpu_validate(uint64_t *insts, uint32_t num_inst);
 210
 211 #endif /* VC4_QPU_H */