2 * Copyright © 2014 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #ifndef VC4_QPU_DEFINES_H
25 #define VC4_QPU_DEFINES_H
28 #include <util/macros.h>
69 QPU_R_FRAG_PAYLOAD_ZW
= 15, /* W for A file, Z for B file */
70 /* 0-31 are the plain regfile a or b fields */
75 QPU_R_XY_PIXEL_COORD
= 41,
76 QPU_R_MS_REV_FLAGS
= 42,
84 /* 0-31 are the plain regfile a or b fields */
85 QPU_W_ACC0
= 32, /* aka r0 */
93 QPU_W_UNIFORMS_ADDRESS
,
94 QPU_W_QUAD_XY
, /* X for regfile a, Y for regfile b */
97 QPU_W_TLB_STENCIL_SETUP
= 43,
101 QPU_W_TLB_ALPHA_MASK
,
103 QPU_W_VPMVCD_SETUP
, /* LD for regfile a, ST for regfile b */
104 QPU_W_VPM_ADDR
, /* LD for regfile a, ST for regfile b */
121 QPU_SIG_SW_BREAKPOINT
,
123 QPU_SIG_THREAD_SWITCH
,
125 QPU_SIG_WAIT_FOR_SCOREBOARD
,
126 QPU_SIG_SCOREBOARD_UNLOCK
,
127 QPU_SIG_LAST_THREAD_SWITCH
,
128 QPU_SIG_COVERAGE_LOAD
,
130 QPU_SIG_COLOR_LOAD_END
,
133 QPU_SIG_ALPHA_MASK_LOAD
,
140 /* hardware mux values */
151 * Non-hardware mux value, stores a small immediate field to be
152 * programmed into raddr_b in the qpu_reg.index.
168 enum qpu_branch_cond
{
169 QPU_COND_BRANCH_ALL_ZS
,
170 QPU_COND_BRANCH_ALL_ZC
,
171 QPU_COND_BRANCH_ANY_ZS
,
172 QPU_COND_BRANCH_ANY_ZC
,
173 QPU_COND_BRANCH_ALL_NS
,
174 QPU_COND_BRANCH_ALL_NC
,
175 QPU_COND_BRANCH_ANY_NS
,
176 QPU_COND_BRANCH_ANY_NC
,
177 QPU_COND_BRANCH_ALL_CS
,
178 QPU_COND_BRANCH_ALL_CC
,
179 QPU_COND_BRANCH_ANY_CS
,
180 QPU_COND_BRANCH_ANY_CC
,
182 QPU_COND_BRANCH_ALWAYS
= 15
187 QPU_PACK_MUL_8888
= 3, /* replicated to each 8 bits of the 32-bit dst. */
196 /* convert to 16 bit float if float input, or to int16. */
199 /* replicated to each 8 bits of the 32-bit dst. */
201 /* Convert to 8-bit unsigned int. */
207 /* Saturating variants of the previous instructions. */
208 QPU_PACK_A_32_SAT
, /* int-only */
209 QPU_PACK_A_16A_SAT
, /* int or float */
229 #define QPU_MASK(high, low) ((((uint64_t)1<<((high)-(low)+1))-1)<<(low))
230 /* Using the GNU statement expression extension */
231 #define QPU_SET_FIELD(value, field) \
233 uint64_t fieldval = (uint64_t)(value) << field ## _SHIFT; \
234 assert((fieldval & ~ field ## _MASK) == 0); \
235 fieldval & field ## _MASK; \
238 #define QPU_GET_FIELD(word, field) ((uint32_t)(((word) & field ## _MASK) >> field ## _SHIFT))
240 #define QPU_UPDATE_FIELD(inst, value, field) \
241 (((inst) & ~(field ## _MASK)) | QPU_SET_FIELD(value, field))
243 #define QPU_SIG_SHIFT 60
244 #define QPU_SIG_MASK QPU_MASK(63, 60)
246 #define QPU_UNPACK_SHIFT 57
247 #define QPU_UNPACK_MASK QPU_MASK(59, 57)
249 #define QPU_LOAD_IMM_MODE_SHIFT 57
250 #define QPU_LOAD_IMM_MODE_MASK QPU_MASK(59, 57)
251 # define QPU_LOAD_IMM_MODE_U32 0
252 # define QPU_LOAD_IMM_MODE_I2 1
253 # define QPU_LOAD_IMM_MODE_U2 3
256 * If set, the pack field means PACK_MUL or R4 packing, instead of normal
259 #define QPU_PM ((uint64_t)1 << 56)
261 #define QPU_PACK_SHIFT 52
262 #define QPU_PACK_MASK QPU_MASK(55, 52)
264 #define QPU_COND_ADD_SHIFT 49
265 #define QPU_COND_ADD_MASK QPU_MASK(51, 49)
266 #define QPU_COND_MUL_SHIFT 46
267 #define QPU_COND_MUL_MASK QPU_MASK(48, 46)
270 #define QPU_BRANCH_COND_SHIFT 52
271 #define QPU_BRANCH_COND_MASK QPU_MASK(55, 52)
273 #define QPU_BRANCH_REL ((uint64_t)1 << 51)
274 #define QPU_BRANCH_REG ((uint64_t)1 << 50)
276 #define QPU_BRANCH_RADDR_A_SHIFT 45
277 #define QPU_BRANCH_RADDR_A_MASK QPU_MASK(49, 45)
279 #define QPU_SF ((uint64_t)1 << 45)
281 #define QPU_WADDR_ADD_SHIFT 38
282 #define QPU_WADDR_ADD_MASK QPU_MASK(43, 38)
283 #define QPU_WADDR_MUL_SHIFT 32
284 #define QPU_WADDR_MUL_MASK QPU_MASK(37, 32)
286 #define QPU_OP_MUL_SHIFT 29
287 #define QPU_OP_MUL_MASK QPU_MASK(31, 29)
289 #define QPU_RADDR_A_SHIFT 18
290 #define QPU_RADDR_A_MASK QPU_MASK(23, 18)
291 #define QPU_RADDR_B_SHIFT 12
292 #define QPU_RADDR_B_MASK QPU_MASK(17, 12)
293 #define QPU_SMALL_IMM_SHIFT 12
294 #define QPU_SMALL_IMM_MASK QPU_MASK(17, 12)
295 /* Small immediate value for rotate-by-r5, and 49-63 are "rotate by n
298 #define QPU_SMALL_IMM_MUL_ROT 48
300 #define QPU_ADD_A_SHIFT 9
301 #define QPU_ADD_A_MASK QPU_MASK(11, 9)
302 #define QPU_ADD_B_SHIFT 6
303 #define QPU_ADD_B_MASK QPU_MASK(8, 6)
304 #define QPU_MUL_A_SHIFT 3
305 #define QPU_MUL_A_MASK QPU_MASK(5, 3)
306 #define QPU_MUL_B_SHIFT 0
307 #define QPU_MUL_B_MASK QPU_MASK(2, 0)
309 #define QPU_WS ((uint64_t)1 << 44)
311 #define QPU_OP_ADD_SHIFT 24
312 #define QPU_OP_ADD_MASK QPU_MASK(28, 24)
314 #define QPU_LOAD_IMM_SHIFT 0
315 #define QPU_LOAD_IMM_MASK QPU_MASK(31, 0)
317 #define QPU_BRANCH_TARGET_SHIFT 0
318 #define QPU_BRANCH_TARGET_MASK QPU_MASK(31, 0)
320 #endif /* VC4_QPU_DEFINES_H */