2 * Copyright © 2014 Broadcom
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8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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24 #ifndef VC4_QPU_DEFINES_H
25 #define VC4_QPU_DEFINES_H
28 #include <util/macros.h>
69 QPU_R_FRAG_PAYLOAD_ZW
= 15, /* W for A file, Z for B file */
70 /* 0-31 are the plain regfile a or b fields */
75 QPU_R_XY_PIXEL_COORD
= 41,
76 QPU_R_MS_REV_FLAGS
= 42,
84 /* 0-31 are the plain regfile a or b fields */
85 QPU_W_ACC0
= 32, /* aka r0 */
93 QPU_W_UNIFORMS_ADDRESS
,
94 QPU_W_QUAD_XY
, /* X for regfile a, Y for regfile b */
97 QPU_W_TLB_STENCIL_SETUP
= 43,
101 QPU_W_TLB_ALPHA_MASK
,
103 QPU_W_VPMVCD_SETUP
, /* LD for regfile a, ST for regfile b */
104 QPU_W_VPM_ADDR
, /* LD for regfile a, ST for regfile b */
121 QPU_SIG_SW_BREAKPOINT
,
123 QPU_SIG_THREAD_SWITCH
,
125 QPU_SIG_WAIT_FOR_SCOREBOARD
,
126 QPU_SIG_SCOREBOARD_UNLOCK
,
127 QPU_SIG_LAST_THREAD_SWITCH
,
128 QPU_SIG_COVERAGE_LOAD
,
130 QPU_SIG_COLOR_LOAD_END
,
133 QPU_SIG_ALPHA_MASK_LOAD
,
140 /* hardware mux values */
151 * Non-hardware mux value, stores a small immediate field to be
152 * programmed into raddr_b in the qpu_reg.index.
170 QPU_PACK_MUL_8888
= 3, /* replicated to each 8 bits of the 32-bit dst. */
179 /* convert to 16 bit float if float input, or to int16. */
182 /* replicated to each 8 bits of the 32-bit dst. */
184 /* Convert to 8-bit unsigned int. */
190 /* Saturating variants of the previous instructions. */
191 QPU_PACK_A_32_SAT
, /* int-only */
192 QPU_PACK_A_16A_SAT
, /* int or float */
203 QPU_UNPACK_16A_TO_F32
,
204 QPU_UNPACK_16B_TO_F32
,
212 #define QPU_MASK(high, low) ((((uint64_t)1<<((high)-(low)+1))-1)<<(low))
213 /* Using the GNU statement expression extension */
214 #define QPU_SET_FIELD(value, field) \
216 uint64_t fieldval = (uint64_t)(value) << field ## _SHIFT; \
217 assert((fieldval & ~ field ## _MASK) == 0); \
218 fieldval & field ## _MASK; \
221 #define QPU_GET_FIELD(word, field) ((uint32_t)(((word) & field ## _MASK) >> field ## _SHIFT))
223 #define QPU_UPDATE_FIELD(inst, value, field) \
224 (((inst) & ~(field ## _MASK)) | QPU_SET_FIELD(value, field))
226 #define QPU_SIG_SHIFT 60
227 #define QPU_SIG_MASK QPU_MASK(63, 60)
229 #define QPU_UNPACK_SHIFT 57
230 #define QPU_UNPACK_MASK QPU_MASK(59, 57)
233 * If set, the pack field means PACK_MUL or R4 packing, instead of normal
236 #define QPU_PM ((uint64_t)1 << 56)
238 #define QPU_PACK_SHIFT 52
239 #define QPU_PACK_MASK QPU_MASK(55, 52)
241 #define QPU_COND_ADD_SHIFT 49
242 #define QPU_COND_ADD_MASK QPU_MASK(51, 49)
243 #define QPU_COND_MUL_SHIFT 46
244 #define QPU_COND_MUL_MASK QPU_MASK(48, 46)
246 #define QPU_SF ((uint64_t)1 << 45)
248 #define QPU_WADDR_ADD_SHIFT 38
249 #define QPU_WADDR_ADD_MASK QPU_MASK(43, 38)
250 #define QPU_WADDR_MUL_SHIFT 32
251 #define QPU_WADDR_MUL_MASK QPU_MASK(37, 32)
253 #define QPU_OP_MUL_SHIFT 29
254 #define QPU_OP_MUL_MASK QPU_MASK(31, 29)
256 #define QPU_RADDR_A_SHIFT 18
257 #define QPU_RADDR_A_MASK QPU_MASK(23, 18)
258 #define QPU_RADDR_B_SHIFT 12
259 #define QPU_RADDR_B_MASK QPU_MASK(17, 12)
260 #define QPU_SMALL_IMM_SHIFT 12
261 #define QPU_SMALL_IMM_MASK QPU_MASK(17, 12)
263 #define QPU_ADD_A_SHIFT 9
264 #define QPU_ADD_A_MASK QPU_MASK(11, 9)
265 #define QPU_ADD_B_SHIFT 6
266 #define QPU_ADD_B_MASK QPU_MASK(8, 6)
267 #define QPU_MUL_A_SHIFT 3
268 #define QPU_MUL_A_MASK QPU_MASK(5, 3)
269 #define QPU_MUL_B_SHIFT 0
270 #define QPU_MUL_B_MASK QPU_MASK(2, 0)
272 #define QPU_WS ((uint64_t)1 << 44)
274 #define QPU_OP_ADD_SHIFT 24
275 #define QPU_OP_ADD_MASK QPU_MASK(28, 24)
277 #endif /* VC4_QPU_DEFINES_H */