2 * Copyright © 2014 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #ifndef VC4_QPU_DEFINES_H
25 #define VC4_QPU_DEFINES_H
29 #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
70 QPU_R_FRAG_PAYLOAD_ZW
= 15, /* W for A file, Z for B file */
71 /* 0-31 are the plain regfile a or b fields */
76 QPU_R_XY_PIXEL_COORD
= 41,
77 QPU_R_MS_REV_FLAGS
= 41,
85 /* 0-31 are the plain regfile a or b fields */
86 QPU_W_ACC0
= 32, /* aka r0 */
94 QPU_W_UNIFORMS_ADDRESS
,
95 QPU_W_QUAD_XY
, /* X for regfile a, Y for regfile b */
98 QPU_W_TLB_STENCIL_SETUP
= 43,
102 QPU_W_TLB_ALPHA_MASK
,
104 QPU_W_VPMVCD_SETUP
, /* LD for regfile a, ST for regfile b */
105 QPU_W_VPM_ADDR
, /* LD for regfile a, ST for regfile b */
122 QPU_SIG_SW_BREAKPOINT
,
124 QPU_SIG_THREAD_SWITCH
,
126 QPU_SIG_WAIT_FOR_SCOREBOARD
,
127 QPU_SIG_SCOREBOARD_UNLOCK
,
128 QPU_SIG_LAST_THREAD_SWITCH
,
129 QPU_SIG_COVERAGE_LOAD
,
131 QPU_SIG_COLOR_LOAD_END
,
134 QPU_SIG_ALPHA_MASK_LOAD
,
141 /* hardware mux values */
151 /* non-hardware mux values */
168 QPU_PACK_MUL_8888
= 3, /* replicated to each 8 bits of the 32-bit dst. */
177 /* convert to 16 bit float if float input, or to int16. */
180 /* replicated to each 8 bits of the 32-bit dst. */
182 /* Convert to 8-bit unsigned int. */
188 /* Saturating variants of the previous instructions. */
189 QPU_PACK_A_32_SAT
, /* int-only */
190 QPU_PACK_A_16A_SAT
, /* int or float */
201 QPU_UNPACK_R4_F16A_TO_F32
,
202 QPU_UNPACK_R4_F16B_TO_F32
,
203 QPU_UNPACK_R4_8D_REP
,
210 #define QPU_MASK(high, low) ((((uint64_t)1<<((high)-(low)+1))-1)<<(low))
211 /* Using the GNU statement expression extension */
212 #define QPU_SET_FIELD(value, field) \
214 uint64_t fieldval = (uint64_t)(value) << field ## _SHIFT; \
215 assert((fieldval & ~ field ## _MASK) == 0); \
216 fieldval & field ## _MASK; \
219 #define QPU_GET_FIELD(word, field) ((uint32_t)(((word) & field ## _MASK) >> field ## _SHIFT))
221 #define QPU_SIG_SHIFT 60
222 #define QPU_SIG_MASK QPU_MASK(63, 60)
224 #define QPU_UNPACK_SHIFT 57
225 #define QPU_UNPACK_MASK QPU_MASK(59, 57)
228 * If set, the pack field means PACK_MUL or R4 packing, instead of normal
231 #define QPU_PM ((uint64_t)1 << 56)
233 #define QPU_PACK_SHIFT 52
234 #define QPU_PACK_MASK QPU_MASK(55, 52)
236 #define QPU_COND_ADD_SHIFT 49
237 #define QPU_COND_ADD_MASK QPU_MASK(51, 49)
238 #define QPU_COND_MUL_SHIFT 46
239 #define QPU_COND_MUL_MASK QPU_MASK(48, 46)
241 #define QPU_SF ((uint64_t)1 << 45)
243 #define QPU_WADDR_ADD_SHIFT 38
244 #define QPU_WADDR_ADD_MASK QPU_MASK(43, 38)
245 #define QPU_WADDR_MUL_SHIFT 32
246 #define QPU_WADDR_MUL_MASK QPU_MASK(37, 32)
248 #define QPU_OP_MUL_SHIFT 29
249 #define QPU_OP_MUL_MASK QPU_MASK(31, 29)
251 #define QPU_RADDR_A_SHIFT 18
252 #define QPU_RADDR_A_MASK QPU_MASK(23, 18)
253 #define QPU_RADDR_B_SHIFT 12
254 #define QPU_RADDR_B_MASK QPU_MASK(17, 12)
255 #define QPU_SMALL_IMM_SHIFT 12
256 #define QPU_SMALL_IMM_MASK QPU_MASK(17, 12)
258 #define QPU_ADD_A_SHIFT 9
259 #define QPU_ADD_A_MASK QPU_MASK(11, 9)
260 #define QPU_ADD_B_SHIFT 6
261 #define QPU_ADD_B_MASK QPU_MASK(8, 6)
262 #define QPU_MUL_A_SHIFT 3
263 #define QPU_MUL_A_MASK QPU_MASK(5, 3)
264 #define QPU_MUL_B_SHIFT 0
265 #define QPU_MUL_B_MASK QPU_MASK(2, 0)
267 #define QPU_WS ((uint64_t)1 << 44)
269 #define QPU_OP_ADD_SHIFT 24
270 #define QPU_OP_ADD_MASK QPU_MASK(28, 24)
272 #endif /* VC4_QPU_DEFINES_H */