2 * Copyright © 2014 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "vc4_context.h"
29 #include "util/ralloc.h"
32 vc4_dump_program(struct vc4_compile
*c
)
34 fprintf(stderr
, "%s prog %d/%d QPU:\n",
35 qir_get_stage_name(c
->stage
),
36 c
->program_id
, c
->variant_id
);
38 for (int i
= 0; i
< c
->qpu_inst_count
; i
++) {
39 fprintf(stderr
, "0x%016"PRIx64
" ", c
->qpu_insts
[i
]);
40 vc4_qpu_disasm(&c
->qpu_insts
[i
], 1);
41 fprintf(stderr
, "\n");
43 fprintf(stderr
, "\n");
47 queue(struct qblock
*block
, uint64_t inst
)
49 struct queued_qpu_inst
*q
= rzalloc(block
, struct queued_qpu_inst
);
51 list_addtail(&q
->link
, &block
->qpu_inst_list
);
55 last_inst(struct qblock
*block
)
57 struct queued_qpu_inst
*q
=
58 (struct queued_qpu_inst
*)block
->qpu_inst_list
.prev
;
63 set_last_cond_add(struct qblock
*block
, uint32_t cond
)
65 *last_inst(block
) = qpu_set_cond_add(*last_inst(block
), cond
);
69 set_last_cond_mul(struct qblock
*block
, uint32_t cond
)
71 *last_inst(block
) = qpu_set_cond_mul(*last_inst(block
), cond
);
75 * Some special registers can be read from either file, which lets us resolve
76 * raddr conflicts without extra MOVs.
79 swap_file(struct qpu_reg
*src
)
84 if (src
->mux
== QPU_MUX_SMALL_IMM
) {
87 if (src
->mux
== QPU_MUX_A
)
100 * Sets up the VPM read FIFO before we do any VPM read.
102 * VPM reads (vertex attribute input) and VPM writes (varyings output) from
103 * the QPU reuse the VRI (varying interpolation) block's FIFOs to talk to the
104 * VPM block. In the VS/CS (unlike in the FS), the block starts out
105 * uninitialized, and you need to emit setup to the block before any VPM
108 * VRI has a FIFO in each direction, with each FIFO able to hold four
109 * 32-bit-per-vertex values. VPM reads come through the read FIFO and VPM
110 * writes go through the write FIFO. The read/write setup values from QPU go
111 * through the write FIFO as well, with a sideband signal indicating that
112 * they're setup values. Once a read setup reaches the other side of the
113 * FIFO, the VPM block will start asynchronously reading vertex attributes and
114 * filling the read FIFO -- that way hopefully the QPU doesn't have to block
117 * VPM read setup can configure 16 32-bit-per-vertex values to be read at a
118 * time, which is 4 vec4s. If more than that is being read (since we support
119 * 8 vec4 vertex attributes), then multiple read setup writes need to be done.
121 * The existence of the FIFO makes it seem like you should be able to emit
122 * both setups for the 5-8 attribute cases and then do all the attribute
123 * reads. However, once the setup value makes it to the other end of the
124 * write FIFO, it will immediately update the VPM block's setup register.
125 * That updated setup register would be used for read FIFO fills from then on,
126 * breaking whatever remaining VPM values were supposed to be read into the
127 * read FIFO from the previous attribute set.
129 * As a result, we need to emit the read setup, pull every VPM read value from
130 * that setup, and only then emit the second setup if applicable.
133 setup_for_vpm_read(struct vc4_compile
*c
, struct qblock
*block
)
135 if (c
->num_inputs_in_fifo
) {
136 c
->num_inputs_in_fifo
--;
140 c
->num_inputs_in_fifo
= MIN2(c
->num_inputs_remaining
, 16);
143 qpu_load_imm_ui(qpu_vrsetup(),
146 ((c
->num_inputs_in_fifo
& 0xf) << 20)));
147 c
->num_inputs_remaining
-= c
->num_inputs_in_fifo
;
148 c
->vpm_read_offset
+= c
->num_inputs_in_fifo
;
150 c
->num_inputs_in_fifo
--;
154 * This is used to resolve the fact that we might register-allocate two
155 * different operands of an instruction to the same physical register file
156 * even though instructions have only one field for the register file source
159 * In that case, we need to move one to a temporary that can be used in the
160 * instruction, instead. We reserve ra31/rb31 for this purpose.
163 fixup_raddr_conflict(struct qblock
*block
,
165 struct qpu_reg
*src0
, struct qpu_reg
*src1
,
166 struct qinst
*inst
, uint64_t *unpack
)
168 uint32_t mux0
= src0
->mux
== QPU_MUX_SMALL_IMM
? QPU_MUX_B
: src0
->mux
;
169 uint32_t mux1
= src1
->mux
== QPU_MUX_SMALL_IMM
? QPU_MUX_B
: src1
->mux
;
171 if (mux0
<= QPU_MUX_R5
||
173 (src0
->addr
== src1
->addr
&&
174 src0
->mux
== src1
->mux
)) {
178 if (swap_file(src0
) || swap_file(src1
))
181 if (mux0
== QPU_MUX_A
) {
182 /* Make sure we use the same type of MOV as the instruction,
183 * in case of unpacks.
185 if (qir_is_float_input(inst
))
186 queue(block
, qpu_a_FMAX(qpu_rb(31), *src0
, *src0
));
188 queue(block
, qpu_a_MOV(qpu_rb(31), *src0
));
190 /* If we had an unpack on this A-file source, we need to put
191 * it into this MOV, not into the later move from regfile B.
193 if (inst
->src
[0].pack
) {
194 *last_inst(block
) |= *unpack
;
199 queue(block
, qpu_a_MOV(qpu_ra(31), *src0
));
205 set_last_dst_pack(struct qblock
*block
, struct qinst
*inst
)
207 bool had_pm
= *last_inst(block
) & QPU_PM
;
208 bool had_ws
= *last_inst(block
) & QPU_WS
;
209 uint32_t unpack
= QPU_GET_FIELD(*last_inst(block
), QPU_UNPACK
);
214 *last_inst(block
) |= QPU_SET_FIELD(inst
->dst
.pack
, QPU_PACK
);
216 if (qir_is_mul(inst
)) {
217 assert(!unpack
|| had_pm
);
218 *last_inst(block
) |= QPU_PM
;
220 assert(!unpack
|| !had_pm
);
221 assert(!had_ws
); /* dst must be a-file to pack. */
226 handle_r4_qpu_write(struct qblock
*block
, struct qinst
*qinst
,
229 if (dst
.mux
!= QPU_MUX_R4
)
230 queue(block
, qpu_a_MOV(dst
, qpu_r4()));
232 queue(block
, qpu_a_MOV(qpu_ra(QPU_W_NOP
), qpu_r4()));
236 vc4_generate_code_block(struct vc4_compile
*c
,
237 struct qblock
*block
,
238 struct qpu_reg
*temp_registers
)
240 int last_vpm_read_index
= -1;
242 qir_for_each_inst(qinst
, block
) {
244 fprintf(stderr
, "translating qinst to qpu: ");
245 qir_dump_inst(qinst
);
246 fprintf(stderr
, "\n");
249 static const struct {
252 #define A(name) [QOP_##name] = {QPU_A_##name}
253 #define M(name) [QOP_##name] = {QPU_M_##name}
282 /* If we replicate src[0] out to src[1], this works
283 * out the same as a MOV.
285 [QOP_MOV
] = { QPU_A_OR
},
286 [QOP_FMOV
] = { QPU_A_FMAX
},
287 [QOP_MMOV
] = { QPU_M_V8MIN
},
291 struct qpu_reg src
[4];
292 for (int i
= 0; i
< qir_get_op_nsrc(qinst
->op
); i
++) {
293 int index
= qinst
->src
[i
].index
;
294 switch (qinst
->src
[i
].file
) {
300 src
[i
] = temp_registers
[index
];
301 if (qinst
->src
[i
].pack
) {
303 unpack
== qinst
->src
[i
].pack
);
304 unpack
= QPU_SET_FIELD(qinst
->src
[i
].pack
,
306 if (src
[i
].mux
== QPU_MUX_R4
)
316 case QFILE_SMALL_IMM
:
317 src
[i
].mux
= QPU_MUX_SMALL_IMM
;
318 src
[i
].addr
= qpu_encode_small_immediate(qinst
->src
[i
].index
);
319 /* This should only have returned a valid
320 * small immediate field, not ~0 for failure.
322 assert(src
[i
].addr
<= 47);
325 setup_for_vpm_read(c
, block
);
326 assert((int)qinst
->src
[i
].index
>=
327 last_vpm_read_index
);
328 (void)last_vpm_read_index
;
329 last_vpm_read_index
= qinst
->src
[i
].index
;
330 src
[i
] = qpu_ra(QPU_R_VPM
);
334 src
[i
] = qpu_ra(QPU_R_XY_PIXEL_COORD
);
337 src
[i
] = qpu_rb(QPU_R_XY_PIXEL_COORD
);
339 case QFILE_FRAG_REV_FLAG
:
340 src
[i
] = qpu_rb(QPU_R_MS_REV_FLAGS
);
343 case QFILE_TLB_COLOR_WRITE
:
344 case QFILE_TLB_COLOR_WRITE_MS
:
345 case QFILE_TLB_Z_WRITE
:
346 case QFILE_TLB_STENCIL_SETUP
:
347 unreachable("bad qir src file");
352 switch (qinst
->dst
.file
) {
354 dst
= qpu_ra(QPU_W_NOP
);
357 dst
= temp_registers
[qinst
->dst
.index
];
360 dst
= qpu_ra(QPU_W_VPM
);
363 case QFILE_TLB_COLOR_WRITE
:
367 case QFILE_TLB_COLOR_WRITE_MS
:
371 case QFILE_TLB_Z_WRITE
:
372 dst
= qpu_ra(QPU_W_TLB_Z
);
375 case QFILE_TLB_STENCIL_SETUP
:
376 dst
= qpu_ra(QPU_W_TLB_STENCIL_SETUP
);
381 case QFILE_SMALL_IMM
:
385 case QFILE_FRAG_REV_FLAG
:
386 assert(!"not reached");
390 bool handled_qinst_cond
= false;
399 queue(block
, qpu_a_MOV(qpu_rb(QPU_W_SFU_RECIP
),
403 queue(block
, qpu_a_MOV(qpu_rb(QPU_W_SFU_RECIPSQRT
),
407 queue(block
, qpu_a_MOV(qpu_rb(QPU_W_SFU_EXP
),
411 queue(block
, qpu_a_MOV(qpu_rb(QPU_W_SFU_LOG
),
418 handle_r4_qpu_write(block
, qinst
, dst
);
423 assert(qinst
->src
[0].file
== QFILE_LOAD_IMM
);
424 queue(block
, qpu_load_imm_ui(dst
, qinst
->src
[0].index
));
428 src
[1] = qpu_ra(QPU_R_MS_REV_FLAGS
);
429 fixup_raddr_conflict(block
, dst
, &src
[0], &src
[1],
431 queue(block
, qpu_a_AND(qpu_ra(QPU_W_MS_FLAGS
),
432 src
[0], src
[1]) | unpack
);
437 /* QOP_FRAG_Z/W don't emit instructions, just allocate
438 * the register to the Z/W payload.
442 case QOP_TLB_COLOR_READ
:
443 queue(block
, qpu_NOP());
444 *last_inst(block
) = qpu_set_sig(*last_inst(block
),
446 handle_r4_qpu_write(block
, qinst
, dst
);
450 queue(block
, qpu_a_FADD(dst
, src
[0], qpu_r5()) | unpack
);
457 queue(block
, qpu_a_MOV(qpu_rb(QPU_W_TMU0_S
+
458 (qinst
->op
- QOP_TEX_S
)),
463 fixup_raddr_conflict(block
, dst
, &src
[0], &src
[1],
465 queue(block
, qpu_a_ADD(qpu_rb(QPU_W_TMU0_S
),
466 src
[0], src
[1]) | unpack
);
470 queue(block
, qpu_NOP());
471 *last_inst(block
) = qpu_set_sig(*last_inst(block
),
473 handle_r4_qpu_write(block
, qinst
, dst
);
477 /* The branch target will be updated at QPU scheduling
480 queue(block
, (qpu_branch(qinst
->cond
, 0) |
482 handled_qinst_cond
= true;
485 case QOP_UNIFORMS_RESET
:
486 fixup_raddr_conflict(block
, dst
, &src
[0], &src
[1],
489 queue(block
, qpu_a_ADD(qpu_ra(QPU_W_UNIFORMS_ADDRESS
),
494 assert(qinst
->op
< ARRAY_SIZE(translate
));
495 assert(translate
[qinst
->op
].op
!= 0); /* NOPs */
497 /* Skip emitting the MOV if it's a no-op. */
498 if (qir_is_raw_mov(qinst
) &&
499 dst
.mux
== src
[0].mux
&& dst
.addr
== src
[0].addr
) {
503 /* If we have only one source, put it in the second
504 * argument slot as well so that we don't take up
505 * another raddr just to get unused data.
507 if (qir_get_op_nsrc(qinst
->op
) == 1)
510 fixup_raddr_conflict(block
, dst
, &src
[0], &src
[1],
513 if (qir_is_mul(qinst
)) {
514 queue(block
, qpu_m_alu2(translate
[qinst
->op
].op
,
516 src
[0], src
[1]) | unpack
);
517 set_last_cond_mul(block
, qinst
->cond
);
519 queue(block
, qpu_a_alu2(translate
[qinst
->op
].op
,
521 src
[0], src
[1]) | unpack
);
522 set_last_cond_add(block
, qinst
->cond
);
524 handled_qinst_cond
= true;
525 set_last_dst_pack(block
, qinst
);
530 assert(qinst
->cond
== QPU_COND_ALWAYS
||
534 *last_inst(block
) |= QPU_SF
;
539 vc4_generate_code(struct vc4_context
*vc4
, struct vc4_compile
*c
)
541 struct qpu_reg
*temp_registers
= vc4_register_allocate(vc4
, c
);
542 struct qblock
*start_block
= list_first_entry(&c
->blocks
,
543 struct qblock
, link
);
548 c
->num_inputs_remaining
= c
->num_inputs
;
549 queue(start_block
, qpu_load_imm_ui(qpu_vwsetup(), 0x00001a00));
555 qir_for_each_block(block
, c
)
556 vc4_generate_code_block(c
, block
, temp_registers
);
558 uint32_t cycles
= qpu_schedule_instructions(c
);
559 uint32_t inst_count_at_schedule_time
= c
->qpu_inst_count
;
561 /* thread end can't have VPM write or read */
562 if (QPU_GET_FIELD(c
->qpu_insts
[c
->qpu_inst_count
- 1],
563 QPU_WADDR_ADD
) == QPU_W_VPM
||
564 QPU_GET_FIELD(c
->qpu_insts
[c
->qpu_inst_count
- 1],
565 QPU_WADDR_MUL
) == QPU_W_VPM
||
566 QPU_GET_FIELD(c
->qpu_insts
[c
->qpu_inst_count
- 1],
567 QPU_RADDR_A
) == QPU_R_VPM
||
568 QPU_GET_FIELD(c
->qpu_insts
[c
->qpu_inst_count
- 1],
569 QPU_RADDR_B
) == QPU_R_VPM
) {
570 qpu_serialize_one_inst(c
, qpu_NOP());
573 /* thread end can't have uniform read */
574 if (QPU_GET_FIELD(c
->qpu_insts
[c
->qpu_inst_count
- 1],
575 QPU_RADDR_A
) == QPU_R_UNIF
||
576 QPU_GET_FIELD(c
->qpu_insts
[c
->qpu_inst_count
- 1],
577 QPU_RADDR_B
) == QPU_R_UNIF
) {
578 qpu_serialize_one_inst(c
, qpu_NOP());
581 /* thread end can't have TLB operations */
582 if (qpu_inst_is_tlb(c
->qpu_insts
[c
->qpu_inst_count
- 1]))
583 qpu_serialize_one_inst(c
, qpu_NOP());
585 /* Make sure there's no existing signal set (like for a small
588 if (QPU_GET_FIELD(c
->qpu_insts
[c
->qpu_inst_count
- 1],
589 QPU_SIG
) != QPU_SIG_NONE
) {
590 qpu_serialize_one_inst(c
, qpu_NOP());
593 c
->qpu_insts
[c
->qpu_inst_count
- 1] =
594 qpu_set_sig(c
->qpu_insts
[c
->qpu_inst_count
- 1],
596 qpu_serialize_one_inst(c
, qpu_NOP());
597 qpu_serialize_one_inst(c
, qpu_NOP());
604 c
->qpu_insts
[c
->qpu_inst_count
- 1] =
605 qpu_set_sig(c
->qpu_insts
[c
->qpu_inst_count
- 1],
606 QPU_SIG_SCOREBOARD_UNLOCK
);
610 cycles
+= c
->qpu_inst_count
- inst_count_at_schedule_time
;
612 if (vc4_debug
& VC4_DEBUG_SHADERDB
) {
613 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %d estimated cycles\n",
614 qir_get_stage_name(c
->stage
),
615 c
->program_id
, c
->variant_id
,
619 if (vc4_debug
& VC4_DEBUG_QPU
)
622 vc4_qpu_validate(c
->qpu_insts
, c
->qpu_inst_count
);
624 free(temp_registers
);