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[mesa.git] / src / gallium / drivers / vc4 / vc4_qpu_emit.c
1 /*
2 * Copyright © 2014 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <stdio.h>
25 #include <inttypes.h>
26
27 #include "vc4_context.h"
28 #include "vc4_qir.h"
29 #include "vc4_qpu.h"
30
31 static void
32 vc4_dump_program(struct qcompile *c)
33 {
34 fprintf(stderr, "%s:\n", qir_get_stage_name(c->stage));
35
36 for (int i = 0; i < c->qpu_inst_count; i++) {
37 fprintf(stderr, "0x%016"PRIx64" ", c->qpu_insts[i]);
38 vc4_qpu_disasm(&c->qpu_insts[i], 1);
39 fprintf(stderr, "\n");
40 }
41 }
42
43 struct queued_qpu_inst {
44 struct simple_node link;
45 uint64_t inst;
46 };
47
48 static void
49 queue(struct qcompile *c, uint64_t inst)
50 {
51 struct queued_qpu_inst *q = calloc(1, sizeof(*q));
52 q->inst = inst;
53 insert_at_tail(&c->qpu_inst_list, &q->link);
54 }
55
56 static uint64_t *
57 last_inst(struct qcompile *c)
58 {
59 struct queued_qpu_inst *q =
60 (struct queued_qpu_inst *)last_elem(&c->qpu_inst_list);
61 return &q->inst;
62 }
63
64 /**
65 * This is used to resolve the fact that we might register-allocate two
66 * different operands of an instruction to the same physical register file
67 * even though instructions have only one field for the register file source
68 * address.
69 *
70 * In that case, we need to move one to a temporary that can be used in the
71 * instruction, instead.
72 */
73 static void
74 fixup_raddr_conflict(struct qcompile *c,
75 struct qpu_reg src0, struct qpu_reg *src1)
76 {
77 if ((src0.mux == QPU_MUX_A || src0.mux == QPU_MUX_B) &&
78 (src1->mux == QPU_MUX_A || src1->mux == QPU_MUX_B) &&
79 src0.addr != src1->addr) {
80 queue(c, qpu_inst(qpu_a_MOV(qpu_r3(), *src1),
81 qpu_m_NOP()));
82 *src1 = qpu_r3();
83 }
84 }
85
86 static void
87 serialize_one_inst(struct qcompile *c, uint64_t inst)
88 {
89 if (c->qpu_inst_count >= c->qpu_inst_size) {
90 c->qpu_inst_size = MAX2(16, c->qpu_inst_size * 2);
91 c->qpu_insts = realloc(c->qpu_insts,
92 c->qpu_inst_size * sizeof(uint64_t));
93 }
94 c->qpu_insts[c->qpu_inst_count++] = inst;
95 }
96
97 static void
98 serialize_insts(struct qcompile *c)
99 {
100 int last_sfu_write = -10;
101
102 while (!is_empty_list(&c->qpu_inst_list)) {
103 struct queued_qpu_inst *q =
104 (struct queued_qpu_inst *)first_elem(&c->qpu_inst_list);
105 uint32_t last_waddr_a = QPU_W_NOP, last_waddr_b = QPU_W_NOP;
106 uint32_t raddr_a = QPU_GET_FIELD(q->inst, QPU_RADDR_A);
107 uint32_t raddr_b = QPU_GET_FIELD(q->inst, QPU_RADDR_B);
108
109 if (c->qpu_inst_count > 0) {
110 uint64_t last_inst = c->qpu_insts[c->qpu_inst_count -
111 1];
112 uint32_t last_waddr_add = QPU_GET_FIELD(last_inst,
113 QPU_WADDR_ADD);
114 uint32_t last_waddr_mul = QPU_GET_FIELD(last_inst,
115 QPU_WADDR_MUL);
116
117 if (last_inst & QPU_WS) {
118 last_waddr_a = last_waddr_mul;
119 last_waddr_b = last_waddr_add;
120 } else {
121 last_waddr_a = last_waddr_add;
122 last_waddr_b = last_waddr_mul;
123 }
124 }
125
126 uint32_t src_muxes[] = {
127 QPU_GET_FIELD(q->inst, QPU_ADD_A),
128 QPU_GET_FIELD(q->inst, QPU_ADD_B),
129 QPU_GET_FIELD(q->inst, QPU_MUL_A),
130 QPU_GET_FIELD(q->inst, QPU_MUL_B),
131 };
132
133 /* "An instruction must not read from a location in physical
134 * regfile A or B that was written to by the previous
135 * instruction."
136 */
137 bool needs_raddr_vs_waddr_nop = false;
138 bool reads_r4 = false;
139 for (int i = 0; i < ARRAY_SIZE(src_muxes); i++) {
140 if ((raddr_a < 32 &&
141 src_muxes[i] == QPU_MUX_A &&
142 last_waddr_a == raddr_a) ||
143 (raddr_b < 32 &&
144 src_muxes[i] == QPU_MUX_B &&
145 last_waddr_b == raddr_b)) {
146 needs_raddr_vs_waddr_nop = true;
147 }
148 if (src_muxes[i] == QPU_MUX_R4)
149 reads_r4 = true;
150 }
151
152 if (needs_raddr_vs_waddr_nop) {
153 serialize_one_inst(c, qpu_inst(qpu_a_NOP(),
154 qpu_m_NOP()));
155 }
156
157 /* "After an SFU lookup instruction, accumulator r4 must not
158 * be read in the following two instructions. Any other
159 * instruction that results in r4 being written (that is, TMU
160 * read, TLB read, SFU lookup) cannot occur in the two
161 * instructions following an SFU lookup."
162 */
163 if (reads_r4) {
164 while (c->qpu_inst_count - last_sfu_write < 3) {
165 serialize_one_inst(c, qpu_inst(qpu_a_NOP(),
166 qpu_m_NOP()));
167 }
168 }
169
170 uint32_t waddr_a = QPU_GET_FIELD(q->inst, QPU_WADDR_ADD);
171 uint32_t waddr_m = QPU_GET_FIELD(q->inst, QPU_WADDR_MUL);
172 if ((waddr_a >= QPU_W_SFU_RECIP && waddr_a <= QPU_W_SFU_LOG) ||
173 (waddr_m >= QPU_W_SFU_RECIP && waddr_m <= QPU_W_SFU_LOG)) {
174 last_sfu_write = c->qpu_inst_count;
175 }
176
177 serialize_one_inst(c, q->inst);
178
179 remove_from_list(&q->link);
180 free(q);
181 }
182 }
183
184 void
185 vc4_generate_code(struct qcompile *c)
186 {
187 struct qpu_reg allocate_to_qpu_reg[3 + 32 + 32];
188 bool reg_in_use[ARRAY_SIZE(allocate_to_qpu_reg)];
189 int *reg_allocated = calloc(c->num_temps, sizeof(*reg_allocated));
190 int *reg_uses_remaining =
191 calloc(c->num_temps, sizeof(*reg_uses_remaining));
192
193 for (int i = 0; i < ARRAY_SIZE(reg_in_use); i++)
194 reg_in_use[i] = false;
195 for (int i = 0; i < c->num_temps; i++)
196 reg_allocated[i] = -1;
197 for (int i = 0; i < 3; i++)
198 allocate_to_qpu_reg[i] = qpu_rn(i);
199 for (int i = 0; i < 32; i++)
200 allocate_to_qpu_reg[i + 3] = qpu_ra(i);
201 for (int i = 0; i < 32; i++)
202 allocate_to_qpu_reg[i + 3 + 32] = qpu_rb(i);
203
204 make_empty_list(&c->qpu_inst_list);
205
206 struct simple_node *node;
207 foreach(node, &c->instructions) {
208 struct qinst *qinst = (struct qinst *)node;
209
210 if (qinst->dst.file == QFILE_TEMP)
211 reg_uses_remaining[qinst->dst.index]++;
212 for (int i = 0; i < qir_get_op_nsrc(qinst->op); i++) {
213 if (qinst->src[i].file == QFILE_TEMP)
214 reg_uses_remaining[qinst->src[i].index]++;
215 }
216 }
217
218 switch (c->stage) {
219 case QSTAGE_VERT:
220 case QSTAGE_COORD:
221 queue(c, qpu_load_imm_ui(qpu_vrsetup(),
222 (0x00001a00 +
223 0x00100000 * c->num_inputs)));
224 queue(c, qpu_load_imm_ui(qpu_vwsetup(), 0x00001a00));
225 break;
226 case QSTAGE_FRAG:
227 break;
228 }
229
230 foreach(node, &c->instructions) {
231 struct qinst *qinst = (struct qinst *)node;
232
233 #if 0
234 fprintf(stderr, "translating qinst to qpu: ");
235 qir_dump_inst(qinst);
236 fprintf(stderr, "\n");
237 #endif
238
239 static const struct {
240 uint32_t op;
241 bool is_mul;
242 } translate[] = {
243 #define A(name) [QOP_##name] = {QPU_A_##name, false}
244 #define M(name) [QOP_##name] = {QPU_M_##name, true}
245 A(FADD),
246 A(FSUB),
247 A(FMIN),
248 A(FMAX),
249 A(FMINABS),
250 A(FMAXABS),
251 A(FTOI),
252 A(ITOF),
253
254 M(FMUL),
255 };
256
257 static const uint32_t compareflags[] = {
258 [QOP_SEQ - QOP_SEQ] = QPU_COND_ZS,
259 [QOP_SNE - QOP_SEQ] = QPU_COND_ZC,
260 [QOP_SLT - QOP_SEQ] = QPU_COND_NS,
261 [QOP_SGE - QOP_SEQ] = QPU_COND_NC,
262 };
263
264 struct qpu_reg src[4];
265 for (int i = 0; i < qir_get_op_nsrc(qinst->op); i++) {
266 int index = qinst->src[i].index;
267 switch (qinst->src[i].file) {
268 case QFILE_NULL:
269 src[i] = qpu_rn(0);
270 break;
271 case QFILE_TEMP:
272 if (reg_allocated[index] == -1) {
273 fprintf(stderr, "undefined reg use: ");
274 qir_dump_inst(qinst);
275 fprintf(stderr, "\n");
276
277 src[i] = qpu_rn(0);
278 } else {
279 src[i] = allocate_to_qpu_reg[reg_allocated[index]];
280 reg_uses_remaining[index]--;
281 if (reg_uses_remaining[index] == 0)
282 reg_in_use[reg_allocated[index]] = false;
283 }
284 break;
285 case QFILE_UNIF:
286 src[i] = qpu_unif();
287 break;
288 case QFILE_VARY:
289 src[i] = qpu_vary();
290 break;
291 }
292 }
293
294 struct qpu_reg dst;
295 switch (qinst->dst.file) {
296 case QFILE_NULL:
297 dst = qpu_ra(QPU_W_NOP);
298 break;
299
300 case QFILE_TEMP:
301 if (reg_allocated[qinst->dst.index] == -1) {
302 int alloc;
303 for (alloc = 0;
304 alloc < ARRAY_SIZE(reg_in_use);
305 alloc++) {
306 /* The pack flags require an A-file register. */
307 if (qinst->op == QOP_PACK_SCALED &&
308 allocate_to_qpu_reg[alloc].mux != QPU_MUX_A) {
309 continue;
310 }
311
312 if (!reg_in_use[alloc])
313 break;
314 }
315 assert(alloc != ARRAY_SIZE(reg_in_use) && "need better reg alloc");
316 reg_in_use[alloc] = true;
317 reg_allocated[qinst->dst.index] = alloc;
318 }
319
320 dst = allocate_to_qpu_reg[reg_allocated[qinst->dst.index]];
321
322 reg_uses_remaining[qinst->dst.index]--;
323 if (reg_uses_remaining[qinst->dst.index] == 0) {
324 reg_in_use[reg_allocated[qinst->dst.index]] =
325 false;
326 }
327 break;
328
329 case QFILE_VARY:
330 case QFILE_UNIF:
331 assert(!"not reached");
332 break;
333 }
334
335 switch (qinst->op) {
336 case QOP_MOV:
337 /* Skip emitting the MOV if it's a no-op. */
338 if (dst.mux == QPU_MUX_A || dst.mux == QPU_MUX_B ||
339 dst.mux != src[0].mux || dst.addr != src[0].addr) {
340 queue(c, qpu_inst(qpu_a_MOV(dst, src[0]),
341 qpu_m_NOP()));
342 }
343 break;
344
345 case QOP_CMP:
346 queue(c, qpu_inst(qpu_a_MOV(qpu_ra(QPU_W_NOP),
347 src[0]),
348 qpu_m_NOP()));
349 *last_inst(c) |= QPU_SF;
350
351 if (dst.mux <= QPU_MUX_R3) {
352 fixup_raddr_conflict(c, src[1], &src[2]);
353 queue(c, qpu_inst(qpu_a_MOV(dst, src[1]),
354 qpu_m_MOV(dst, src[2])));
355 *last_inst(c) = ((*last_inst(c) & ~(QPU_COND_ADD_MASK |
356 QPU_COND_MUL_MASK))
357 | QPU_SET_FIELD(QPU_COND_NS,
358 QPU_COND_ADD)
359 | QPU_SET_FIELD(QPU_COND_NC,
360 QPU_COND_MUL));
361 } else {
362 if (dst.mux == src[1].mux &&
363 dst.addr == src[1].addr) {
364 queue(c, qpu_inst(qpu_a_MOV(dst, src[1]),
365 qpu_m_NOP()));
366
367 queue(c, qpu_inst(qpu_a_MOV(dst, src[2]),
368 qpu_m_NOP()));
369 *last_inst(c) = ((*last_inst(c) & ~(QPU_COND_ADD_MASK))
370 | QPU_SET_FIELD(QPU_COND_NC,
371 QPU_COND_ADD));
372 } else {
373 queue(c, qpu_inst(qpu_a_MOV(dst, src[2]),
374 qpu_m_NOP()));
375
376 queue(c, qpu_inst(qpu_a_MOV(dst, src[1]),
377 qpu_m_NOP()));
378 *last_inst(c) = ((*last_inst(c) & ~(QPU_COND_ADD_MASK))
379 | QPU_SET_FIELD(QPU_COND_NS,
380 QPU_COND_ADD));
381 }
382 }
383 break;
384
385 case QOP_SEQ:
386 case QOP_SNE:
387 case QOP_SGE:
388 case QOP_SLT:
389 fixup_raddr_conflict(c, src[0], &src[1]);
390 queue(c, qpu_inst(qpu_a_SUB(qpu_ra(QPU_W_NOP),
391 src[0], src[1]),
392 qpu_m_NOP()));
393 *last_inst(c) |= QPU_SF;
394
395 queue(c, qpu_load_imm_f(dst, 0.0));
396 queue(c, qpu_load_imm_f(dst, 1.0));
397 *last_inst(c) = ((*last_inst(c) & ~QPU_COND_ADD_MASK)
398 | QPU_SET_FIELD(compareflags[qinst->op - QOP_SEQ],
399 QPU_COND_ADD));
400
401 break;
402
403 case QOP_VPM_WRITE:
404 queue(c, qpu_inst(qpu_a_MOV(qpu_ra(QPU_W_VPM), src[0]),
405 qpu_m_NOP()));
406 break;
407
408 case QOP_VPM_READ:
409 queue(c, qpu_inst(qpu_a_MOV(dst, qpu_ra(QPU_R_VPM)),
410 qpu_m_NOP()));
411 break;
412
413 case QOP_RCP:
414 case QOP_RSQ:
415 case QOP_EXP2:
416 case QOP_LOG2:
417 switch (qinst->op) {
418 case QOP_RCP:
419 queue(c, qpu_inst(qpu_a_MOV(qpu_rb(QPU_W_SFU_RECIP),
420 src[0]),
421 qpu_m_NOP()));
422 break;
423 case QOP_RSQ:
424 queue(c, qpu_inst(qpu_a_MOV(qpu_rb(QPU_W_SFU_RECIPSQRT),
425 src[0]),
426 qpu_m_NOP()));
427 break;
428 case QOP_EXP2:
429 queue(c, qpu_inst(qpu_a_MOV(qpu_rb(QPU_W_SFU_EXP),
430 src[0]),
431 qpu_m_NOP()));
432 break;
433 case QOP_LOG2:
434 queue(c, qpu_inst(qpu_a_MOV(qpu_rb(QPU_W_SFU_LOG),
435 src[0]),
436 qpu_m_NOP()));
437 break;
438 default:
439 abort();
440 }
441
442 queue(c, qpu_inst(qpu_a_MOV(dst, qpu_r4()),
443 qpu_m_NOP()));
444
445 break;
446
447 case QOP_PACK_COLORS:
448 for (int i = 0; i < 4; i++) {
449 queue(c, qpu_inst(qpu_a_NOP(),
450 qpu_m_MOV(qpu_r3(), src[i])));
451 *last_inst(c) |= QPU_PM;
452 *last_inst(c) |= QPU_SET_FIELD(QPU_PACK_MUL_8A + i,
453 QPU_PACK);
454 }
455
456 queue(c, qpu_inst(qpu_a_MOV(dst, qpu_r3()),
457 qpu_m_NOP()));
458
459 break;
460
461 case QOP_TLB_COLOR_WRITE:
462 queue(c, qpu_inst(qpu_a_MOV(qpu_tlbc(),
463 src[0]),
464 qpu_m_NOP()));
465 break;
466
467 case QOP_VARY_ADD_C:
468 queue(c, qpu_inst(qpu_a_FADD(dst,
469 src[0], qpu_r5()),
470 qpu_m_NOP()));
471 break;
472
473 case QOP_PACK_SCALED:
474 queue(c, qpu_inst(qpu_a_MOV(dst, src[0]),
475 qpu_m_NOP()));
476 *last_inst(c) |= QPU_SET_FIELD(QPU_PACK_A_16A,
477 QPU_PACK);
478
479 queue(c, qpu_inst(qpu_a_MOV(dst, src[1]),
480 qpu_m_NOP()));
481 *last_inst(c) |= QPU_SET_FIELD(QPU_PACK_A_16B,
482 QPU_PACK);
483
484 break;
485
486 default:
487 assert(qinst->op < ARRAY_SIZE(translate));
488 assert(translate[qinst->op].op != 0); /* NOPs */
489
490 /* If we have only one source, put it in the second
491 * argument slot as well so that we don't take up
492 * another raddr just to get unused data.
493 */
494 if (qir_get_op_nsrc(qinst->op) == 1)
495 src[1] = src[0];
496
497 fixup_raddr_conflict(c, src[0], &src[1]);
498
499 if (translate[qinst->op].is_mul) {
500 queue(c, qpu_inst(qpu_a_NOP(),
501 qpu_m_alu2(translate[qinst->op].op,
502 dst,
503 src[0], src[1])));
504 } else {
505 queue(c, qpu_inst(qpu_a_alu2(translate[qinst->op].op,
506 dst,
507 src[0], src[1]),
508 qpu_m_NOP()));
509 }
510 break;
511 }
512 }
513
514 serialize_insts(c);
515
516 /* thread end can't have VPM write */
517 if (QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
518 QPU_WADDR_ADD) == QPU_W_VPM ||
519 QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
520 QPU_WADDR_MUL) == QPU_W_VPM) {
521 serialize_one_inst(c, qpu_inst(qpu_a_NOP(), qpu_m_NOP()));
522 }
523
524 c->qpu_insts[c->qpu_inst_count - 1] =
525 qpu_set_sig(c->qpu_insts[c->qpu_inst_count - 1],
526 QPU_SIG_PROG_END);
527 serialize_one_inst(c, qpu_inst(qpu_a_NOP(), qpu_m_NOP()));
528 serialize_one_inst(c, qpu_inst(qpu_a_NOP(), qpu_m_NOP()));
529
530 switch (c->stage) {
531 case QSTAGE_VERT:
532 case QSTAGE_COORD:
533 break;
534 case QSTAGE_FRAG:
535 c->qpu_insts[2] = qpu_set_sig(c->qpu_insts[2],
536 QPU_SIG_WAIT_FOR_SCOREBOARD);
537 c->qpu_insts[c->qpu_inst_count - 1] =
538 qpu_set_sig(c->qpu_insts[c->qpu_inst_count - 1],
539 QPU_SIG_SCOREBOARD_UNLOCK);
540 break;
541 }
542
543 if (vc4_debug & VC4_DEBUG_QPU)
544 vc4_dump_program(c);
545
546 vc4_qpu_validate(c->qpu_insts, c->qpu_inst_count);
547 }