2 * Copyright © 2014 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "vc4_context.h"
29 #include "util/ralloc.h"
32 vc4_dump_program(struct vc4_compile
*c
)
34 fprintf(stderr
, "%s prog %d/%d QPU:\n",
35 qir_get_stage_name(c
->stage
),
36 c
->program_id
, c
->variant_id
);
38 for (int i
= 0; i
< c
->qpu_inst_count
; i
++) {
39 fprintf(stderr
, "0x%016"PRIx64
" ", c
->qpu_insts
[i
]);
40 vc4_qpu_disasm(&c
->qpu_insts
[i
], 1);
41 fprintf(stderr
, "\n");
43 fprintf(stderr
, "\n");
47 queue(struct vc4_compile
*c
, uint64_t inst
)
49 struct queued_qpu_inst
*q
= rzalloc(c
, struct queued_qpu_inst
);
51 list_addtail(&q
->link
, &c
->qpu_inst_list
);
55 last_inst(struct vc4_compile
*c
)
57 struct queued_qpu_inst
*q
=
58 (struct queued_qpu_inst
*)c
->qpu_inst_list
.prev
;
63 set_last_cond_add(struct vc4_compile
*c
, uint32_t cond
)
65 *last_inst(c
) = qpu_set_cond_add(*last_inst(c
), cond
);
69 set_last_cond_mul(struct vc4_compile
*c
, uint32_t cond
)
71 *last_inst(c
) = qpu_set_cond_mul(*last_inst(c
), cond
);
75 * Some special registers can be read from either file, which lets us resolve
76 * raddr conflicts without extra MOVs.
79 swap_file(struct qpu_reg
*src
)
84 if (src
->mux
== QPU_MUX_SMALL_IMM
) {
87 if (src
->mux
== QPU_MUX_A
)
100 * This is used to resolve the fact that we might register-allocate two
101 * different operands of an instruction to the same physical register file
102 * even though instructions have only one field for the register file source
105 * In that case, we need to move one to a temporary that can be used in the
106 * instruction, instead. We reserve ra31/rb31 for this purpose.
109 fixup_raddr_conflict(struct vc4_compile
*c
,
111 struct qpu_reg
*src0
, struct qpu_reg
*src1
,
112 struct qinst
*inst
, uint64_t *unpack
)
114 uint32_t mux0
= src0
->mux
== QPU_MUX_SMALL_IMM
? QPU_MUX_B
: src0
->mux
;
115 uint32_t mux1
= src1
->mux
== QPU_MUX_SMALL_IMM
? QPU_MUX_B
: src1
->mux
;
117 if (mux0
<= QPU_MUX_R5
||
119 (src0
->addr
== src1
->addr
&&
120 src0
->mux
== src1
->mux
)) {
124 if (swap_file(src0
) || swap_file(src1
))
127 if (mux0
== QPU_MUX_A
) {
128 /* Make sure we use the same type of MOV as the instruction,
129 * in case of unpacks.
131 if (qir_is_float_input(inst
))
132 queue(c
, qpu_a_FMAX(qpu_rb(31), *src0
, *src0
));
134 queue(c
, qpu_a_MOV(qpu_rb(31), *src0
));
136 /* If we had an unpack on this A-file source, we need to put
137 * it into this MOV, not into the later move from regfile B.
139 if (inst
->src
[0].pack
) {
140 *last_inst(c
) |= *unpack
;
145 queue(c
, qpu_a_MOV(qpu_ra(31), *src0
));
151 set_last_dst_pack(struct vc4_compile
*c
, struct qinst
*inst
)
153 bool had_pm
= *last_inst(c
) & QPU_PM
;
154 bool had_ws
= *last_inst(c
) & QPU_WS
;
155 uint32_t unpack
= QPU_GET_FIELD(*last_inst(c
), QPU_UNPACK
);
160 *last_inst(c
) |= QPU_SET_FIELD(inst
->dst
.pack
, QPU_PACK
);
162 if (qir_is_mul(inst
)) {
163 assert(!unpack
|| had_pm
);
164 *last_inst(c
) |= QPU_PM
;
166 assert(!unpack
|| !had_pm
);
167 assert(!had_ws
); /* dst must be a-file to pack. */
172 handle_r4_qpu_write(struct vc4_compile
*c
, struct qinst
*qinst
,
175 if (dst
.mux
!= QPU_MUX_R4
)
176 queue(c
, qpu_a_MOV(dst
, qpu_r4()));
178 queue(c
, qpu_a_MOV(qpu_ra(QPU_W_NOP
), qpu_r4()));
182 vc4_generate_code(struct vc4_context
*vc4
, struct vc4_compile
*c
)
184 struct qpu_reg
*temp_registers
= vc4_register_allocate(vc4
, c
);
185 uint32_t inputs_remaining
= c
->num_inputs
;
186 uint32_t vpm_read_fifo_count
= 0;
187 uint32_t vpm_read_offset
= 0;
188 int last_vpm_read_index
= -1;
190 list_inithead(&c
->qpu_inst_list
);
195 /* There's a 4-entry FIFO for VPMVCD reads, each of which can
196 * load up to 16 dwords (4 vec4s) per vertex.
198 while (inputs_remaining
) {
199 uint32_t num_entries
= MIN2(inputs_remaining
, 16);
200 queue(c
, qpu_load_imm_ui(qpu_vrsetup(),
203 ((num_entries
& 0xf) << 20)));
204 inputs_remaining
-= num_entries
;
205 vpm_read_offset
+= num_entries
;
206 vpm_read_fifo_count
++;
208 assert(vpm_read_fifo_count
<= 4);
210 queue(c
, qpu_load_imm_ui(qpu_vwsetup(), 0x00001a00));
216 qir_for_each_inst_inorder(qinst
, c
) {
218 fprintf(stderr
, "translating qinst to qpu: ");
219 qir_dump_inst(qinst
);
220 fprintf(stderr
, "\n");
223 static const struct {
226 #define A(name) [QOP_##name] = {QPU_A_##name}
227 #define M(name) [QOP_##name] = {QPU_M_##name}
256 /* If we replicate src[0] out to src[1], this works
257 * out the same as a MOV.
259 [QOP_MOV
] = { QPU_A_OR
},
260 [QOP_FMOV
] = { QPU_A_FMAX
},
261 [QOP_MMOV
] = { QPU_M_V8MIN
},
265 struct qpu_reg src
[4];
266 for (int i
= 0; i
< qir_get_op_nsrc(qinst
->op
); i
++) {
267 int index
= qinst
->src
[i
].index
;
268 switch (qinst
->src
[i
].file
) {
274 src
[i
] = temp_registers
[index
];
275 if (qinst
->src
[i
].pack
) {
277 unpack
== qinst
->src
[i
].pack
);
278 unpack
= QPU_SET_FIELD(qinst
->src
[i
].pack
,
280 if (src
[i
].mux
== QPU_MUX_R4
)
290 case QFILE_SMALL_IMM
:
291 src
[i
].mux
= QPU_MUX_SMALL_IMM
;
292 src
[i
].addr
= qpu_encode_small_immediate(qinst
->src
[i
].index
);
293 /* This should only have returned a valid
294 * small immediate field, not ~0 for failure.
296 assert(src
[i
].addr
<= 47);
299 assert((int)qinst
->src
[i
].index
>=
300 last_vpm_read_index
);
301 (void)last_vpm_read_index
;
302 last_vpm_read_index
= qinst
->src
[i
].index
;
303 src
[i
] = qpu_ra(QPU_R_VPM
);
307 src
[i
] = qpu_ra(QPU_R_XY_PIXEL_COORD
);
310 src
[i
] = qpu_rb(QPU_R_XY_PIXEL_COORD
);
312 case QFILE_FRAG_REV_FLAG
:
313 src
[i
] = qpu_rb(QPU_R_MS_REV_FLAGS
);
316 case QFILE_TLB_COLOR_WRITE
:
317 case QFILE_TLB_COLOR_WRITE_MS
:
318 case QFILE_TLB_Z_WRITE
:
319 case QFILE_TLB_STENCIL_SETUP
:
320 unreachable("bad qir src file");
325 switch (qinst
->dst
.file
) {
327 dst
= qpu_ra(QPU_W_NOP
);
330 dst
= temp_registers
[qinst
->dst
.index
];
333 dst
= qpu_ra(QPU_W_VPM
);
336 case QFILE_TLB_COLOR_WRITE
:
340 case QFILE_TLB_COLOR_WRITE_MS
:
344 case QFILE_TLB_Z_WRITE
:
345 dst
= qpu_ra(QPU_W_TLB_Z
);
348 case QFILE_TLB_STENCIL_SETUP
:
349 dst
= qpu_ra(QPU_W_TLB_STENCIL_SETUP
);
354 case QFILE_SMALL_IMM
:
358 case QFILE_FRAG_REV_FLAG
:
359 assert(!"not reached");
363 bool handled_qinst_cond
= false;
372 queue(c
, qpu_a_MOV(qpu_rb(QPU_W_SFU_RECIP
),
376 queue(c
, qpu_a_MOV(qpu_rb(QPU_W_SFU_RECIPSQRT
),
380 queue(c
, qpu_a_MOV(qpu_rb(QPU_W_SFU_EXP
),
384 queue(c
, qpu_a_MOV(qpu_rb(QPU_W_SFU_LOG
),
391 handle_r4_qpu_write(c
, qinst
, dst
);
396 assert(qinst
->src
[0].file
== QFILE_LOAD_IMM
);
397 queue(c
, qpu_load_imm_ui(dst
, qinst
->src
[0].index
));
401 src
[1] = qpu_ra(QPU_R_MS_REV_FLAGS
);
402 fixup_raddr_conflict(c
, dst
, &src
[0], &src
[1],
404 queue(c
, qpu_a_AND(qpu_ra(QPU_W_MS_FLAGS
),
405 src
[0], src
[1]) | unpack
);
410 /* QOP_FRAG_Z/W don't emit instructions, just allocate
411 * the register to the Z/W payload.
415 case QOP_TLB_COLOR_READ
:
417 *last_inst(c
) = qpu_set_sig(*last_inst(c
),
419 handle_r4_qpu_write(c
, qinst
, dst
);
423 queue(c
, qpu_a_FADD(dst
, src
[0], qpu_r5()) | unpack
);
430 queue(c
, qpu_a_MOV(qpu_rb(QPU_W_TMU0_S
+
431 (qinst
->op
- QOP_TEX_S
)),
436 fixup_raddr_conflict(c
, dst
, &src
[0], &src
[1],
438 queue(c
, qpu_a_ADD(qpu_rb(QPU_W_TMU0_S
),
439 src
[0], src
[1]) | unpack
);
444 *last_inst(c
) = qpu_set_sig(*last_inst(c
),
446 handle_r4_qpu_write(c
, qinst
, dst
);
450 /* The branch target will be updated at QPU scheduling
453 queue(c
, (qpu_branch(qinst
->cond
, 0) |
455 handled_qinst_cond
= true;
459 assert(qinst
->op
< ARRAY_SIZE(translate
));
460 assert(translate
[qinst
->op
].op
!= 0); /* NOPs */
462 /* Skip emitting the MOV if it's a no-op. */
463 if (qir_is_raw_mov(qinst
) &&
464 dst
.mux
== src
[0].mux
&& dst
.addr
== src
[0].addr
) {
468 /* If we have only one source, put it in the second
469 * argument slot as well so that we don't take up
470 * another raddr just to get unused data.
472 if (qir_get_op_nsrc(qinst
->op
) == 1)
475 fixup_raddr_conflict(c
, dst
, &src
[0], &src
[1],
478 if (qir_is_mul(qinst
)) {
479 queue(c
, qpu_m_alu2(translate
[qinst
->op
].op
,
481 src
[0], src
[1]) | unpack
);
482 set_last_cond_mul(c
, qinst
->cond
);
484 queue(c
, qpu_a_alu2(translate
[qinst
->op
].op
,
486 src
[0], src
[1]) | unpack
);
487 set_last_cond_add(c
, qinst
->cond
);
489 handled_qinst_cond
= true;
490 set_last_dst_pack(c
, qinst
);
495 assert(qinst
->cond
== QPU_COND_ALWAYS
||
499 *last_inst(c
) |= QPU_SF
;
502 uint32_t cycles
= qpu_schedule_instructions(c
);
503 uint32_t inst_count_at_schedule_time
= c
->qpu_inst_count
;
505 /* thread end can't have VPM write or read */
506 if (QPU_GET_FIELD(c
->qpu_insts
[c
->qpu_inst_count
- 1],
507 QPU_WADDR_ADD
) == QPU_W_VPM
||
508 QPU_GET_FIELD(c
->qpu_insts
[c
->qpu_inst_count
- 1],
509 QPU_WADDR_MUL
) == QPU_W_VPM
||
510 QPU_GET_FIELD(c
->qpu_insts
[c
->qpu_inst_count
- 1],
511 QPU_RADDR_A
) == QPU_R_VPM
||
512 QPU_GET_FIELD(c
->qpu_insts
[c
->qpu_inst_count
- 1],
513 QPU_RADDR_B
) == QPU_R_VPM
) {
514 qpu_serialize_one_inst(c
, qpu_NOP());
517 /* thread end can't have uniform read */
518 if (QPU_GET_FIELD(c
->qpu_insts
[c
->qpu_inst_count
- 1],
519 QPU_RADDR_A
) == QPU_R_UNIF
||
520 QPU_GET_FIELD(c
->qpu_insts
[c
->qpu_inst_count
- 1],
521 QPU_RADDR_B
) == QPU_R_UNIF
) {
522 qpu_serialize_one_inst(c
, qpu_NOP());
525 /* thread end can't have TLB operations */
526 if (qpu_inst_is_tlb(c
->qpu_insts
[c
->qpu_inst_count
- 1]))
527 qpu_serialize_one_inst(c
, qpu_NOP());
529 /* Make sure there's no existing signal set (like for a small
532 if (QPU_GET_FIELD(c
->qpu_insts
[c
->qpu_inst_count
- 1],
533 QPU_SIG
) != QPU_SIG_NONE
) {
534 qpu_serialize_one_inst(c
, qpu_NOP());
537 c
->qpu_insts
[c
->qpu_inst_count
- 1] =
538 qpu_set_sig(c
->qpu_insts
[c
->qpu_inst_count
- 1],
540 qpu_serialize_one_inst(c
, qpu_NOP());
541 qpu_serialize_one_inst(c
, qpu_NOP());
548 c
->qpu_insts
[c
->qpu_inst_count
- 1] =
549 qpu_set_sig(c
->qpu_insts
[c
->qpu_inst_count
- 1],
550 QPU_SIG_SCOREBOARD_UNLOCK
);
554 cycles
+= c
->qpu_inst_count
- inst_count_at_schedule_time
;
556 if (vc4_debug
& VC4_DEBUG_SHADERDB
) {
557 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %d estimated cycles\n",
558 qir_get_stage_name(c
->stage
),
559 c
->program_id
, c
->variant_id
,
563 if (vc4_debug
& VC4_DEBUG_QPU
)
566 vc4_qpu_validate(c
->qpu_insts
, c
->qpu_inst_count
);
568 free(temp_registers
);