2 * Copyright © 2014 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "vc4_context.h"
29 #include "util/ralloc.h"
32 vc4_dump_program(struct vc4_compile
*c
)
34 fprintf(stderr
, "%s prog %d/%d QPU:\n",
35 qir_get_stage_name(c
->stage
),
36 c
->program_id
, c
->variant_id
);
38 for (int i
= 0; i
< c
->qpu_inst_count
; i
++) {
39 fprintf(stderr
, "0x%016"PRIx64
" ", c
->qpu_insts
[i
]);
40 vc4_qpu_disasm(&c
->qpu_insts
[i
], 1);
41 fprintf(stderr
, "\n");
46 queue(struct vc4_compile
*c
, uint64_t inst
)
48 struct queued_qpu_inst
*q
= rzalloc(c
, struct queued_qpu_inst
);
50 insert_at_tail(&c
->qpu_inst_list
, &q
->link
);
54 last_inst(struct vc4_compile
*c
)
56 struct queued_qpu_inst
*q
=
57 (struct queued_qpu_inst
*)last_elem(&c
->qpu_inst_list
);
62 set_last_cond_add(struct vc4_compile
*c
, uint32_t cond
)
64 *last_inst(c
) = qpu_set_cond_add(*last_inst(c
), cond
);
68 * Some special registers can be read from either file, which lets us resolve
69 * raddr conflicts without extra MOVs.
72 swap_file(struct qpu_reg
*src
)
77 if (src
->mux
== QPU_MUX_A
)
89 * This is used to resolve the fact that we might register-allocate two
90 * different operands of an instruction to the same physical register file
91 * even though instructions have only one field for the register file source
94 * In that case, we need to move one to a temporary that can be used in the
95 * instruction, instead.
98 fixup_raddr_conflict(struct vc4_compile
*c
,
100 struct qpu_reg
*src0
, struct qpu_reg
*src1
,
103 if ((src0
->mux
!= QPU_MUX_A
&& src0
->mux
!= QPU_MUX_B
) ||
104 src0
->mux
!= src1
->mux
||
105 src0
->addr
== src1
->addr
) {
109 if (swap_file(src0
) || swap_file(src1
))
112 if (src0
->mux
== QPU_MUX_A
) {
113 /* If we're conflicting over the A regfile, then we can just
114 * use the reserved rb31.
116 queue(c
, qpu_a_MOV(qpu_rb(31), *src1
));
120 /* Otherwise, we need a non-B regfile. So, we spill r3 out to
121 * rb31, then store our desired value in r3, and tell the
122 * caller to put rb31 back into r3 when we're done.
125 queue(c
, qpu_a_MOV(qpu_rb(31), qpu_r3()));
126 queue(c
, qpu_a_MOV(qpu_r3(), *src1
));
130 return r3_live
&& dst
.mux
!= QPU_MUX_R3
;
135 vc4_generate_code(struct vc4_context
*vc4
, struct vc4_compile
*c
)
137 struct qpu_reg
*temp_registers
= vc4_register_allocate(vc4
, c
);
138 bool discard
= false;
139 uint32_t inputs_remaining
= c
->num_inputs
;
140 uint32_t vpm_read_fifo_count
= 0;
141 uint32_t vpm_read_offset
= 0;
142 bool written_r3
= false;
145 make_empty_list(&c
->qpu_inst_list
);
150 /* There's a 4-entry FIFO for VPMVCD reads, each of which can
151 * load up to 16 dwords (4 vec4s) per vertex.
153 while (inputs_remaining
) {
154 uint32_t num_entries
= MIN2(inputs_remaining
, 16);
155 queue(c
, qpu_load_imm_ui(qpu_vrsetup(),
158 ((num_entries
& 0xf) << 20)));
159 inputs_remaining
-= num_entries
;
160 vpm_read_offset
+= num_entries
;
161 vpm_read_fifo_count
++;
163 assert(vpm_read_fifo_count
<= 4);
165 queue(c
, qpu_load_imm_ui(qpu_vwsetup(), 0x00001a00));
171 struct simple_node
*node
;
172 foreach(node
, &c
->instructions
) {
173 struct qinst
*qinst
= (struct qinst
*)node
;
176 fprintf(stderr
, "translating qinst to qpu: ");
177 qir_dump_inst(qinst
);
178 fprintf(stderr
, "\n");
181 static const struct {
185 #define A(name) [QOP_##name] = {QPU_A_##name, false}
186 #define M(name) [QOP_##name] = {QPU_M_##name, true}
211 struct qpu_reg src
[4];
212 for (int i
= 0; i
< qir_get_op_nsrc(qinst
->op
); i
++) {
213 int index
= qinst
->src
[i
].index
;
214 switch (qinst
->src
[i
].file
) {
219 src
[i
] = temp_registers
[index
];
231 switch (qinst
->dst
.file
) {
233 dst
= qpu_ra(QPU_W_NOP
);
236 dst
= temp_registers
[qinst
->dst
.index
];
240 assert(!"not reached");
246 /* Skip emitting the MOV if it's a no-op. */
247 if (dst
.mux
== QPU_MUX_A
|| dst
.mux
== QPU_MUX_B
||
248 dst
.mux
!= src
[0].mux
|| dst
.addr
!= src
[0].addr
) {
249 queue(c
, qpu_a_MOV(dst
, src
[0]));
254 queue(c
, qpu_a_MOV(qpu_ra(QPU_W_NOP
), src
[0]));
255 *last_inst(c
) |= QPU_SF
;
262 queue(c
, qpu_a_MOV(dst
, src
[0]));
263 set_last_cond_add(c
, qinst
->op
- QOP_SEL_X_0_ZS
+
266 queue(c
, qpu_a_XOR(dst
, qpu_r0(), qpu_r0()));
267 set_last_cond_add(c
, ((qinst
->op
- QOP_SEL_X_0_ZS
) ^
275 queue(c
, qpu_a_MOV(dst
, src
[0]));
276 set_last_cond_add(c
, qinst
->op
- QOP_SEL_X_Y_ZS
+
279 queue(c
, qpu_a_MOV(dst
, src
[1]));
280 set_last_cond_add(c
, ((qinst
->op
- QOP_SEL_X_Y_ZS
) ^
286 queue(c
, qpu_a_MOV(qpu_ra(QPU_W_VPM
), src
[0]));
290 queue(c
, qpu_a_MOV(dst
, qpu_ra(QPU_R_VPM
)));
299 queue(c
, qpu_a_MOV(qpu_rb(QPU_W_SFU_RECIP
),
303 queue(c
, qpu_a_MOV(qpu_rb(QPU_W_SFU_RECIPSQRT
),
307 queue(c
, qpu_a_MOV(qpu_rb(QPU_W_SFU_EXP
),
311 queue(c
, qpu_a_MOV(qpu_rb(QPU_W_SFU_LOG
),
318 queue(c
, qpu_a_MOV(dst
, qpu_r4()));
322 case QOP_PACK_COLORS
: {
323 /* We have to be careful not to start writing over one
324 * of our source values when incrementally writing the
325 * destination. So, if the dst is one of the srcs, we
326 * pack that one first (and we pack 4 channels at once
327 * for the first pack).
329 struct qpu_reg first_pack
= src
[0];
330 for (int i
= 0; i
< 4; i
++) {
331 if (src
[i
].mux
== dst
.mux
&&
332 src
[i
].addr
== dst
.addr
) {
337 queue(c
, qpu_m_MOV(dst
, first_pack
));
338 *last_inst(c
) |= QPU_PM
;
339 *last_inst(c
) |= QPU_SET_FIELD(QPU_PACK_MUL_8888
,
342 for (int i
= 0; i
< 4; i
++) {
343 if (src
[i
].mux
== first_pack
.mux
&&
344 src
[i
].addr
== first_pack
.addr
) {
348 queue(c
, qpu_m_MOV(dst
, src
[i
]));
349 *last_inst(c
) |= QPU_PM
;
350 *last_inst(c
) |= QPU_SET_FIELD(QPU_PACK_MUL_8A
+ i
,
358 queue(c
, qpu_a_ITOF(dst
,
359 qpu_ra(QPU_R_XY_PIXEL_COORD
)));
363 queue(c
, qpu_a_ITOF(dst
,
364 qpu_rb(QPU_R_XY_PIXEL_COORD
)));
367 case QOP_FRAG_REV_FLAG
:
368 queue(c
, qpu_a_ITOF(dst
,
369 qpu_rb(QPU_R_MS_REV_FLAGS
)));
374 /* QOP_FRAG_Z/W don't emit instructions, just allocate
375 * the register to the Z/W payload.
379 case QOP_TLB_DISCARD_SETUP
:
381 queue(c
, qpu_a_MOV(src
[0], src
[0]));
382 *last_inst(c
) |= QPU_SF
;
385 case QOP_TLB_STENCIL_SETUP
:
386 queue(c
, qpu_a_MOV(qpu_ra(QPU_W_TLB_STENCIL_SETUP
), src
[0]));
389 case QOP_TLB_Z_WRITE
:
390 queue(c
, qpu_a_MOV(qpu_ra(QPU_W_TLB_Z
), src
[0]));
392 set_last_cond_add(c
, QPU_COND_ZS
);
396 case QOP_TLB_COLOR_READ
:
398 *last_inst(c
) = qpu_set_sig(*last_inst(c
),
403 case QOP_TLB_COLOR_WRITE
:
404 queue(c
, qpu_a_MOV(qpu_tlbc(), src
[0]));
406 set_last_cond_add(c
, QPU_COND_ZS
);
411 queue(c
, qpu_a_FADD(dst
, src
[0], qpu_r5()));
414 case QOP_PACK_SCALED
: {
415 uint64_t a
= (qpu_a_MOV(dst
, src
[0]) |
416 QPU_SET_FIELD(QPU_PACK_A_16A
,
418 uint64_t b
= (qpu_a_MOV(dst
, src
[1]) |
419 QPU_SET_FIELD(QPU_PACK_A_16B
,
422 if (dst
.mux
== src
[1].mux
&& dst
.addr
== src
[1].addr
) {
436 queue(c
, qpu_a_MOV(qpu_rb(QPU_W_TMU0_S
+
437 (qinst
->op
- QOP_TEX_S
)),
442 needs_restore
= fixup_raddr_conflict(c
, dst
,
445 queue(c
, qpu_a_ADD(qpu_rb(QPU_W_TMU0_S
), src
[0], src
[1]));
447 queue(c
, qpu_a_MOV(qpu_r3(), qpu_rb(31)));
452 *last_inst(c
) = qpu_set_sig(*last_inst(c
),
457 case QOP_R4_UNPACK_A
:
458 case QOP_R4_UNPACK_B
:
459 case QOP_R4_UNPACK_C
:
460 case QOP_R4_UNPACK_D
:
461 assert(src
[0].mux
== QPU_MUX_R4
);
462 queue(c
, qpu_a_MOV(dst
, src
[0]));
463 *last_inst(c
) |= QPU_PM
;
464 *last_inst(c
) |= QPU_SET_FIELD(QPU_UNPACK_8A
+
471 case QOP_UNPACK_8A_F
:
472 case QOP_UNPACK_8B_F
:
473 case QOP_UNPACK_8C_F
:
474 case QOP_UNPACK_8D_F
:
475 assert(src
[0].mux
== QPU_MUX_A
);
477 /* Since we're setting the pack bits, if the
478 * destination is in A it would get re-packed.
480 queue(c
, qpu_a_FMAX((dst
.mux
== QPU_MUX_A
?
483 *last_inst(c
) |= QPU_SET_FIELD(QPU_UNPACK_8A
+
488 if (dst
.mux
== QPU_MUX_A
) {
489 queue(c
, qpu_a_MOV(dst
, qpu_rb(31)));
494 assert(qinst
->op
< ARRAY_SIZE(translate
));
495 assert(translate
[qinst
->op
].op
!= 0); /* NOPs */
497 /* If we have only one source, put it in the second
498 * argument slot as well so that we don't take up
499 * another raddr just to get unused data.
501 if (qir_get_op_nsrc(qinst
->op
) == 1)
504 needs_restore
= fixup_raddr_conflict(c
, dst
,
508 if (translate
[qinst
->op
].is_mul
) {
509 queue(c
, qpu_m_alu2(translate
[qinst
->op
].op
,
513 queue(c
, qpu_a_alu2(translate
[qinst
->op
].op
,
518 queue(c
, qpu_a_MOV(qpu_r3(), qpu_rb(31)));
523 if (dst
.mux
== QPU_MUX_R3
)
527 qpu_schedule_instructions(c
);
529 /* thread end can't have VPM write or read */
530 if (QPU_GET_FIELD(c
->qpu_insts
[c
->qpu_inst_count
- 1],
531 QPU_WADDR_ADD
) == QPU_W_VPM
||
532 QPU_GET_FIELD(c
->qpu_insts
[c
->qpu_inst_count
- 1],
533 QPU_WADDR_MUL
) == QPU_W_VPM
||
534 QPU_GET_FIELD(c
->qpu_insts
[c
->qpu_inst_count
- 1],
535 QPU_RADDR_A
) == QPU_R_VPM
||
536 QPU_GET_FIELD(c
->qpu_insts
[c
->qpu_inst_count
- 1],
537 QPU_RADDR_B
) == QPU_R_VPM
) {
538 qpu_serialize_one_inst(c
, qpu_NOP());
541 /* thread end can't have uniform read */
542 if (QPU_GET_FIELD(c
->qpu_insts
[c
->qpu_inst_count
- 1],
543 QPU_RADDR_A
) == QPU_R_UNIF
||
544 QPU_GET_FIELD(c
->qpu_insts
[c
->qpu_inst_count
- 1],
545 QPU_RADDR_B
) == QPU_R_UNIF
) {
546 qpu_serialize_one_inst(c
, qpu_NOP());
549 /* thread end can't have TLB operations */
550 if (qpu_inst_is_tlb(c
->qpu_insts
[c
->qpu_inst_count
- 1]))
551 qpu_serialize_one_inst(c
, qpu_NOP());
553 c
->qpu_insts
[c
->qpu_inst_count
- 1] =
554 qpu_set_sig(c
->qpu_insts
[c
->qpu_inst_count
- 1],
556 qpu_serialize_one_inst(c
, qpu_NOP());
557 qpu_serialize_one_inst(c
, qpu_NOP());
564 c
->qpu_insts
[c
->qpu_inst_count
- 1] =
565 qpu_set_sig(c
->qpu_insts
[c
->qpu_inst_count
- 1],
566 QPU_SIG_SCOREBOARD_UNLOCK
);
570 if (vc4_debug
& VC4_DEBUG_QPU
)
573 vc4_qpu_validate(c
->qpu_insts
, c
->qpu_inst_count
);
575 free(temp_registers
);