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vc4: Add support for depth clears and tests within a tile.
[mesa.git] / src / gallium / drivers / vc4 / vc4_qpu_emit.c
1 /*
2 * Copyright © 2014 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <stdio.h>
25 #include <inttypes.h>
26
27 #include "vc4_context.h"
28 #include "vc4_qir.h"
29 #include "vc4_qpu.h"
30
31 static void
32 vc4_dump_program(struct qcompile *c)
33 {
34 fprintf(stderr, "%s:\n", qir_get_stage_name(c->stage));
35
36 for (int i = 0; i < c->qpu_inst_count; i++) {
37 fprintf(stderr, "0x%016"PRIx64" ", c->qpu_insts[i]);
38 vc4_qpu_disasm(&c->qpu_insts[i], 1);
39 fprintf(stderr, "\n");
40 }
41 }
42
43 struct queued_qpu_inst {
44 struct simple_node link;
45 uint64_t inst;
46 };
47
48 static void
49 queue(struct qcompile *c, uint64_t inst)
50 {
51 struct queued_qpu_inst *q = calloc(1, sizeof(*q));
52 q->inst = inst;
53 insert_at_tail(&c->qpu_inst_list, &q->link);
54 }
55
56 static uint64_t *
57 last_inst(struct qcompile *c)
58 {
59 struct queued_qpu_inst *q =
60 (struct queued_qpu_inst *)last_elem(&c->qpu_inst_list);
61 return &q->inst;
62 }
63
64 /**
65 * This is used to resolve the fact that we might register-allocate two
66 * different operands of an instruction to the same physical register file
67 * even though instructions have only one field for the register file source
68 * address.
69 *
70 * In that case, we need to move one to a temporary that can be used in the
71 * instruction, instead.
72 */
73 static void
74 fixup_raddr_conflict(struct qcompile *c,
75 struct qpu_reg src0, struct qpu_reg *src1)
76 {
77 if ((src0.mux == QPU_MUX_A || src0.mux == QPU_MUX_B) &&
78 (src1->mux == QPU_MUX_A || src1->mux == QPU_MUX_B) &&
79 src0.addr != src1->addr) {
80 queue(c, qpu_inst(qpu_a_MOV(qpu_r3(), *src1),
81 qpu_m_NOP()));
82 *src1 = qpu_r3();
83 }
84 }
85
86 static void
87 serialize_one_inst(struct qcompile *c, uint64_t inst)
88 {
89 if (c->qpu_inst_count >= c->qpu_inst_size) {
90 c->qpu_inst_size = MAX2(16, c->qpu_inst_size * 2);
91 c->qpu_insts = realloc(c->qpu_insts,
92 c->qpu_inst_size * sizeof(uint64_t));
93 }
94 c->qpu_insts[c->qpu_inst_count++] = inst;
95 }
96
97 static void
98 serialize_insts(struct qcompile *c)
99 {
100 int last_sfu_write = -10;
101
102 while (!is_empty_list(&c->qpu_inst_list)) {
103 struct queued_qpu_inst *q =
104 (struct queued_qpu_inst *)first_elem(&c->qpu_inst_list);
105 uint32_t last_waddr_a = QPU_W_NOP, last_waddr_b = QPU_W_NOP;
106 uint32_t raddr_a = QPU_GET_FIELD(q->inst, QPU_RADDR_A);
107 uint32_t raddr_b = QPU_GET_FIELD(q->inst, QPU_RADDR_B);
108
109 if (c->qpu_inst_count > 0) {
110 uint64_t last_inst = c->qpu_insts[c->qpu_inst_count -
111 1];
112 uint32_t last_waddr_add = QPU_GET_FIELD(last_inst,
113 QPU_WADDR_ADD);
114 uint32_t last_waddr_mul = QPU_GET_FIELD(last_inst,
115 QPU_WADDR_MUL);
116
117 if (last_inst & QPU_WS) {
118 last_waddr_a = last_waddr_mul;
119 last_waddr_b = last_waddr_add;
120 } else {
121 last_waddr_a = last_waddr_add;
122 last_waddr_b = last_waddr_mul;
123 }
124 }
125
126 uint32_t src_muxes[] = {
127 QPU_GET_FIELD(q->inst, QPU_ADD_A),
128 QPU_GET_FIELD(q->inst, QPU_ADD_B),
129 QPU_GET_FIELD(q->inst, QPU_MUL_A),
130 QPU_GET_FIELD(q->inst, QPU_MUL_B),
131 };
132
133 /* "An instruction must not read from a location in physical
134 * regfile A or B that was written to by the previous
135 * instruction."
136 */
137 bool needs_raddr_vs_waddr_nop = false;
138 bool reads_r4 = false;
139 for (int i = 0; i < ARRAY_SIZE(src_muxes); i++) {
140 if ((raddr_a < 32 &&
141 src_muxes[i] == QPU_MUX_A &&
142 last_waddr_a == raddr_a) ||
143 (raddr_b < 32 &&
144 src_muxes[i] == QPU_MUX_B &&
145 last_waddr_b == raddr_b)) {
146 needs_raddr_vs_waddr_nop = true;
147 }
148 if (src_muxes[i] == QPU_MUX_R4)
149 reads_r4 = true;
150 }
151
152 if (needs_raddr_vs_waddr_nop) {
153 serialize_one_inst(c, qpu_inst(qpu_a_NOP(),
154 qpu_m_NOP()));
155 }
156
157 /* "After an SFU lookup instruction, accumulator r4 must not
158 * be read in the following two instructions. Any other
159 * instruction that results in r4 being written (that is, TMU
160 * read, TLB read, SFU lookup) cannot occur in the two
161 * instructions following an SFU lookup."
162 */
163 if (reads_r4) {
164 while (c->qpu_inst_count - last_sfu_write < 3) {
165 serialize_one_inst(c, qpu_inst(qpu_a_NOP(),
166 qpu_m_NOP()));
167 }
168 }
169
170 uint32_t waddr_a = QPU_GET_FIELD(q->inst, QPU_WADDR_ADD);
171 uint32_t waddr_m = QPU_GET_FIELD(q->inst, QPU_WADDR_MUL);
172 if ((waddr_a >= QPU_W_SFU_RECIP && waddr_a <= QPU_W_SFU_LOG) ||
173 (waddr_m >= QPU_W_SFU_RECIP && waddr_m <= QPU_W_SFU_LOG)) {
174 last_sfu_write = c->qpu_inst_count;
175 }
176
177 serialize_one_inst(c, q->inst);
178
179 remove_from_list(&q->link);
180 free(q);
181 }
182 }
183
184 void
185 vc4_generate_code(struct qcompile *c)
186 {
187 struct qpu_reg allocate_to_qpu_reg[3 + 32 + 32];
188 bool reg_in_use[ARRAY_SIZE(allocate_to_qpu_reg)];
189 int *reg_allocated = calloc(c->num_temps, sizeof(*reg_allocated));
190 int *reg_uses_remaining =
191 calloc(c->num_temps, sizeof(*reg_uses_remaining));
192
193 for (int i = 0; i < ARRAY_SIZE(reg_in_use); i++)
194 reg_in_use[i] = false;
195 for (int i = 0; i < c->num_temps; i++)
196 reg_allocated[i] = -1;
197 for (int i = 0; i < 3; i++)
198 allocate_to_qpu_reg[i] = qpu_rn(i);
199 for (int i = 0; i < 32; i++)
200 allocate_to_qpu_reg[i + 3] = qpu_ra(i);
201 for (int i = 0; i < 32; i++)
202 allocate_to_qpu_reg[i + 3 + 32] = qpu_rb(i);
203
204 make_empty_list(&c->qpu_inst_list);
205
206 struct simple_node *node;
207 foreach(node, &c->instructions) {
208 struct qinst *qinst = (struct qinst *)node;
209
210 if (qinst->dst.file == QFILE_TEMP)
211 reg_uses_remaining[qinst->dst.index]++;
212 for (int i = 0; i < qir_get_op_nsrc(qinst->op); i++) {
213 if (qinst->src[i].file == QFILE_TEMP)
214 reg_uses_remaining[qinst->src[i].index]++;
215 }
216 if (qinst->op == QOP_TLB_PASSTHROUGH_Z_WRITE)
217 reg_in_use[3 + 32 + QPU_R_FRAG_PAYLOAD_ZW] = true;
218 }
219
220 switch (c->stage) {
221 case QSTAGE_VERT:
222 case QSTAGE_COORD:
223 queue(c, qpu_load_imm_ui(qpu_vrsetup(),
224 (0x00001a00 +
225 0x00100000 * c->num_inputs)));
226 queue(c, qpu_load_imm_ui(qpu_vwsetup(), 0x00001a00));
227 break;
228 case QSTAGE_FRAG:
229 break;
230 }
231
232 foreach(node, &c->instructions) {
233 struct qinst *qinst = (struct qinst *)node;
234
235 #if 0
236 fprintf(stderr, "translating qinst to qpu: ");
237 qir_dump_inst(qinst);
238 fprintf(stderr, "\n");
239 #endif
240
241 static const struct {
242 uint32_t op;
243 bool is_mul;
244 } translate[] = {
245 #define A(name) [QOP_##name] = {QPU_A_##name, false}
246 #define M(name) [QOP_##name] = {QPU_M_##name, true}
247 A(FADD),
248 A(FSUB),
249 A(FMIN),
250 A(FMAX),
251 A(FMINABS),
252 A(FMAXABS),
253 A(FTOI),
254 A(ITOF),
255
256 M(FMUL),
257 };
258
259 static const uint32_t compareflags[] = {
260 [QOP_SEQ - QOP_SEQ] = QPU_COND_ZS,
261 [QOP_SNE - QOP_SEQ] = QPU_COND_ZC,
262 [QOP_SLT - QOP_SEQ] = QPU_COND_NS,
263 [QOP_SGE - QOP_SEQ] = QPU_COND_NC,
264 };
265
266 struct qpu_reg src[4];
267 for (int i = 0; i < qir_get_op_nsrc(qinst->op); i++) {
268 int index = qinst->src[i].index;
269 switch (qinst->src[i].file) {
270 case QFILE_NULL:
271 src[i] = qpu_rn(0);
272 break;
273 case QFILE_TEMP:
274 if (reg_allocated[index] == -1) {
275 fprintf(stderr, "undefined reg use: ");
276 qir_dump_inst(qinst);
277 fprintf(stderr, "\n");
278
279 src[i] = qpu_rn(0);
280 } else {
281 src[i] = allocate_to_qpu_reg[reg_allocated[index]];
282 reg_uses_remaining[index]--;
283 if (reg_uses_remaining[index] == 0)
284 reg_in_use[reg_allocated[index]] = false;
285 }
286 break;
287 case QFILE_UNIF:
288 src[i] = qpu_unif();
289 break;
290 case QFILE_VARY:
291 src[i] = qpu_vary();
292 break;
293 }
294 }
295
296 struct qpu_reg dst;
297 switch (qinst->dst.file) {
298 case QFILE_NULL:
299 dst = qpu_ra(QPU_W_NOP);
300 break;
301
302 case QFILE_TEMP:
303 if (reg_allocated[qinst->dst.index] == -1) {
304 int alloc;
305 for (alloc = 0;
306 alloc < ARRAY_SIZE(reg_in_use);
307 alloc++) {
308 /* The pack flags require an A-file register. */
309 if (qinst->op == QOP_PACK_SCALED &&
310 allocate_to_qpu_reg[alloc].mux != QPU_MUX_A) {
311 continue;
312 }
313
314 if (!reg_in_use[alloc])
315 break;
316 }
317 assert(alloc != ARRAY_SIZE(reg_in_use) && "need better reg alloc");
318 reg_in_use[alloc] = true;
319 reg_allocated[qinst->dst.index] = alloc;
320 }
321
322 dst = allocate_to_qpu_reg[reg_allocated[qinst->dst.index]];
323
324 reg_uses_remaining[qinst->dst.index]--;
325 if (reg_uses_remaining[qinst->dst.index] == 0) {
326 reg_in_use[reg_allocated[qinst->dst.index]] =
327 false;
328 }
329 break;
330
331 case QFILE_VARY:
332 case QFILE_UNIF:
333 assert(!"not reached");
334 break;
335 }
336
337 switch (qinst->op) {
338 case QOP_MOV:
339 /* Skip emitting the MOV if it's a no-op. */
340 if (dst.mux == QPU_MUX_A || dst.mux == QPU_MUX_B ||
341 dst.mux != src[0].mux || dst.addr != src[0].addr) {
342 queue(c, qpu_inst(qpu_a_MOV(dst, src[0]),
343 qpu_m_NOP()));
344 }
345 break;
346
347 case QOP_CMP:
348 queue(c, qpu_inst(qpu_a_MOV(qpu_ra(QPU_W_NOP),
349 src[0]),
350 qpu_m_NOP()));
351 *last_inst(c) |= QPU_SF;
352
353 if (dst.mux <= QPU_MUX_R3) {
354 fixup_raddr_conflict(c, src[1], &src[2]);
355 queue(c, qpu_inst(qpu_a_MOV(dst, src[1]),
356 qpu_m_MOV(dst, src[2])));
357 *last_inst(c) = ((*last_inst(c) & ~(QPU_COND_ADD_MASK |
358 QPU_COND_MUL_MASK))
359 | QPU_SET_FIELD(QPU_COND_NS,
360 QPU_COND_ADD)
361 | QPU_SET_FIELD(QPU_COND_NC,
362 QPU_COND_MUL));
363 } else {
364 if (dst.mux == src[1].mux &&
365 dst.addr == src[1].addr) {
366 queue(c, qpu_inst(qpu_a_MOV(dst, src[1]),
367 qpu_m_NOP()));
368
369 queue(c, qpu_inst(qpu_a_MOV(dst, src[2]),
370 qpu_m_NOP()));
371 *last_inst(c) = ((*last_inst(c) & ~(QPU_COND_ADD_MASK))
372 | QPU_SET_FIELD(QPU_COND_NC,
373 QPU_COND_ADD));
374 } else {
375 queue(c, qpu_inst(qpu_a_MOV(dst, src[2]),
376 qpu_m_NOP()));
377
378 queue(c, qpu_inst(qpu_a_MOV(dst, src[1]),
379 qpu_m_NOP()));
380 *last_inst(c) = ((*last_inst(c) & ~(QPU_COND_ADD_MASK))
381 | QPU_SET_FIELD(QPU_COND_NS,
382 QPU_COND_ADD));
383 }
384 }
385 break;
386
387 case QOP_SEQ:
388 case QOP_SNE:
389 case QOP_SGE:
390 case QOP_SLT:
391 fixup_raddr_conflict(c, src[0], &src[1]);
392 queue(c, qpu_inst(qpu_a_SUB(qpu_ra(QPU_W_NOP),
393 src[0], src[1]),
394 qpu_m_NOP()));
395 *last_inst(c) |= QPU_SF;
396
397 queue(c, qpu_load_imm_f(dst, 0.0));
398 queue(c, qpu_load_imm_f(dst, 1.0));
399 *last_inst(c) = ((*last_inst(c) & ~QPU_COND_ADD_MASK)
400 | QPU_SET_FIELD(compareflags[qinst->op - QOP_SEQ],
401 QPU_COND_ADD));
402
403 break;
404
405 case QOP_VPM_WRITE:
406 queue(c, qpu_inst(qpu_a_MOV(qpu_ra(QPU_W_VPM), src[0]),
407 qpu_m_NOP()));
408 break;
409
410 case QOP_VPM_READ:
411 queue(c, qpu_inst(qpu_a_MOV(dst, qpu_ra(QPU_R_VPM)),
412 qpu_m_NOP()));
413 break;
414
415 case QOP_RCP:
416 case QOP_RSQ:
417 case QOP_EXP2:
418 case QOP_LOG2:
419 switch (qinst->op) {
420 case QOP_RCP:
421 queue(c, qpu_inst(qpu_a_MOV(qpu_rb(QPU_W_SFU_RECIP),
422 src[0]),
423 qpu_m_NOP()));
424 break;
425 case QOP_RSQ:
426 queue(c, qpu_inst(qpu_a_MOV(qpu_rb(QPU_W_SFU_RECIPSQRT),
427 src[0]),
428 qpu_m_NOP()));
429 break;
430 case QOP_EXP2:
431 queue(c, qpu_inst(qpu_a_MOV(qpu_rb(QPU_W_SFU_EXP),
432 src[0]),
433 qpu_m_NOP()));
434 break;
435 case QOP_LOG2:
436 queue(c, qpu_inst(qpu_a_MOV(qpu_rb(QPU_W_SFU_LOG),
437 src[0]),
438 qpu_m_NOP()));
439 break;
440 default:
441 abort();
442 }
443
444 queue(c, qpu_inst(qpu_a_MOV(dst, qpu_r4()),
445 qpu_m_NOP()));
446
447 break;
448
449 case QOP_PACK_COLORS:
450 for (int i = 0; i < 4; i++) {
451 queue(c, qpu_inst(qpu_a_NOP(),
452 qpu_m_MOV(qpu_r3(), src[i])));
453 *last_inst(c) |= QPU_PM;
454 *last_inst(c) |= QPU_SET_FIELD(QPU_PACK_MUL_8A + i,
455 QPU_PACK);
456 }
457
458 queue(c, qpu_inst(qpu_a_MOV(dst, qpu_r3()),
459 qpu_m_NOP()));
460
461 break;
462
463 case QOP_TLB_PASSTHROUGH_Z_WRITE:
464 queue(c, qpu_inst(qpu_a_MOV(qpu_ra(QPU_W_TLB_Z),
465 qpu_rb(QPU_R_FRAG_PAYLOAD_ZW)),
466 qpu_m_NOP()));
467 break;
468
469 case QOP_TLB_COLOR_WRITE:
470 queue(c, qpu_inst(qpu_a_MOV(qpu_tlbc(),
471 src[0]),
472 qpu_m_NOP()));
473 break;
474
475 case QOP_VARY_ADD_C:
476 queue(c, qpu_inst(qpu_a_FADD(dst,
477 src[0], qpu_r5()),
478 qpu_m_NOP()));
479 break;
480
481 case QOP_PACK_SCALED: {
482 uint64_t a = (qpu_inst(qpu_a_MOV(dst, src[0]),
483 qpu_m_NOP()) |
484 QPU_SET_FIELD(QPU_PACK_A_16A,
485 QPU_PACK));
486 uint64_t b = (qpu_inst(qpu_a_MOV(dst, src[1]),
487 qpu_m_NOP()) |
488 QPU_SET_FIELD(QPU_PACK_A_16B,
489 QPU_PACK));
490
491 if (dst.mux == src[1].mux && dst.addr == src[1].addr) {
492 queue(c, b);
493 queue(c, a);
494 } else {
495 queue(c, a);
496 queue(c, b);
497 }
498 break;
499 }
500
501 case QOP_TEX_S:
502 case QOP_TEX_T:
503 case QOP_TEX_R:
504 case QOP_TEX_B:
505 queue(c, qpu_inst(qpu_a_MOV(qpu_rb(QPU_W_TMU0_S +
506 (qinst->op -
507 QOP_TEX_S)),
508 src[0]),
509 qpu_m_NOP()));
510 break;
511
512 case QOP_TEX_RESULT:
513 queue(c, qpu_inst(qpu_a_NOP(), qpu_m_NOP()));
514 *last_inst(c) = qpu_set_sig(*last_inst(c),
515 QPU_SIG_LOAD_TMU0);
516
517 break;
518
519 case QOP_R4_UNPACK_A:
520 case QOP_R4_UNPACK_B:
521 case QOP_R4_UNPACK_C:
522 case QOP_R4_UNPACK_D:
523 queue(c, qpu_inst(qpu_a_MOV(dst, qpu_r4()),
524 qpu_m_NOP()));
525 *last_inst(c) |= QPU_PM;
526 *last_inst(c) |= QPU_SET_FIELD(QPU_UNPACK_R4_8A +
527 (qinst->op -
528 QOP_R4_UNPACK_A),
529 QPU_UNPACK);
530
531 break;
532
533 default:
534 assert(qinst->op < ARRAY_SIZE(translate));
535 assert(translate[qinst->op].op != 0); /* NOPs */
536
537 /* If we have only one source, put it in the second
538 * argument slot as well so that we don't take up
539 * another raddr just to get unused data.
540 */
541 if (qir_get_op_nsrc(qinst->op) == 1)
542 src[1] = src[0];
543
544 fixup_raddr_conflict(c, src[0], &src[1]);
545
546 if (translate[qinst->op].is_mul) {
547 queue(c, qpu_inst(qpu_a_NOP(),
548 qpu_m_alu2(translate[qinst->op].op,
549 dst,
550 src[0], src[1])));
551 } else {
552 queue(c, qpu_inst(qpu_a_alu2(translate[qinst->op].op,
553 dst,
554 src[0], src[1]),
555 qpu_m_NOP()));
556 }
557 break;
558 }
559 }
560
561 serialize_insts(c);
562
563 /* thread end can't have VPM write */
564 if (QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
565 QPU_WADDR_ADD) == QPU_W_VPM ||
566 QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
567 QPU_WADDR_MUL) == QPU_W_VPM) {
568 serialize_one_inst(c, qpu_inst(qpu_a_NOP(), qpu_m_NOP()));
569 }
570
571 c->qpu_insts[c->qpu_inst_count - 1] =
572 qpu_set_sig(c->qpu_insts[c->qpu_inst_count - 1],
573 QPU_SIG_PROG_END);
574 serialize_one_inst(c, qpu_inst(qpu_a_NOP(), qpu_m_NOP()));
575 serialize_one_inst(c, qpu_inst(qpu_a_NOP(), qpu_m_NOP()));
576
577 switch (c->stage) {
578 case QSTAGE_VERT:
579 case QSTAGE_COORD:
580 break;
581 case QSTAGE_FRAG:
582 c->qpu_insts[2] = qpu_set_sig(c->qpu_insts[2],
583 QPU_SIG_WAIT_FOR_SCOREBOARD);
584 c->qpu_insts[c->qpu_inst_count - 1] =
585 qpu_set_sig(c->qpu_insts[c->qpu_inst_count - 1],
586 QPU_SIG_SCOREBOARD_UNLOCK);
587 break;
588 }
589
590 if (vc4_debug & VC4_DEBUG_QPU)
591 vc4_dump_program(c);
592
593 vc4_qpu_validate(c->qpu_insts, c->qpu_inst_count);
594 }