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vc4: Merge qpu_a_NOP() and qpu_m_NOP to a single qpu_NOP() helper.
[mesa.git] / src / gallium / drivers / vc4 / vc4_qpu_emit.c
1 /*
2 * Copyright © 2014 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <inttypes.h>
25
26 #include "vc4_context.h"
27 #include "vc4_qir.h"
28 #include "vc4_qpu.h"
29
30 static void
31 vc4_dump_program(struct qcompile *c)
32 {
33 fprintf(stderr, "%s:\n", qir_get_stage_name(c->stage));
34
35 for (int i = 0; i < c->qpu_inst_count; i++) {
36 fprintf(stderr, "0x%016"PRIx64" ", c->qpu_insts[i]);
37 vc4_qpu_disasm(&c->qpu_insts[i], 1);
38 fprintf(stderr, "\n");
39 }
40 }
41
42 struct queued_qpu_inst {
43 struct simple_node link;
44 uint64_t inst;
45 };
46
47 static void
48 queue(struct qcompile *c, uint64_t inst)
49 {
50 struct queued_qpu_inst *q = calloc(1, sizeof(*q));
51 q->inst = inst;
52 insert_at_tail(&c->qpu_inst_list, &q->link);
53 }
54
55 static uint64_t *
56 last_inst(struct qcompile *c)
57 {
58 struct queued_qpu_inst *q =
59 (struct queued_qpu_inst *)last_elem(&c->qpu_inst_list);
60 return &q->inst;
61 }
62
63 /**
64 * This is used to resolve the fact that we might register-allocate two
65 * different operands of an instruction to the same physical register file
66 * even though instructions have only one field for the register file source
67 * address.
68 *
69 * In that case, we need to move one to a temporary that can be used in the
70 * instruction, instead.
71 */
72 static void
73 fixup_raddr_conflict(struct qcompile *c,
74 struct qpu_reg src0, struct qpu_reg *src1)
75 {
76 if ((src0.mux == QPU_MUX_A || src0.mux == QPU_MUX_B) &&
77 (src1->mux == QPU_MUX_A || src1->mux == QPU_MUX_B) &&
78 src0.addr != src1->addr) {
79 queue(c, qpu_inst(qpu_a_MOV(qpu_r3(), *src1),
80 qpu_NOP()));
81 *src1 = qpu_r3();
82 }
83 }
84
85 static void
86 serialize_one_inst(struct qcompile *c, uint64_t inst)
87 {
88 if (c->qpu_inst_count >= c->qpu_inst_size) {
89 c->qpu_inst_size = MAX2(16, c->qpu_inst_size * 2);
90 c->qpu_insts = realloc(c->qpu_insts,
91 c->qpu_inst_size * sizeof(uint64_t));
92 }
93 c->qpu_insts[c->qpu_inst_count++] = inst;
94 }
95
96 static void
97 serialize_insts(struct qcompile *c)
98 {
99 int last_sfu_write = -10;
100 bool scoreboard_wait_emitted = false;
101
102 while (!is_empty_list(&c->qpu_inst_list)) {
103 struct queued_qpu_inst *q =
104 (struct queued_qpu_inst *)first_elem(&c->qpu_inst_list);
105 uint32_t last_waddr_a = QPU_W_NOP, last_waddr_b = QPU_W_NOP;
106 uint32_t raddr_a = QPU_GET_FIELD(q->inst, QPU_RADDR_A);
107 uint32_t raddr_b = QPU_GET_FIELD(q->inst, QPU_RADDR_B);
108
109 if (c->qpu_inst_count > 0) {
110 uint64_t last_inst = c->qpu_insts[c->qpu_inst_count -
111 1];
112 uint32_t last_waddr_add = QPU_GET_FIELD(last_inst,
113 QPU_WADDR_ADD);
114 uint32_t last_waddr_mul = QPU_GET_FIELD(last_inst,
115 QPU_WADDR_MUL);
116
117 if (last_inst & QPU_WS) {
118 last_waddr_a = last_waddr_mul;
119 last_waddr_b = last_waddr_add;
120 } else {
121 last_waddr_a = last_waddr_add;
122 last_waddr_b = last_waddr_mul;
123 }
124 }
125
126 uint32_t src_muxes[] = {
127 QPU_GET_FIELD(q->inst, QPU_ADD_A),
128 QPU_GET_FIELD(q->inst, QPU_ADD_B),
129 QPU_GET_FIELD(q->inst, QPU_MUL_A),
130 QPU_GET_FIELD(q->inst, QPU_MUL_B),
131 };
132
133 /* "An instruction must not read from a location in physical
134 * regfile A or B that was written to by the previous
135 * instruction."
136 */
137 bool needs_raddr_vs_waddr_nop = false;
138 bool reads_r4 = false;
139 for (int i = 0; i < ARRAY_SIZE(src_muxes); i++) {
140 if ((raddr_a < 32 &&
141 src_muxes[i] == QPU_MUX_A &&
142 last_waddr_a == raddr_a) ||
143 (raddr_b < 32 &&
144 src_muxes[i] == QPU_MUX_B &&
145 last_waddr_b == raddr_b)) {
146 needs_raddr_vs_waddr_nop = true;
147 }
148 if (src_muxes[i] == QPU_MUX_R4)
149 reads_r4 = true;
150 }
151
152 if (needs_raddr_vs_waddr_nop) {
153 serialize_one_inst(c, qpu_NOP());
154 }
155
156 /* "After an SFU lookup instruction, accumulator r4 must not
157 * be read in the following two instructions. Any other
158 * instruction that results in r4 being written (that is, TMU
159 * read, TLB read, SFU lookup) cannot occur in the two
160 * instructions following an SFU lookup."
161 */
162 if (reads_r4) {
163 while (c->qpu_inst_count - last_sfu_write < 3) {
164 serialize_one_inst(c, qpu_NOP());
165 }
166 }
167
168 uint32_t waddr_a = QPU_GET_FIELD(q->inst, QPU_WADDR_ADD);
169 uint32_t waddr_m = QPU_GET_FIELD(q->inst, QPU_WADDR_MUL);
170 if ((waddr_a >= QPU_W_SFU_RECIP && waddr_a <= QPU_W_SFU_LOG) ||
171 (waddr_m >= QPU_W_SFU_RECIP && waddr_m <= QPU_W_SFU_LOG)) {
172 last_sfu_write = c->qpu_inst_count;
173 }
174
175 /* "A scoreboard wait must not occur in the first two
176 * instructions of a fragment shader. This is either the
177 * explicit Wait for Scoreboard signal or an implicit wait
178 * with the first tile-buffer read or write instruction."
179 */
180 if (!scoreboard_wait_emitted &&
181 (waddr_a == QPU_W_TLB_Z || waddr_m == QPU_W_TLB_Z ||
182 waddr_a == QPU_W_TLB_COLOR_MS ||
183 waddr_m == QPU_W_TLB_COLOR_MS ||
184 waddr_a == QPU_W_TLB_COLOR_ALL ||
185 waddr_m == QPU_W_TLB_COLOR_ALL ||
186 QPU_GET_FIELD(q->inst, QPU_SIG) == QPU_SIG_COLOR_LOAD)) {
187 while (c->qpu_inst_count < 3 ||
188 QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
189 QPU_SIG) != QPU_SIG_NONE) {
190 serialize_one_inst(c, qpu_NOP());
191 }
192 c->qpu_insts[c->qpu_inst_count - 1] =
193 qpu_set_sig(c->qpu_insts[c->qpu_inst_count - 1],
194 QPU_SIG_WAIT_FOR_SCOREBOARD);
195 scoreboard_wait_emitted = true;
196 }
197
198 serialize_one_inst(c, q->inst);
199
200 remove_from_list(&q->link);
201 free(q);
202 }
203 }
204
205 void
206 vc4_generate_code(struct qcompile *c)
207 {
208 struct qpu_reg allocate_to_qpu_reg[3 + 32 + 32];
209 bool reg_in_use[ARRAY_SIZE(allocate_to_qpu_reg)];
210 int *reg_allocated = calloc(c->num_temps, sizeof(*reg_allocated));
211 int *reg_uses_remaining =
212 calloc(c->num_temps, sizeof(*reg_uses_remaining));
213 bool discard = false;
214
215 for (int i = 0; i < ARRAY_SIZE(reg_in_use); i++)
216 reg_in_use[i] = false;
217 for (int i = 0; i < c->num_temps; i++)
218 reg_allocated[i] = -1;
219 for (int i = 0; i < 3; i++)
220 allocate_to_qpu_reg[i] = qpu_rn(i);
221 for (int i = 0; i < 32; i++)
222 allocate_to_qpu_reg[i + 3] = qpu_ra(i);
223 for (int i = 0; i < 32; i++)
224 allocate_to_qpu_reg[i + 3 + 32] = qpu_rb(i);
225
226 make_empty_list(&c->qpu_inst_list);
227
228 struct simple_node *node;
229 foreach(node, &c->instructions) {
230 struct qinst *qinst = (struct qinst *)node;
231
232 if (qinst->dst.file == QFILE_TEMP)
233 reg_uses_remaining[qinst->dst.index]++;
234 for (int i = 0; i < qir_get_op_nsrc(qinst->op); i++) {
235 if (qinst->src[i].file == QFILE_TEMP)
236 reg_uses_remaining[qinst->src[i].index]++;
237 }
238 if (qinst->op == QOP_TLB_PASSTHROUGH_Z_WRITE ||
239 qinst->op == QOP_FRAG_Z)
240 reg_in_use[3 + 32 + QPU_R_FRAG_PAYLOAD_ZW] = true;
241 }
242
243 switch (c->stage) {
244 case QSTAGE_VERT:
245 case QSTAGE_COORD:
246 queue(c, qpu_load_imm_ui(qpu_vrsetup(),
247 (0x00001a00 +
248 0x00100000 * c->num_inputs)));
249 queue(c, qpu_load_imm_ui(qpu_vwsetup(), 0x00001a00));
250 break;
251 case QSTAGE_FRAG:
252 break;
253 }
254
255 foreach(node, &c->instructions) {
256 struct qinst *qinst = (struct qinst *)node;
257
258 #if 0
259 fprintf(stderr, "translating qinst to qpu: ");
260 qir_dump_inst(qinst);
261 fprintf(stderr, "\n");
262 #endif
263
264 static const struct {
265 uint32_t op;
266 bool is_mul;
267 } translate[] = {
268 #define A(name) [QOP_##name] = {QPU_A_##name, false}
269 #define M(name) [QOP_##name] = {QPU_M_##name, true}
270 A(FADD),
271 A(FSUB),
272 A(FMIN),
273 A(FMAX),
274 A(FMINABS),
275 A(FMAXABS),
276 A(FTOI),
277 A(ITOF),
278
279 M(FMUL),
280 };
281
282 static const uint32_t compareflags[] = {
283 [QOP_SEQ - QOP_SEQ] = QPU_COND_ZS,
284 [QOP_SNE - QOP_SEQ] = QPU_COND_ZC,
285 [QOP_SLT - QOP_SEQ] = QPU_COND_NS,
286 [QOP_SGE - QOP_SEQ] = QPU_COND_NC,
287 };
288
289 struct qpu_reg src[4];
290 for (int i = 0; i < qir_get_op_nsrc(qinst->op); i++) {
291 int index = qinst->src[i].index;
292 switch (qinst->src[i].file) {
293 case QFILE_NULL:
294 src[i] = qpu_rn(0);
295 break;
296 case QFILE_TEMP:
297 if (reg_allocated[index] == -1) {
298 fprintf(stderr, "undefined reg use: ");
299 qir_dump_inst(qinst);
300 fprintf(stderr, "\n");
301
302 src[i] = qpu_rn(0);
303 } else {
304 src[i] = allocate_to_qpu_reg[reg_allocated[index]];
305 reg_uses_remaining[index]--;
306 if (reg_uses_remaining[index] == 0)
307 reg_in_use[reg_allocated[index]] = false;
308 }
309 break;
310 case QFILE_UNIF:
311 src[i] = qpu_unif();
312 break;
313 case QFILE_VARY:
314 src[i] = qpu_vary();
315 break;
316 }
317 }
318
319 struct qpu_reg dst;
320 switch (qinst->dst.file) {
321 case QFILE_NULL:
322 dst = qpu_ra(QPU_W_NOP);
323 break;
324
325 case QFILE_TEMP:
326 if (reg_allocated[qinst->dst.index] == -1) {
327 int alloc;
328 for (alloc = 0;
329 alloc < ARRAY_SIZE(reg_in_use);
330 alloc++) {
331 /* The pack flags require an A-file register. */
332 if (qinst->op == QOP_PACK_SCALED &&
333 allocate_to_qpu_reg[alloc].mux != QPU_MUX_A) {
334 continue;
335 }
336
337 if (!reg_in_use[alloc])
338 break;
339 }
340 assert(alloc != ARRAY_SIZE(reg_in_use) && "need better reg alloc");
341 reg_in_use[alloc] = true;
342 reg_allocated[qinst->dst.index] = alloc;
343 }
344
345 dst = allocate_to_qpu_reg[reg_allocated[qinst->dst.index]];
346
347 reg_uses_remaining[qinst->dst.index]--;
348 if (reg_uses_remaining[qinst->dst.index] == 0) {
349 reg_in_use[reg_allocated[qinst->dst.index]] =
350 false;
351 }
352 break;
353
354 case QFILE_VARY:
355 case QFILE_UNIF:
356 assert(!"not reached");
357 break;
358 }
359
360 switch (qinst->op) {
361 case QOP_MOV:
362 /* Skip emitting the MOV if it's a no-op. */
363 if (dst.mux == QPU_MUX_A || dst.mux == QPU_MUX_B ||
364 dst.mux != src[0].mux || dst.addr != src[0].addr) {
365 queue(c, qpu_inst(qpu_a_MOV(dst, src[0]),
366 qpu_NOP()));
367 }
368 break;
369
370 case QOP_CMP:
371 queue(c, qpu_inst(qpu_a_MOV(qpu_ra(QPU_W_NOP),
372 src[0]),
373 qpu_NOP()));
374 *last_inst(c) |= QPU_SF;
375
376 if (dst.mux <= QPU_MUX_R3) {
377 fixup_raddr_conflict(c, src[1], &src[2]);
378 queue(c, qpu_inst(qpu_a_MOV(dst, src[1]),
379 qpu_m_MOV(dst, src[2])));
380 *last_inst(c) = qpu_set_cond_add(*last_inst(c),
381 QPU_COND_NS);
382 *last_inst(c) = qpu_set_cond_mul(*last_inst(c),
383 QPU_COND_NC);
384 } else {
385 if (dst.mux == src[1].mux &&
386 dst.addr == src[1].addr) {
387 queue(c, qpu_inst(qpu_a_MOV(dst, src[1]),
388 qpu_NOP()));
389
390 queue(c, qpu_inst(qpu_a_MOV(dst, src[2]),
391 qpu_NOP()));
392 *last_inst(c) = qpu_set_cond_add(*last_inst(c),
393 QPU_COND_NC);
394 } else {
395 queue(c, qpu_inst(qpu_a_MOV(dst, src[2]),
396 qpu_NOP()));
397
398 queue(c, qpu_inst(qpu_a_MOV(dst, src[1]),
399 qpu_NOP()));
400 *last_inst(c) = qpu_set_cond_add(*last_inst(c),
401 QPU_COND_NS);
402 }
403 }
404 break;
405
406 case QOP_SEQ:
407 case QOP_SNE:
408 case QOP_SGE:
409 case QOP_SLT:
410 fixup_raddr_conflict(c, src[0], &src[1]);
411 queue(c, qpu_inst(qpu_a_FSUB(qpu_ra(QPU_W_NOP),
412 src[0], src[1]),
413 qpu_NOP()));
414 *last_inst(c) |= QPU_SF;
415
416 queue(c, qpu_load_imm_f(dst, 0.0));
417 queue(c, qpu_load_imm_f(dst, 1.0));
418 *last_inst(c) = qpu_set_cond_add(*last_inst(c),
419 compareflags[qinst->op - QOP_SEQ]);
420
421
422 break;
423
424 case QOP_VPM_WRITE:
425 queue(c, qpu_inst(qpu_a_MOV(qpu_ra(QPU_W_VPM), src[0]),
426 qpu_NOP()));
427 break;
428
429 case QOP_VPM_READ:
430 queue(c, qpu_inst(qpu_a_MOV(dst, qpu_ra(QPU_R_VPM)),
431 qpu_NOP()));
432 break;
433
434 case QOP_RCP:
435 case QOP_RSQ:
436 case QOP_EXP2:
437 case QOP_LOG2:
438 switch (qinst->op) {
439 case QOP_RCP:
440 queue(c, qpu_inst(qpu_a_MOV(qpu_rb(QPU_W_SFU_RECIP),
441 src[0]),
442 qpu_NOP()));
443 break;
444 case QOP_RSQ:
445 queue(c, qpu_inst(qpu_a_MOV(qpu_rb(QPU_W_SFU_RECIPSQRT),
446 src[0]),
447 qpu_NOP()));
448 break;
449 case QOP_EXP2:
450 queue(c, qpu_inst(qpu_a_MOV(qpu_rb(QPU_W_SFU_EXP),
451 src[0]),
452 qpu_NOP()));
453 break;
454 case QOP_LOG2:
455 queue(c, qpu_inst(qpu_a_MOV(qpu_rb(QPU_W_SFU_LOG),
456 src[0]),
457 qpu_NOP()));
458 break;
459 default:
460 abort();
461 }
462
463 queue(c, qpu_inst(qpu_a_MOV(dst, qpu_r4()),
464 qpu_NOP()));
465
466 break;
467
468 case QOP_PACK_COLORS:
469 for (int i = 0; i < 4; i++) {
470 queue(c, qpu_inst(qpu_NOP(),
471 qpu_m_MOV(qpu_r3(), src[i])));
472 *last_inst(c) |= QPU_PM;
473 *last_inst(c) |= QPU_SET_FIELD(QPU_PACK_MUL_8A + i,
474 QPU_PACK);
475 }
476
477 queue(c, qpu_inst(qpu_a_MOV(dst, qpu_r3()),
478 qpu_NOP()));
479
480 break;
481
482 case QOP_FRAG_X:
483 queue(c, qpu_inst(qpu_a_ITOF(dst,
484 qpu_ra(QPU_R_XY_PIXEL_COORD)),
485 qpu_NOP()));
486 break;
487
488 case QOP_FRAG_Y:
489 queue(c, qpu_inst(qpu_a_ITOF(dst,
490 qpu_rb(QPU_R_XY_PIXEL_COORD)),
491 qpu_NOP()));
492 break;
493
494 case QOP_FRAG_Z:
495 queue(c, qpu_inst(qpu_a_ITOF(dst,
496 qpu_rb(QPU_R_FRAG_PAYLOAD_ZW)),
497 qpu_NOP()));
498 break;
499
500 case QOP_FRAG_RCP_W:
501 queue(c, qpu_inst(qpu_a_MOV(qpu_rb(QPU_W_SFU_RECIP),
502 qpu_ra(QPU_R_FRAG_PAYLOAD_ZW)),
503 qpu_NOP()));
504
505 queue(c, qpu_inst(qpu_a_MOV(dst, qpu_r4()),
506 qpu_NOP()));
507 break;
508
509 case QOP_TLB_DISCARD_SETUP:
510 discard = true;
511 queue(c, qpu_inst(qpu_a_MOV(src[0], src[0]),
512 qpu_NOP()));
513 *last_inst(c) |= QPU_SF;
514 break;
515
516 case QOP_TLB_PASSTHROUGH_Z_WRITE:
517 queue(c, qpu_inst(qpu_a_MOV(qpu_ra(QPU_W_TLB_Z),
518 qpu_rb(QPU_R_FRAG_PAYLOAD_ZW)),
519 qpu_NOP()));
520 if (discard) {
521 *last_inst(c) = qpu_set_cond_add(*last_inst(c),
522 QPU_COND_ZS);
523 }
524 break;
525
526 case QOP_TLB_COLOR_READ:
527 queue(c, qpu_NOP());
528 *last_inst(c) = qpu_set_sig(*last_inst(c),
529 QPU_SIG_COLOR_LOAD);
530
531 break;
532
533 case QOP_TLB_COLOR_WRITE:
534 queue(c, qpu_inst(qpu_a_MOV(qpu_tlbc(),
535 src[0]),
536 qpu_NOP()));
537 if (discard) {
538 *last_inst(c) = qpu_set_cond_add(*last_inst(c),
539 QPU_COND_ZS);
540 }
541 break;
542
543 case QOP_VARY_ADD_C:
544 queue(c, qpu_inst(qpu_a_FADD(dst,
545 src[0], qpu_r5()),
546 qpu_NOP()));
547 break;
548
549 case QOP_PACK_SCALED: {
550 uint64_t a = (qpu_inst(qpu_a_MOV(dst, src[0]),
551 qpu_NOP()) |
552 QPU_SET_FIELD(QPU_PACK_A_16A,
553 QPU_PACK));
554 uint64_t b = (qpu_inst(qpu_a_MOV(dst, src[1]),
555 qpu_NOP()) |
556 QPU_SET_FIELD(QPU_PACK_A_16B,
557 QPU_PACK));
558
559 if (dst.mux == src[1].mux && dst.addr == src[1].addr) {
560 queue(c, b);
561 queue(c, a);
562 } else {
563 queue(c, a);
564 queue(c, b);
565 }
566 break;
567 }
568
569 case QOP_TEX_S:
570 case QOP_TEX_T:
571 case QOP_TEX_R:
572 case QOP_TEX_B:
573 queue(c, qpu_inst(qpu_a_MOV(qpu_rb(QPU_W_TMU0_S +
574 (qinst->op -
575 QOP_TEX_S)),
576 src[0]),
577 qpu_NOP()));
578 break;
579
580 case QOP_TEX_RESULT:
581 queue(c, qpu_NOP());
582 *last_inst(c) = qpu_set_sig(*last_inst(c),
583 QPU_SIG_LOAD_TMU0);
584
585 break;
586
587 case QOP_R4_UNPACK_A:
588 case QOP_R4_UNPACK_B:
589 case QOP_R4_UNPACK_C:
590 case QOP_R4_UNPACK_D:
591 queue(c, qpu_inst(qpu_a_MOV(dst, qpu_r4()),
592 qpu_NOP()));
593 *last_inst(c) |= QPU_PM;
594 *last_inst(c) |= QPU_SET_FIELD(QPU_UNPACK_R4_8A +
595 (qinst->op -
596 QOP_R4_UNPACK_A),
597 QPU_UNPACK);
598
599 break;
600
601 default:
602 assert(qinst->op < ARRAY_SIZE(translate));
603 assert(translate[qinst->op].op != 0); /* NOPs */
604
605 /* If we have only one source, put it in the second
606 * argument slot as well so that we don't take up
607 * another raddr just to get unused data.
608 */
609 if (qir_get_op_nsrc(qinst->op) == 1)
610 src[1] = src[0];
611
612 fixup_raddr_conflict(c, src[0], &src[1]);
613
614 if (translate[qinst->op].is_mul) {
615 queue(c, qpu_inst(qpu_NOP(),
616 qpu_m_alu2(translate[qinst->op].op,
617 dst,
618 src[0], src[1])));
619 } else {
620 queue(c, qpu_inst(qpu_a_alu2(translate[qinst->op].op,
621 dst,
622 src[0], src[1]),
623 qpu_NOP()));
624 }
625 break;
626 }
627 }
628
629 serialize_insts(c);
630
631 /* thread end can't have VPM write */
632 if (QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
633 QPU_WADDR_ADD) == QPU_W_VPM ||
634 QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
635 QPU_WADDR_MUL) == QPU_W_VPM) {
636 serialize_one_inst(c, qpu_NOP());
637 }
638
639 c->qpu_insts[c->qpu_inst_count - 1] =
640 qpu_set_sig(c->qpu_insts[c->qpu_inst_count - 1],
641 QPU_SIG_PROG_END);
642 serialize_one_inst(c, qpu_NOP());
643 serialize_one_inst(c, qpu_NOP());
644
645 switch (c->stage) {
646 case QSTAGE_VERT:
647 case QSTAGE_COORD:
648 break;
649 case QSTAGE_FRAG:
650 c->qpu_insts[c->qpu_inst_count - 1] =
651 qpu_set_sig(c->qpu_insts[c->qpu_inst_count - 1],
652 QPU_SIG_SCOREBOARD_UNLOCK);
653 break;
654 }
655
656 if (vc4_debug & VC4_DEBUG_QPU)
657 vc4_dump_program(c);
658
659 vc4_qpu_validate(c->qpu_insts, c->qpu_inst_count);
660 }